coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: amd/pi/00670F00: Add generic romstage
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18495 -gerrit commit aaa52be97f48f7cb9708be3c45ecf545c32b672a Author: Marc Jones <marcj303(a)gmail.com> Date: Thu Feb 23 11:39:50 2017 -0700 amd/pi/00670F00: Add generic romstage Move the generic romstage code to the Stoney Ridge cpu. Change-Id: If66ac0e4b3c088f138b9282546ed1ec2d861dd74 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00670F00/Makefile.inc | 1 + src/cpu/amd/pi/00670F00/romstage.c | 56 +++++++++++++++++++++++++++++++++++ src/cpu/amd/pi/00670F00/romstage.h | 17 +++++++++++ src/mainboard/amd/gardenia/romstage.c | 36 ++-------------------- 4 files changed, 77 insertions(+), 33 deletions(-) diff --git a/src/cpu/amd/pi/00670F00/Makefile.inc b/src/cpu/amd/pi/00670F00/Makefile.inc index 6c6a2b8..ae10485 100644 --- a/src/cpu/amd/pi/00670F00/Makefile.inc +++ b/src/cpu/amd/pi/00670F00/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c ramstage-y += model_15_init.c diff --git a/src/cpu/amd/pi/00670F00/romstage.c b/src/cpu/amd/pi/00670F00/romstage.c new file mode 100644 index 0000000..e305a05 --- /dev/null +++ b/src/cpu/amd/pi/00670F00/romstage.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> +#include <cpu/amd/pi/00670F00/romstage.h> +#include <console/console.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <program_loading.h> + +void cache_as_ram_stage_main(void) +{ + post_code(0x37); + mainboard_romstage_entry(); + + post_code(0x49); + disable_cache_as_ram(); + + post_code(0x50); + run_ramstage(); + post_code(0x54); /* Should never see this post code. */ + die("ERROR - Failed to load ramstage!"); +} + +/* Entry from the mainboard. */ +void romstage_common(void) +{ + post_code(0x38); + AGESAWRAPPER(amdinitreset); + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); + + post_code(0x39); + AGESAWRAPPER(amdinitearly); + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + post_code(0x41); + AGESAWRAPPER(amdinitenv); +} diff --git a/src/cpu/amd/pi/00670F00/romstage.h b/src/cpu/amd/pi/00670F00/romstage.h new file mode 100644 index 0000000..79e6863 --- /dev/null +++ b/src/cpu/amd/pi/00670F00/romstage.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void mainboard_romstage_entry(void); +void romstage_common(void); diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 940b51a..22f079e 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -13,39 +13,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cpu/amd/car.h> -#include <cpu/amd/pi/car.h> -#include <northbridge/amd/pi/agesawrapper.h> -#include <northbridge/amd/pi/agesawrapper_call.h> -#include <southbridge/amd/pi/hudson/hudson.h> +#include <cpu/amd/pi/00670F00/romstage.h> -void cache_as_ram_stage_main(void) +void mainboard_romstage_entry(void) { - - // TODO: Move all generic functions to PI generic romstage - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - AGESAWRAPPER(amdinitenv); - - disable_cache_as_ram(); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + romstage_common(); }

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New patch to review for coreboot: mainboard/amd/gardenia: Remove S3 support
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18494 -gerrit commit 7a6374488d0aefbefffeea8f42f07d15683820b6 Author: Marc Jones <marcj303(a)gmail.com> Date: Thu Feb 23 22:06:01 2017 -0700 mainboard/amd/gardenia: Remove S3 support S3 is not yet supported for Stoney Ridge. Remove it until the support is written. Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/mainboard.c | 3 --- src/mainboard/amd/gardenia/romstage.c | 32 +++++++------------------------- 2 files changed, 7 insertions(+), 28 deletions(-) diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 7ebe087..acc9b7c 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -84,9 +84,6 @@ static void gardenia_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 1d2d05b..940b51a 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -19,48 +19,30 @@ #include <arch/stages.h> #include <cpu/amd/car.h> #include <cpu/amd/pi/car.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> void cache_as_ram_stage_main(void) { -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif + // TODO: Move all generic functions to PI generic romstage post_code(0x37); AGESAWRAPPER(amdinitreset); + post_code(0x38); printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); + post_code(0x40); + AGESAWRAPPER(amdinitpost); - post_code(0x61); - prepare_for_resume(); - } + post_code(0x41); + AGESAWRAPPER(amdinitenv); - if (s3resume || acpi_is_wakeup_s4()) { - outb(0xEE, PM_INDEX); - outb(0x8, PM_DATA); - } + disable_cache_as_ram(); post_code(0x50); copy_and_run();

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New patch to review for coreboot: amd/pi/hudson/acpi: Only declare S3 if it is supported
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18493 -gerrit commit 1c1eded5c30db113d35e5caa15cf187485501072 Author: Marc Jones <marcj303(a)gmail.com> Date: Wed Feb 22 16:21:49 2017 -0700 amd/pi/hudson/acpi: Only declare S3 if it is supported Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME is set. Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/acpi/sleepstates.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl index 912c0df..d93f068 100644 --- a/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl +++ b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl @@ -23,9 +23,11 @@ If (LAnd(SSFG, 0x01)) { If (LAnd(SSFG, 0x02)) { Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } +#if CONFIG_HAVE_ACPI_RESUME If (LAnd(SSFG, 0x04)) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ } +#endif If (LAnd(SSFG, 0x08)) { Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ }

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New patch to review for coreboot: vendorcode/amd/pi/00670F00: cleanup CAR disable
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18492 -gerrit commit 8b72a5e201f71e5c5cf6647c5892ac74d40501bb Author: Marc Jones <marcj303(a)gmail.com> Date: Fri Feb 24 16:40:41 2017 -0700 vendorcode/amd/pi/00670F00: cleanup CAR disable Clean up the AMD_DISABLE_STACK_FAMILY_HOOK_F15 to be clear that it does a wbinvd to preserve the coreboot stack and CAR globals. The Stoney Ridge uses a different S3 architecture, so this is not an issue of reserving or relocting the stack on a resume. Change-Id: I77e53262212e00bce9145b0bc3909ad8651f2328 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc | 24 ++++++++++++++-------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc index d6782a3..ac15134 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc @@ -401,6 +401,14 @@ fam15_enable_stack_hook_exit: * Return any family specific controls to their 'standard' * settings for using cache with main memory. * +* Note: Customized for coreboot: +* A wbinvd is used to send cache to memory to preserve stack and +* coreboot CAR globals. This should NOT be used with S3 resume IF the +* stack/cache area is not reserved and over system memory. +* +* This CPU resume path doesn't use CAR, but be careful if porting to +* other CPUs. +* * Inputs: * ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# * Outputs: @@ -634,11 +642,13 @@ fam15_disable_stack_remote_read_exit: # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. #-------------------------------------------------------------------------- - mov $HWCR, %ecx # MSR:C001_0015h - _RDMSR - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR - wbinvd #bao # Clear the cache tag RAMs + #-------------------------------------------------------------------------- + # Send cache to memory. Preserve stack and coreboot car globals. + # This shouldn't be used with S3 resume IF the stack/cache area is + # not reserved and over system memory. + #-------------------------------------------------------------------------- + wbinvd # Clear the cache tag RAMs + # #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? # cmp $01, %bh # jz 4f @@ -659,10 +669,6 @@ fam15_disable_stack_remote_read_exit: 1: #.endif #Do Standard Family 15 work - mov $HWCR, %ecx # MSR:C001_0015h - _RDMSR - bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD - _WRMSR #.endif # end 0: //

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Patch set updated for coreboot: amd/gardenia: Add early_mainboard.c file
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18443 -gerrit commit b0f0792a32e7226e0b633868c44814bbcefc1b77 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Feb 14 17:18:45 2017 -0700 amd/gardenia: Add early_mainboard.c file Add a file that can speed up the SPI interface to match the populated SPI flash. The board uses an MX25U6435F. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit cfda0166302d2c89aa09d95df84b97eb49b1f4fd) Change-Id: Ibbad1391fb128249a58caa9358ecb5e0ca6382aa Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/Makefile.inc | 3 +++ src/mainboard/amd/gardenia/early_mainboard.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index 72cd042..43c5a04 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -19,3 +19,6 @@ romstage-y += OemCustomize.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c + +verstage-y += early_mainboard.c +romstage-y += early_mainboard.c diff --git a/src/mainboard/amd/gardenia/early_mainboard.c b/src/mainboard/amd/gardenia/early_mainboard.c new file mode 100644 index 0000000..e89484b --- /dev/null +++ b/src/mainboard/amd/gardenia/early_mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pci_def.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/pi/car.h> +#include <southbridge/amd/pi/hudson/hudson.h> + +void car_mainboard_pre_console_init(void) +{ + hudson_set_spi100(SPI_SPEED_33M, + SPI_SPEED_66M, SPI_SPEED_16M, SPI_SPEED_16M); + hudson_disable_4dw_burst(); + hudson_read_mode(SPI_READ_MODE_QUAD114); +}

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Patch set updated for coreboot: amd/pi: Add verstage support
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18439 -gerrit commit 77ff9157e63805c414424f8393d26283508e170e Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Feb 9 16:19:34 2017 -0700 amd/pi: Add verstage support This patch takes hints from the work in commits 75c51d9 and 909c512. Give PI-based systems the capability of running a SEPARATE_VERSTAGE. This adds * A verstage.c file to that initiates loading romstage (and verification) * A new entry point in car.c that will be used when there is a separate verstage * Makefile flags and verstage-y additions for cpu and southbridge * Besides AMD binary-PI changes, the x86 lapic timer is also now included into verstage This has been tested on Stoney (00670F000) and Gardenia. Although additional APUs' makefiles are modified, none of those platforms are assumed to support verstage at this time. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 15ce30cbd9d20aa0f5a5516e5f3bee7eab069852) Change-Id: Ie43d87908c2d83b42b95b306419156e85993f7bd Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00630F01/Makefile.inc | 1 + src/cpu/amd/pi/00660F01/Makefile.inc | 1 + src/cpu/amd/pi/00670F00/Makefile.inc | 1 + src/cpu/amd/pi/00730F01/Makefile.inc | 1 + src/cpu/amd/pi/Makefile.inc | 4 ++++ src/cpu/amd/pi/car.c | 6 ++++++ src/cpu/amd/pi/car.h | 3 +++ src/cpu/amd/pi/romstage_after_verstage.S | 23 +++++++++++++++++++++++ src/cpu/amd/pi/verstage.c | 23 +++++++++++++++++++++++ src/cpu/x86/lapic/Makefile.inc | 1 + src/southbridge/amd/pi/hudson/Makefile.inc | 3 +++ src/vendorcode/amd/pi/Makefile.inc | 2 ++ 12 files changed, 69 insertions(+) diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index 98a7050..9dce0a8 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +verstage-y += fixme.c romstage-y += fixme.c ramstage-y += fixme.c diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc index 6c6a2b8..acaf1f4 100644 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ b/src/cpu/amd/pi/00660F01/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +verstage-y += fixme.c romstage-y += fixme.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/pi/00670F00/Makefile.inc b/src/cpu/amd/pi/00670F00/Makefile.inc index ae10485..601e062 100644 --- a/src/cpu/amd/pi/00670F00/Makefile.inc +++ b/src/cpu/amd/pi/00670F00/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +verstage-y += fixme.c romstage-y += fixme.c romstage-y += romstage.c ramstage-y += fixme.c diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 9367b45..57cabb3 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +verstage-y += fixme.c romstage-y += fixme.c ramstage-y += fixme.c diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index ce60833..972c11d 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -18,7 +18,11 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 +verstage-y += verstage.c +verstage-y += car.c + romstage-y += car.c +romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S romstage-y += s3_resume.c ramstage-y += s3_resume.c diff --git a/src/cpu/amd/pi/car.c b/src/cpu/amd/pi/car.c index 62c5338..f66f94f 100644 --- a/src/cpu/amd/pi/car.c +++ b/src/cpu/amd/pi/car.c @@ -66,6 +66,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cache_as_ram_stage_main(); } +void romstage_after_verstage(void) +{ + /* This does not return. */ + cache_as_ram_stage_main(); +} + unsigned long __attribute__((weak)) car_bist_mask_bist(unsigned long bist) { return bist; diff --git a/src/cpu/amd/pi/car.h b/src/cpu/amd/pi/car.h index 98da75d..fdf1420 100644 --- a/src/cpu/amd/pi/car.h +++ b/src/cpu/amd/pi/car.h @@ -17,6 +17,9 @@ #ifndef PI_SPLIT_CAR_H #define PI_SPLIT_CAR_H +/* Entry points from the cache-as-ram assembly code */ +void romstage_after_verstage(void); + /* Early initialization immediately after CAR setup */ void cache_as_ram_stage_main(void); diff --git a/src/cpu/amd/pi/romstage_after_verstage.S b/src/cpu/amd/pi/romstage_after_verstage.S new file mode 100644 index 0000000..a89c20a --- /dev/null +++ b/src/cpu/amd/pi/romstage_after_verstage.S @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "gcccar.inc" + +.text +.global car_stage_entry +car_stage_entry: + call romstage_after_verstage + + #include "after_raminit.S" diff --git a/src/cpu/amd/pi/verstage.c b/src/cpu/amd/pi/verstage.c new file mode 100644 index 0000000..c8551dd --- /dev/null +++ b/src/cpu/amd/pi/verstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/pi/car.h> +#include <program_loading.h> + +void cache_as_ram_stage_main(void) +{ + run_romstage(); + /* Will not return to here. */ +} diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9df2c5f..58f67b2 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S +verstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 2153c62..4bd599b 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -42,8 +42,10 @@ ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c +verstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +verstage-y += early_setup.c romstage-y += early_setup.c ifeq ($(CONFIG_HUDSON_IMC_FWM), y) romstage-y += imc.c @@ -51,6 +53,7 @@ ramstage-y += imc.c endif ifeq ($(CONFIG_HUDSON_UART), y) +verstage-y += uart.c romstage-y += uart.c ramstage-y += uart.c endif diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 2cd18c1..b782540 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -77,6 +77,7 @@ export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) +CC_verstage := $(CC_verstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) @@ -139,6 +140,7 @@ $(obj)/agesa/libagesa.a: $(call src-to-obj,libagesa,$(agesa_src_files)) @printf " AGESA $(subst $(obj)/,,$(@))\n" ar rcs $@ $+ +verstage-libs += $(obj)/agesa/libagesa.a romstage-libs += $(obj)/agesa/libagesa.a ramstage-libs += $(obj)/agesa/libagesa.a

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Patch set updated for coreboot: cpu/amd/pi: Change wrapper to use config option
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18438 -gerrit commit bf937343c3d42bb424b59480d502232c29581994 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Jan 25 15:23:47 2017 -0700 cpu/amd/pi: Change wrapper to use config option Add a check for vboot when locating the binaryPI image. There is currently an ordering problem using cbmem to locate the image when vboot is present. Vboot inserts its locator into the search process so that memory can be checked before flash is queried. For the earliest calls using the wrapper, DRAM has not been set up and cbmem not initialized in romstage. This change prevents an endless loop when vboot searches cbmem. This change has another side effect. When vboot is in effect, the change forces the RO binaryPI to be used even when on either of the RW paths. There is currently no ability to relocate the XIP image for use in a RW region. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474) Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/agesawrapper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 0fe8eab..543aa80 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -603,8 +603,14 @@ const void *agesawrapper_locate_module (const CHAR8 name[8]) const AMD_MODULE_HEADER* module; size_t file_size; +#if IS_ENABLED(CONFIG_VBOOT) + /* Use phys. location in flash and prevent vboot from searching cbmem */ + agesa = (void *)CONFIG_AGESA_BINARY_PI_LOCATION; + file_size = 0x100000; +#else agesa = cbfs_boot_map_with_leak((const char *)CONFIG_CBFS_AGESA_NAME, CBFS_TYPE_RAW, &file_size); +#endif if (!agesa) return NULL; image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name);

1 0

Patch set updated for coreboot: cpu/amd/pi: Split CAR setup for use in multiple stages
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18437 -gerrit commit 62d5dfd2bbdf6045618a957500a2ca10eecea48c Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Jan 17 11:57:31 2017 -0500 cpu/amd/pi: Split CAR setup for use in multiple stages This patch uses hints from commit e6af4be to make CAR setup more standalone. These changes will facilitate establishing CAR outside of romstage in an upcoming separate verstage patch. Move CAR teardown to its own file that will always be in romstage, but isn't required in an earlier stage. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit c648d2a0f88ac1161f5d2002f7b947cb8e56b03f) Change-Id: I9fe53ca1fd6b1edd4d5e072849f3962c8bc95df0 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/after_raminit.S | 49 +++++++++++++++++++++++++++++++++++++++++ src/cpu/amd/pi/cache_as_ram.inc | 33 +++++---------------------- 2 files changed, 54 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/pi/after_raminit.S b/src/cpu/amd/pi/after_raminit.S new file mode 100644 index 0000000..79cf59b --- /dev/null +++ b/src/cpu/amd/pi/after_raminit.S @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/cache.h> + +/* + * This is the common entry point after DRAM has been initialized. + */ +.global disable_cache_as_ram +disable_cache_as_ram: + /* Save return stack */ + movd 0(%esp), %xmm1 + movd %esp, %xmm0 + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + xorl %eax, %eax + + /* Restore the return stack */ + wbinvd + movd %xmm0, %esp + movd %xmm1, (%esp) + ret + +cache_as_ram_setup_out: +#ifdef __x86_64__ +.code64 +#endif diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index 24db600..0915c23 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -33,7 +33,7 @@ */ .code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out +.globl cache_as_ram_setup cache_as_ram_setup: @@ -136,31 +136,8 @@ cache_as_ram_setup: stop: jmp stop -disable_cache_as_ram: - /* Save return stack */ - movd 0(%esp), %xmm1 - movd %esp, %xmm0 - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - AMD_DISABLE_STACK - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - xorl %eax, %eax - - /* Restore the return stack */ - wbinvd - movd %xmm0, %esp - movd %xmm1, (%esp) - ret - -cache_as_ram_setup_out: -#ifdef __x86_64__ -.code64 +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after RAM init. */ +#if !ENV_VERSTAGE +#include "after_raminit.S" #endif

1 0

Patch set updated for coreboot: amd/pi/stoney: Change to early cbmem init
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18433 -gerrit commit 155ba75b0d214e4394d4affe0c161ae6ef93bc84 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 29 18:27:02 2017 -0700 amd/pi/stoney: Change to early cbmem init Remove the flexibility of using early or late cbmem init. Use early 100% of the time. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 4c1b4615516dfbd46a768968c2be017cdeb51ee4) Change-Id: Id1c22a15752a07eebf39530ba8549ef1f74265ec Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00670F00/romstage.c | 3 +++ src/northbridge/amd/pi/00670F00/Kconfig | 2 +- src/northbridge/amd/pi/00670F00/memmap.c | 13 ------------- src/northbridge/amd/pi/00670F00/northbridge.c | 9 --------- 4 files changed, 4 insertions(+), 23 deletions(-) diff --git a/src/cpu/amd/pi/00670F00/romstage.c b/src/cpu/amd/pi/00670F00/romstage.c index e305a05..79fb351 100644 --- a/src/cpu/amd/pi/00670F00/romstage.c +++ b/src/cpu/amd/pi/00670F00/romstage.c @@ -52,5 +52,8 @@ void romstage_common(void) AGESAWRAPPER(amdinitpost); post_code(0x41); + cbmem_initialize_empty(); + + post_code(0x42); AGESAWRAPPER(amdinitenv); } diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig index c8ce668..b47a3e6 100644 --- a/src/northbridge/amd/pi/00670F00/Kconfig +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -14,7 +14,7 @@ ## config NORTHBRIDGE_AMD_PI_00670F00 bool - select LATE_CBMEM_INIT + select EARLY_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00670F00 diff --git a/src/northbridge/amd/pi/00670F00/memmap.c b/src/northbridge/amd/pi/00670F00/memmap.c index 02bfc13..982ea62 100644 --- a/src/northbridge/amd/pi/00670F00/memmap.c +++ b/src/northbridge/amd/pi/00670F00/memmap.c @@ -82,20 +82,7 @@ uint32_t uma_base_auto(void) return (uint32_t)topmem - uma_size_auto(); } -#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) -unsigned long get_top_of_ram(void) -{ - AMD_CONFIG_PARAMS StdHeader; - UINT64 MsrReg; - - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - return (unsigned long)MsrReg; -} -#endif - -#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT) void *cbmem_top(void) { return (void *)uma_base_auto(); } -#endif diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 69478d6..e1b3862 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -805,16 +805,7 @@ static void domain_set_resources(device_t dev) ramtop = limitk * 1024; } -#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) -#if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(ramtop); -#endif -#else /* IS_ENABLED(CONFIG_LATE_CBMEM_INIT) */ - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#endif for (link = dev->link_list; link; link = link->next) { if (link->children) {

1 0

Patch set updated for coreboot: amd/northbridge/pi: Move CBMEM_INIT to subdirectories
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18432 -gerrit commit 0a3558039cd0013cf41f8314cfcddc2f9df3d5e1 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Feb 8 08:54:16 2017 -0700 amd/northbridge/pi: Move CBMEM_INIT to subdirectories Split the blanket select for LATE_CBMEM_INIT into individual directories. This allows supporting EARLY as it becomes available in any APU generation. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 017b8fa6e9bb76c55ddc8ca73db683996f6fecee) Change-Id: I144bf34f6f4379eba6a0ae2403bbe97a7df11d8b Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00630F01/Kconfig | 1 + src/northbridge/amd/pi/00660F01/Kconfig | 1 + src/northbridge/amd/pi/00670F00/Kconfig | 1 + src/northbridge/amd/pi/00730F01/Kconfig | 1 + src/northbridge/amd/pi/Kconfig | 1 - 5 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 3669826..0dd2058 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_PI_00630F01 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00630F01 diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig index fdae80f..dc0d870 100644 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_PI_00660F01 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00660F01 diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig index a92658a..c8ce668 100644 --- a/src/northbridge/amd/pi/00670F00/Kconfig +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_PI_00670F00 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00670F00 diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 47c2323..57d6520 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -15,6 +15,7 @@ ## config NORTHBRIDGE_AMD_PI_00730F01 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00730F01 diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index f5f36f8..08327b5 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_AMD_PI bool default CPU_AMD_PI - select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI

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coreboot-gerrit February 2017