coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mb/apple/macbook21: Remove PCI reset code from romstage
by Mono Moosbart 26 Feb '17

26 Feb '17

Mono Moosbart (mono-for-coreboot(a)donderklumpen.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18502 -gerrit commit 7e2330a08567f33b7109033f1dbcc0203a1ed1ef Author: Mono <mono-for-coreboot(a)donderklumpen.de> Date: Sun Feb 26 13:35:17 2017 +0100 mb/apple/macbook21: Remove PCI reset code from romstage Follow commit 7676730 (mb/lenovo/x60: Remove PCI reset code from romstage). The PCI reset was copied from code specific for Roda RK886EX and Kontron 986LCD-M. It is not needed on the MacBook. Change-Id: I22dac962e8079732591f9bc134c1433f5c29ff4e Signed-off-by: Axel Holewa <mono-for-coreboot(a)donderklumpen.de> --- src/mainboard/apple/macbook21/romstage.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 962ad41..92dfe74 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -253,11 +253,6 @@ void mainboard_romstage_entry(unsigned long bist) if (bist == 0) enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - ich7_enable_lpc(); /* Set up the console */

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Patch set updated for coreboot: UNTESTED libpayload: Use interrupt transfers for USB hubs
by Nico Huber 26 Feb '17

26 Feb '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18499 -gerrit commit febf939e2d202646762ec452527baae43ac8efe7 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Jun 12 16:06:08 2013 +0200 UNTESTED libpayload: Use interrupt transfers for USB hubs In interactive payloads, the USB stack's poll procedure is implicitly called from the UI loop. Since all USB control transfers are handled synchronously, polling hubs with these slows the UI significantly down. So switch to interrupt transfers that are done asynchronously and only perform control transfers when the hub reported a status change. Change-Id: I5af02d63e4b8e1451b160b77f3611b93658a7a48 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- payloads/libpayload/drivers/usb/usbhub.c | 115 ++++++++++++++++++++++++++++--- 1 file changed, 107 insertions(+), 8 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index f75141e..5763ba8 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -35,15 +35,33 @@ /* assume that host_to_device is overwritten if necessary */ #define DR_PORT gen_bmRequestType(host_to_device, class_type, other_recp) /* status (and status change) bits */ -#define PORT_CONNECTION 0x1 -#define PORT_ENABLE 0x2 -#define PORT_RESET 0x10 +#define PORT_CONNECTION 0x01 +#define PORT_ENABLE 0x02 +#define PORT_SUSPEND 0x04 +#define PORT_OVER_CURRENT 0x08 +#define PORT_RESET 0x10 /* feature selectors (for setting / clearing features) */ -#define SEL_PORT_RESET 0x4 -#define SEL_PORT_POWER 0x8 -#define SEL_C_PORT_CONNECTION 0x10 +#define SEL_PORT_RESET 0x04 +#define SEL_PORT_POWER 0x08 +#define SEL_C_PORT_CONNECTION 0x10 +#define SEL_C_PORT_ENABLE 0x11 +#define SEL_C_PORT_SUSPEND 0x12 +#define SEL_C_PORT_OVER_CURRENT 0x13 +#define SEL_C_PORT_RESET 0x14 /* request type (USB 3.0 hubs only) */ -#define SET_HUB_DEPTH 12 +#define SET_HUB_DEPTH 12 + +static endpoint_t * +usb_hub_interrupt_ep(usbdev_t *const dev) +{ + int i; + for (i = 0; i < dev->num_endp; ++i) { + if (dev->endpoints[i].type == INTERRUPT && + dev->endpoints[i].direction == IN) + return &dev->endpoints[i]; + } + return NULL; +} static int usb_hub_port_status_changed(usbdev_t *const dev, const int port) @@ -158,9 +176,71 @@ static const generic_hub_ops_t usb_hub_ops = { .reset_port = generic_hub_resetport, }; +static int +usb_hub_handle_port_change(usbdev_t *const dev, const int port) +{ + unsigned short buf[2] = { 0, 0 }; + get_status(dev, port, DR_PORT, 4, buf); + + /* + * Second word holds the change bits. The interrupt transfer shows + * a logical or of these bits, so we have to clear them all. + */ + if (buf[1] & PORT_CONNECTION) { + clear_feature(dev, port, SEL_C_PORT_CONNECTION, DR_PORT); + usb_debug("usbhub: Port change at %d\n", port); + const int ret = generic_hub_scanport(dev, port); + if (ret < 0) + return ret; + } + if (buf[1] & PORT_ENABLE) + clear_feature(dev, port, SEL_C_PORT_ENABLE, DR_PORT); + if (buf[1] & PORT_SUSPEND) + clear_feature(dev, port, SEL_C_PORT_SUSPEND, DR_PORT); + if (buf[1] & PORT_OVER_CURRENT) + clear_feature(dev, port, SEL_C_PORT_OVER_CURRENT, DR_PORT); + if (buf[1] & PORT_RESET) + clear_feature(dev, port, SEL_C_PORT_RESET, DR_PORT); + if (buf[1] & ~(PORT_CONNECTION | PORT_ENABLE | + PORT_SUSPEND | PORT_OVER_CURRENT | PORT_RESET)) + usb_debug("usbhub: Spurious change bit at port %d\n", port); + return 0; +} + +static void +usb_hub_poll(usbdev_t *const dev) +{ + int port; + const u8 *buf; + while ((buf = dev->controller->poll_intr_queue(GEN_HUB(dev)->data))) { + for (port = 1; port <= GEN_HUB(dev)->num_ports; ++port) { + /* ports start at bit1; bit0 is hub status change */ + if (buf[port / 8] & (1 << (port % 8))) { + if (usb_hub_handle_port_change(dev, port) < 0) + return; + } + } + } +} + +static void +usb_hub_destroy(usbdev_t *const dev) +{ + endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev); + dev->controller->destroy_intr_queue(intr_ep, GEN_HUB(dev)->data); + generic_hub_destroy(dev); +} + void usb_hub_init(usbdev_t *const dev) { + endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev); + if (!intr_ep) { + usb_debug("usbhub: ERROR: No interrupt-in endpoint found\n"); + return; + } + + /* Get number of ports from hub decriptor */ int type = dev->speed == SUPER_SPEED ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; /* won't fit the whole thing, we don't care */ if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, @@ -172,5 +252,24 @@ usb_hub_init(usbdev_t *const dev) if (dev->speed == SUPER_SPEED) usb_hub_set_hub_depth(dev); - generic_hub_init(dev, desc.bNbrPorts, &usb_hub_ops); + + /* + * Register interrupt transfer: + * one bit per port + one bit for the hub, + * 20 transfers in the queue, like our HID driver, + * one transfer per 256ms + */ + void *const intrq = dev->controller->create_intr_queue( + intr_ep, (desc.bNbrPorts + 8) / 8, 20, 256); + if (!intrq) + return; + + if (generic_hub_init(dev, desc.bNbrPorts, &usb_hub_ops)) { + dev->controller->destroy_intr_queue(intr_ep, intrq); + return; + } + + GEN_HUB(dev)->data = intrq; + dev->poll = usb_hub_poll; + dev->destroy = usb_hub_destroy; }

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Patch set updated for coreboot: binaryPI platforms: Drop any ACPI S3 support
by Kyösti Mälkki 26 Feb '17

26 Feb '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18501 -gerrit commit 4976a6c5c5270e37a9c64576955e2132ac6d116f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 26 10:18:45 2017 +0200 binaryPI platforms: Drop any ACPI S3 support No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00630F01/model_15_init.c | 4 - src/cpu/amd/pi/00660F01/model_15_init.c | 4 - src/cpu/amd/pi/00670F00/model_15_init.c | 4 - src/cpu/amd/pi/00730F01/model_16_init.c | 4 - src/cpu/amd/pi/Makefile.inc | 17 -- src/cpu/amd/pi/s3_resume.c | 293 -------------------------------- src/cpu/amd/pi/s3_resume.h | 37 ---- src/northbridge/amd/pi/agesawrapper.c | 213 ----------------------- 8 files changed, 576 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index afbade4..925c60c 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -30,7 +30,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> static void model_15_init(device_t dev) { @@ -65,9 +64,6 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index e252c3d..c31dec8 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> #include <amdlib.h> #include <PspBaseLib.h> @@ -80,9 +79,6 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c index dd1c8e3..02e5b79 100644 --- a/src/cpu/amd/pi/00670F00/model_15_init.c +++ b/src/cpu/amd/pi/00670F00/model_15_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> #include <amdlib.h> #include <PspBaseLib.h> @@ -80,9 +79,6 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index a9751a2..294814f 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam16.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> static void model_16_init(device_t dev) { @@ -63,9 +62,6 @@ static void model_16_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 0e31d9f..3dcbbc3 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -18,8 +18,6 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 -romstage-y += s3_resume.c -ramstage-y += s3_resume.c ramstage-$(CONFIG_SPI_FLASH) += spi.c cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc @@ -27,18 +25,3 @@ cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc romstage-y += heapmanager.c ramstage-y += heapmanager.c ramstage-y += amd_late_init.c - -ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) - -$(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp - mv $@.tmp $@ - -cbfs-files-y += s3nv -s3nv-file := $(obj)/coreboot_s3nv.rom -s3nv-position := $(CONFIG_S3_DATA_POS) -s3nv-type := raw - -endif # CONFIG_HAVE_ACPI_RESUME == y diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c deleted file mode 100644 index 338f921..0000000 --- a/src/cpu/amd/pi/s3_resume.c +++ /dev/null @@ -1,293 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <Lib/amdlib.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <cpu/amd/mtrr.h> -#include <cpu/x86/cache.h> -#include <cbmem.h> -#include <device/device.h> -#include <arch/io.h> -#include <arch/acpi.h> -#include <program_loading.h> -#include <string.h> -#include "Porting.h" -#include <northbridge/amd/pi/BiosCallOuts.h> -#include <halt.h> -#include "s3_resume.h" - -/* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_VOLATILE_SIZE 0x6000 -#define S3_DATA_MTRR_SIZE 0x1000 -#define S3_DATA_NONVOLATILE_SIZE 0x1000 - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE -#error "Please increase the value of S3_DATA_SIZE" -#endif - -static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) -{ - /* FIXME: Find file from CBFS. */ - u32 s3_data = CONFIG_S3_DATA_POS; - - switch (S3DataType) { - case S3DataTypeVolatile: - *pos = s3_data; - *len = S3_DATA_VOLATILE_SIZE; - break; - case S3DataTypeMTRR: - *pos = s3_data + S3_DATA_VOLATILE_SIZE; - *len = S3_DATA_MTRR_SIZE; - break; - case S3DataTypeNonVolatile: - *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE; - *len = S3_DATA_NONVOLATILE_SIZE; - break; - default: - *pos = 0; - *len = 0; - break; - } -} - -void restore_mtrr(void) -{ - u32 msr; - volatile UINT32 *msrPtr; - msr_t msr_data; - - printk(BIOS_SPEW, "%s\n", __func__); - - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - msrPtr = (UINT32 *)(pos + sizeof(UINT32)); - - disable_cache(); - - /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Now restore the Fixed MTRRs */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x250, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x258, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x259, msr_data); - - for (msr = 0x268; msr <= 0x26F; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } - - /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Restore the Variable MTRRs */ - for (msr = 0x200; msr <= 0x20F; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } - - /* Restore SYSCFG MTRR */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(SYS_CFG, msr_data); -} - -#ifdef __PRE_RAM__ -static void move_stack_high_mem(void) -{ - uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); - if (!high_stack) - halt(); - - /* TODO: Make the switch with empty stack instead. */ - memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); - -#ifdef __x86_64__ - __asm__ - volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#else - __asm__ - volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#endif -} -#endif - -#ifndef __PRE_RAM__ -/* FIXME: Why store MTRR in SPI, just use CBMEM ? */ -static u8 mtrr_store[S3_DATA_MTRR_SIZE]; - -static void write_mtrr(u8 **p_nvram_pos, unsigned idx) -{ - msr_t msr_data; - msr_data = rdmsr(idx); - - memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data)); - *p_nvram_pos += sizeof(msr_data); -} - -void OemAgesaSaveMtrr(void) -{ - msr_t msr_data; - u32 i; - - u8 *nvram_pos = (u8 *) mtrr_store; - - /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Fixed MTRRs */ - write_mtrr(&nvram_pos, 0x250); - write_mtrr(&nvram_pos, 0x258); - write_mtrr(&nvram_pos, 0x259); - - for (i = 0x268; i < 0x270; i++) - write_mtrr(&nvram_pos, i); - - /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Variable MTRRs */ - for (i = 0x200; i < 0x210; i++) - write_mtrr(&nvram_pos, i); - - /* SYS_CFG */ - write_mtrr(&nvram_pos, 0xC0010010); - /* TOM */ - write_mtrr(&nvram_pos, 0xC001001A); - /* TOM2 */ - write_mtrr(&nvram_pos, 0xC001001D); - -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store); -#endif -} - -u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) -{ -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - spi_SaveS3info(pos, size, Data, DataSize); -#endif - return AGESA_SUCCESS; -} -#endif - -void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) -{ - AMD_CONFIG_PARAMS StdHeader; - - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - - if (S3DataType == S3DataTypeNonVolatile) { - *DataSize = *(UINT32 *) pos; - *Data = (void *) (pos + sizeof(UINT32)); - } else if (S3DataType == S3DataTypeVolatile) { - u32 len = *(UINT32 *) pos; - void *src = (void *) (pos + sizeof(UINT32)); - void *dst = (void *) GetHeapBase(&StdHeader); - memcpy(dst, src, len); - *DataSize = len; - *Data = dst; - } -} - -#ifdef __PRE_RAM__ -static void set_resume_cache(void) -{ - msr_t msr; - - /* disable fixed mtrr for now, it will be enabled by mtrr restore */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); - wrmsr(SYSCFG_MSR, msr); - - /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ - msr.lo = 0 | MTRR_TYPE_WRBACK; - msr.hi = 0; - wrmsr(MTRR_PHYS_BASE(0), msr); - msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; - msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(0), msr); - - /* Set the default memory type and disable fixed and enable variable MTRRs */ - msr.hi = 0; - msr.lo = (1 << 11); - wrmsr(MTRR_DEF_TYPE_MSR, msr); - - enable_cache(); -} - -void prepare_for_resume(void) -{ - if (cbmem_recovery(1)) { - printk(BIOS_EMERG, "Unable to recover CBMEM\n"); - halt(); - } - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - -} -#endif diff --git a/src/cpu/amd/pi/s3_resume.h b/src/cpu/amd/pi/s3_resume.h deleted file mode 100644 index c23c662..0000000 --- a/src/cpu/amd/pi/s3_resume.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef S3_RESUME_H -#define S3_RESUME_H - -typedef enum { - S3DataTypeNonVolatile=0, ///< NonVolatile Data Type - S3DataTypeVolatile, ///< Volatile Data Type - S3DataTypeMTRR ///< MTRR storage -} S3_DATA_TYPE; - -void restore_mtrr(void); -void prepare_for_resume(void); - -u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); -void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); -void OemAgesaSaveMtrr (void); - -void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); - -/* This covers node 0 only. */ -#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) - -#endif diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 0fe8eab..864c8ad 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -15,7 +15,6 @@ #include <AGESA.h> #include <cbfs.h> -#include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> #include <FchPlatform.h> @@ -23,9 +22,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h> -VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); -VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); - void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} #define FILECODE UNASSIGNED_FILE_FILECODE @@ -361,215 +357,6 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( return Status; } -#if CONFIG_HAVE_ACPI_RESUME - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - LibAmdMemFill (&FchParams, - 0, - sizeof(FchParams), - &StdHeader); - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof(AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - - return Status; -} - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - AMD_CONFIG_PARAMS StdHeader; - FCH_DATA_BLOCK FchParams; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - LibAmdMemFill (&FchParams, - 0, - sizeof(FchParams), - &StdHeader); - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ - AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) { AGESA_STATUS Status;

1 0

Patch set updated for coreboot: binaryPI boards: Drop any ACPI S3 support
by Kyösti Mälkki 26 Feb '17

26 Feb '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18500 -gerrit commit 949269853d5e18fc1ae1e0e398224589dbb727d2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 26 10:11:21 2017 +0200 binaryPI boards: Drop any ACPI S3 support None of the boards currently have HAVE_ACPI_RESUME and and ACPI S3 support calls should not appear under board directories anyways. Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/bettong/mainboard.c | 3 --- src/mainboard/amd/bettong/romstage.c | 30 ++++++------------------ src/mainboard/amd/db-ft3b-lc/mainboard.c | 4 ---- src/mainboard/amd/db-ft3b-lc/romstage.c | 34 ++++++++------------------- src/mainboard/amd/gardenia/mainboard.c | 3 --- src/mainboard/amd/gardenia/romstage.c | 30 ++++++------------------ src/mainboard/amd/lamar/mainboard.c | 7 ------ src/mainboard/amd/lamar/romstage.c | 31 +++++++------------------ src/mainboard/amd/olivehillplus/mainboard.c | 4 ---- src/mainboard/amd/olivehillplus/romstage.c | 36 +++++++++-------------------- src/mainboard/bap/ode_e21XX/mainboard.c | 4 ---- src/mainboard/bap/ode_e21XX/romstage.c | 36 +++++++++-------------------- src/mainboard/pcengines/apu2/mainboard.c | 4 ---- src/mainboard/pcengines/apu2/romstage.c | 36 +++++++++-------------------- 14 files changed, 65 insertions(+), 197 deletions(-) diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c index c31f5b7..11d6084 100644 --- a/src/mainboard/amd/bettong/mainboard.c +++ b/src/mainboard/amd/bettong/mainboard.c @@ -84,9 +84,6 @@ static void bettong_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 6b12afc..29cd8a7 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -28,9 +27,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif /* Must come first to enable PCI MMCONF. */ amd_initmmio(); @@ -63,27 +59,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + post_code(0x40); + AGESAWRAPPER(amdinitpost); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); - if (s3resume || acpi_is_wakeup_s4()) { + if (acpi_is_wakeup_s4()) { outb(0xEE, PM_INDEX); outb(0x8, PM_DATA); } diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c index 6f8742c..419a57d 100644 --- a/src/mainboard/amd/db-ft3b-lc/mainboard.c +++ b/src/mainboard/amd/db-ft3b-lc/mainboard.c @@ -17,7 +17,6 @@ #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/pi/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -125,9 +124,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 79cc0f9..0ba1c1d 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -77,28 +75,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 7ebe087..acc9b7c 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -84,9 +84,6 @@ static void gardenia_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index eca9d3b..0136a98 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -28,9 +27,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif amd_initmmio(); hudson_lpc_port80(); @@ -62,27 +58,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + post_code(0x40); + AGESAWRAPPER(amdinitpost); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); - if (s3resume || acpi_is_wakeup_s4()) { + if (acpi_is_wakeup_s4()) { outb(0xEE, PM_INDEX); outb(0x8, PM_DATA); } diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 25e685b..4e010fc 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -147,12 +146,6 @@ static void pirq_setup(void) static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. - */ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index bda8c0f..5530a25 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -32,7 +31,6 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include "cbmem.h" #include "superio/fintek/f81216h/f81216h.h" @@ -88,29 +86,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } - else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); + post_code(0x40); + AGESAWRAPPER(amdinitpost); - post_code(0x61); - prepare_for_resume(); - } + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 1e82768..8693737 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 534a8e5..c98ae25 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -87,29 +85,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c index 1e82768..8693737 100644 --- a/src/mainboard/bap/ode_e21XX/mainboard.c +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 5deeaa8..d8342c9 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> @@ -81,29 +79,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index d2ab638..043bc17 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/pi/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -183,9 +182,6 @@ static void mainboard_enable(device_t dev) // pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14)); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63c..a0d925f 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include <Fch/Fch.h> #include "gpio_ftns.h" @@ -82,29 +80,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7);

1 0

New patch to review for coreboot: binaryPI platforms: Drop any ACPI S3 support
by Kyösti Mälkki 26 Feb '17

26 Feb '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18501 -gerrit commit 57143594009d3d7cdaa43f9edf46e70b7e9b3fd1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 26 10:18:45 2017 +0200 binaryPI platforms: Drop any ACPI S3 support No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00630F01/model_15_init.c | 4 - src/cpu/amd/pi/00660F01/model_15_init.c | 4 - src/cpu/amd/pi/00670F00/model_15_init.c | 4 - src/cpu/amd/pi/00730F01/model_16_init.c | 4 - src/cpu/amd/pi/Makefile.inc | 17 -- src/cpu/amd/pi/s3_resume.c | 293 -------------------------------- src/cpu/amd/pi/s3_resume.h | 37 ---- src/northbridge/amd/pi/agesawrapper.c | 213 ----------------------- 8 files changed, 576 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index afbade4..925c60c 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -30,7 +30,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> static void model_15_init(device_t dev) { @@ -65,9 +64,6 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index e252c3d..c31dec8 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> #include <amdlib.h> #include <PspBaseLib.h> @@ -80,9 +79,6 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c index dd1c8e3..02e5b79 100644 --- a/src/cpu/amd/pi/00670F00/model_15_init.c +++ b/src/cpu/amd/pi/00670F00/model_15_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> #include <amdlib.h> #include <PspBaseLib.h> @@ -80,9 +79,6 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index a9751a2..294814f 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam16.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> static void model_16_init(device_t dev) { @@ -63,9 +62,6 @@ static void model_16_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 0e31d9f..3dcbbc3 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -18,8 +18,6 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 -romstage-y += s3_resume.c -ramstage-y += s3_resume.c ramstage-$(CONFIG_SPI_FLASH) += spi.c cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc @@ -27,18 +25,3 @@ cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc romstage-y += heapmanager.c ramstage-y += heapmanager.c ramstage-y += amd_late_init.c - -ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) - -$(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp - mv $@.tmp $@ - -cbfs-files-y += s3nv -s3nv-file := $(obj)/coreboot_s3nv.rom -s3nv-position := $(CONFIG_S3_DATA_POS) -s3nv-type := raw - -endif # CONFIG_HAVE_ACPI_RESUME == y diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c deleted file mode 100644 index 338f921..0000000 --- a/src/cpu/amd/pi/s3_resume.c +++ /dev/null @@ -1,293 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <Lib/amdlib.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <cpu/amd/mtrr.h> -#include <cpu/x86/cache.h> -#include <cbmem.h> -#include <device/device.h> -#include <arch/io.h> -#include <arch/acpi.h> -#include <program_loading.h> -#include <string.h> -#include "Porting.h" -#include <northbridge/amd/pi/BiosCallOuts.h> -#include <halt.h> -#include "s3_resume.h" - -/* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_VOLATILE_SIZE 0x6000 -#define S3_DATA_MTRR_SIZE 0x1000 -#define S3_DATA_NONVOLATILE_SIZE 0x1000 - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE -#error "Please increase the value of S3_DATA_SIZE" -#endif - -static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) -{ - /* FIXME: Find file from CBFS. */ - u32 s3_data = CONFIG_S3_DATA_POS; - - switch (S3DataType) { - case S3DataTypeVolatile: - *pos = s3_data; - *len = S3_DATA_VOLATILE_SIZE; - break; - case S3DataTypeMTRR: - *pos = s3_data + S3_DATA_VOLATILE_SIZE; - *len = S3_DATA_MTRR_SIZE; - break; - case S3DataTypeNonVolatile: - *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE; - *len = S3_DATA_NONVOLATILE_SIZE; - break; - default: - *pos = 0; - *len = 0; - break; - } -} - -void restore_mtrr(void) -{ - u32 msr; - volatile UINT32 *msrPtr; - msr_t msr_data; - - printk(BIOS_SPEW, "%s\n", __func__); - - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - msrPtr = (UINT32 *)(pos + sizeof(UINT32)); - - disable_cache(); - - /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Now restore the Fixed MTRRs */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x250, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x258, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x259, msr_data); - - for (msr = 0x268; msr <= 0x26F; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } - - /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Restore the Variable MTRRs */ - for (msr = 0x200; msr <= 0x20F; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } - - /* Restore SYSCFG MTRR */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(SYS_CFG, msr_data); -} - -#ifdef __PRE_RAM__ -static void move_stack_high_mem(void) -{ - uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); - if (!high_stack) - halt(); - - /* TODO: Make the switch with empty stack instead. */ - memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); - -#ifdef __x86_64__ - __asm__ - volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#else - __asm__ - volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#endif -} -#endif - -#ifndef __PRE_RAM__ -/* FIXME: Why store MTRR in SPI, just use CBMEM ? */ -static u8 mtrr_store[S3_DATA_MTRR_SIZE]; - -static void write_mtrr(u8 **p_nvram_pos, unsigned idx) -{ - msr_t msr_data; - msr_data = rdmsr(idx); - - memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data)); - *p_nvram_pos += sizeof(msr_data); -} - -void OemAgesaSaveMtrr(void) -{ - msr_t msr_data; - u32 i; - - u8 *nvram_pos = (u8 *) mtrr_store; - - /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Fixed MTRRs */ - write_mtrr(&nvram_pos, 0x250); - write_mtrr(&nvram_pos, 0x258); - write_mtrr(&nvram_pos, 0x259); - - for (i = 0x268; i < 0x270; i++) - write_mtrr(&nvram_pos, i); - - /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Variable MTRRs */ - for (i = 0x200; i < 0x210; i++) - write_mtrr(&nvram_pos, i); - - /* SYS_CFG */ - write_mtrr(&nvram_pos, 0xC0010010); - /* TOM */ - write_mtrr(&nvram_pos, 0xC001001A); - /* TOM2 */ - write_mtrr(&nvram_pos, 0xC001001D); - -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store); -#endif -} - -u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) -{ -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - spi_SaveS3info(pos, size, Data, DataSize); -#endif - return AGESA_SUCCESS; -} -#endif - -void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) -{ - AMD_CONFIG_PARAMS StdHeader; - - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - - if (S3DataType == S3DataTypeNonVolatile) { - *DataSize = *(UINT32 *) pos; - *Data = (void *) (pos + sizeof(UINT32)); - } else if (S3DataType == S3DataTypeVolatile) { - u32 len = *(UINT32 *) pos; - void *src = (void *) (pos + sizeof(UINT32)); - void *dst = (void *) GetHeapBase(&StdHeader); - memcpy(dst, src, len); - *DataSize = len; - *Data = dst; - } -} - -#ifdef __PRE_RAM__ -static void set_resume_cache(void) -{ - msr_t msr; - - /* disable fixed mtrr for now, it will be enabled by mtrr restore */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); - wrmsr(SYSCFG_MSR, msr); - - /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ - msr.lo = 0 | MTRR_TYPE_WRBACK; - msr.hi = 0; - wrmsr(MTRR_PHYS_BASE(0), msr); - msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; - msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(0), msr); - - /* Set the default memory type and disable fixed and enable variable MTRRs */ - msr.hi = 0; - msr.lo = (1 << 11); - wrmsr(MTRR_DEF_TYPE_MSR, msr); - - enable_cache(); -} - -void prepare_for_resume(void) -{ - if (cbmem_recovery(1)) { - printk(BIOS_EMERG, "Unable to recover CBMEM\n"); - halt(); - } - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - -} -#endif diff --git a/src/cpu/amd/pi/s3_resume.h b/src/cpu/amd/pi/s3_resume.h deleted file mode 100644 index c23c662..0000000 --- a/src/cpu/amd/pi/s3_resume.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef S3_RESUME_H -#define S3_RESUME_H - -typedef enum { - S3DataTypeNonVolatile=0, ///< NonVolatile Data Type - S3DataTypeVolatile, ///< Volatile Data Type - S3DataTypeMTRR ///< MTRR storage -} S3_DATA_TYPE; - -void restore_mtrr(void); -void prepare_for_resume(void); - -u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); -void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); -void OemAgesaSaveMtrr (void); - -void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); - -/* This covers node 0 only. */ -#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) - -#endif diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 0fe8eab..864c8ad 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -15,7 +15,6 @@ #include <AGESA.h> #include <cbfs.h> -#include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> #include <FchPlatform.h> @@ -23,9 +22,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h> -VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); -VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); - void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} #define FILECODE UNASSIGNED_FILE_FILECODE @@ -361,215 +357,6 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( return Status; } -#if CONFIG_HAVE_ACPI_RESUME - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - LibAmdMemFill (&FchParams, - 0, - sizeof(FchParams), - &StdHeader); - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof(AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - - return Status; -} - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - AMD_CONFIG_PARAMS StdHeader; - FCH_DATA_BLOCK FchParams; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - LibAmdMemFill (&FchParams, - 0, - sizeof(FchParams), - &StdHeader); - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ - AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) { AGESA_STATUS Status;

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New patch to review for coreboot: binaryPI boards: Drop any ACPI S3 support
by Kyösti Mälkki 26 Feb '17

26 Feb '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18500 -gerrit commit 0be66b7277a33e0f80aabf4a9fa043b33f0238f2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 26 10:11:21 2017 +0200 binaryPI boards: Drop any ACPI S3 support None of the boards currently have HAVE_ACPI_RESUME and and ACPI S3 support calls should not appear under board directories anyways. Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/bettong/mainboard.c | 3 --- src/mainboard/amd/bettong/romstage.c | 32 +++++++------------------ src/mainboard/amd/db-ft3b-lc/mainboard.c | 4 ---- src/mainboard/amd/db-ft3b-lc/romstage.c | 34 ++++++++------------------- src/mainboard/amd/gardenia/mainboard.c | 3 --- src/mainboard/amd/gardenia/romstage.c | 32 +++++++------------------ src/mainboard/amd/lamar/mainboard.c | 7 ------ src/mainboard/amd/lamar/romstage.c | 31 +++++++------------------ src/mainboard/amd/olivehillplus/mainboard.c | 4 ---- src/mainboard/amd/olivehillplus/romstage.c | 36 +++++++++-------------------- src/mainboard/bap/ode_e21XX/mainboard.c | 4 ---- src/mainboard/bap/ode_e21XX/romstage.c | 36 +++++++++-------------------- src/mainboard/pcengines/apu2/mainboard.c | 4 ---- src/mainboard/pcengines/apu2/romstage.c | 36 +++++++++-------------------- 14 files changed, 67 insertions(+), 199 deletions(-) diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c index c31f5b7..11d6084 100644 --- a/src/mainboard/amd/bettong/mainboard.c +++ b/src/mainboard/amd/bettong/mainboard.c @@ -84,9 +84,6 @@ static void bettong_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 6b12afc..7930c89 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -28,9 +27,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif /* Must come first to enable PCI MMCONF. */ amd_initmmio(); @@ -63,31 +59,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - post_code(0x61); - prepare_for_resume(); - } - - if (s3resume || acpi_is_wakeup_s4()) { + if (acpi_is_wakeup_s4()) { outb(0xEE, PM_INDEX); outb(0x8, PM_DATA); } + post_code(0x40); + AGESAWRAPPER(amdinitpost); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); + post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c index 6f8742c..419a57d 100644 --- a/src/mainboard/amd/db-ft3b-lc/mainboard.c +++ b/src/mainboard/amd/db-ft3b-lc/mainboard.c @@ -17,7 +17,6 @@ #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/pi/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -125,9 +124,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 79cc0f9..0ba1c1d 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -77,28 +75,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 7ebe087..acc9b7c 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -84,9 +84,6 @@ static void gardenia_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index eca9d3b..3d65cc2 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -28,9 +27,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif amd_initmmio(); hudson_lpc_port80(); @@ -62,31 +58,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - post_code(0x61); - prepare_for_resume(); - } - - if (s3resume || acpi_is_wakeup_s4()) { + if (acpi_is_wakeup_s4()) { outb(0xEE, PM_INDEX); outb(0x8, PM_DATA); } + post_code(0x40); + AGESAWRAPPER(amdinitpost); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); + post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 25e685b..4e010fc 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -147,12 +146,6 @@ static void pirq_setup(void) static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. - */ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index bda8c0f..5530a25 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -32,7 +31,6 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include "cbmem.h" #include "superio/fintek/f81216h/f81216h.h" @@ -88,29 +86,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } - else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); + post_code(0x40); + AGESAWRAPPER(amdinitpost); - post_code(0x61); - prepare_for_resume(); - } + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 1e82768..8693737 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 534a8e5..c98ae25 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -87,29 +85,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c index 1e82768..8693737 100644 --- a/src/mainboard/bap/ode_e21XX/mainboard.c +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 5deeaa8..d8342c9 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> @@ -81,29 +79,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index d2ab638..043bc17 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/pi/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -183,9 +182,6 @@ static void mainboard_enable(device_t dev) // pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14)); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63c..a0d925f 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include <Fch/Fch.h> #include "gpio_ftns.h" @@ -82,29 +80,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7);

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Patch set updated for coreboot: superiotool: add SMSC KBC1126
by Iru Cai 26 Feb '17

26 Feb '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18480 -gerrit commit ecbad3ee274e81893a0687be8854489a60f9b7aa Author: Iru Cai <mytbk920423(a)gmail.com> Date: Fri Feb 24 15:35:55 2017 +0800 superiotool: add SMSC KBC1126 Device ID is read from HP Elitebook 2760p. LDNs are from superio/smsc/kbc1100/kbc1100.h, and the register indices come from the existing code in smsc.c. Keyboard and EC registers can be seen from superio/sms/kbc1100/early_init.c. COM1 registers can be seen from the DSDT dump of HP Elitebook 2760p running OEM firmware. Change-Id: Id172ae42411a6d42a4ae7c7f30f96aeda3e6c384 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- util/superiotool/smsc.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index 15ba131..4a06ede 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -68,6 +68,33 @@ static const struct superio_registers reg_table[] = { {0x03, "FDC37C93xFR", { /* FIXME: There's another 0x03 but found on port 0x0d/0x0e! */ {EOT}}}, + {0x07, "KBC1126", { + {NOLDN, NULL, + {0x02,0x03,0x07,0x17,0x20,0x21,0x22,0x23,0x24,0x25, + 0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f, + EOT}, + {0x00,RSVD,0x00,RSVD,0x07,0x00,0x00,0x00,0x04,0x04, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + EOT}}, + {0x1, "Power management (PM1)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x4, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x7, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x8, "Embedded controller (EC)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x62,EOT}}, + {0x9, "Mailbox", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0xa, "LPC/8051 addressable GPIO (LGPIO)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {EOT}}}, {0x0a, "FDC37N971", { {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,

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Patch set updated for coreboot: .gitignore: ignore *.swo and option *.roms
by Alexander Couzens 25 Feb '17

25 Feb '17

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15220 -gerrit commit 22857db8a60c5cf1df6d251134e691d83ecef844 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Jun 16 19:53:39 2016 -0700 .gitignore: ignore *.swo and option *.roms Change-Id: I7403f548bae918ca813a9295bfb095a7c4c51e21 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 2061f00..f5fb152 100644 --- a/.gitignore +++ b/.gitignore @@ -53,7 +53,8 @@ site-local *.elf *.o *.out -*.swp +*.sw[po] +/*.rom # Development friendly files tags

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Patch merged into coreboot/master: mainboard/google/reef: keep LPSS_UART2_TXD high in suspend state
by gerrit＠coreboot.org 25 Feb '17

25 Feb '17

the following patch was just integrated into master: commit 6295b8a57aec05add2ab4c4d9af53bf8e707b882 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 24 15:56:27 2017 -0600 mainboard/google/reef: keep LPSS_UART2_TXD high in suspend state The cr50 part on reef is connected to the SoC's UART lines. However, when the tx signal is low it causes an interrupt to fire on cr50. Therefore, keep the tx signal high in suspend state so that it doesn't cause an interrupt storm on cr50 which prevents cr50 from sleeping. BUG=chrome-os-partner:63283 BRANCH=reef TEST=s0ix no longer causes interrupt storm on cr50. Power consumption normal. Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/18491 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/18491 for details. -gerrit

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Patch merged into coreboot/master: google/eve: Add rise/fall times for I2C buses
by gerrit＠coreboot.org 25 Feb '17

25 Feb '17

the following patch was just integrated into master: commit d4d6ba180d718b073379000b480dc3f468581955 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Feb 24 12:28:12 2017 -0800 google/eve: Add rise/fall times for I2C buses Apply tuning for the PCH I2C buses on Eve based on rise/fall time measurements that were done with a scope. BUG=chrome-os-partner:59686 BRANCH=none TEST=Manual testing on Eve P1 to verify that all devices on I2C buses are still functional. Post-tuning measurement will be done once a new firmware is released. Change-Id: I3d70ff455a20ecda374d7e7fa6cd3ab15e7f2621 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/18487 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/18487 for details. -gerrit

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coreboot-gerrit February 2017