coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/x4x/gma.c: Add disable function
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18504 -gerrit commit 41e826c84599de93e64ff3045883240b7646f57d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 26 23:04:51 2017 +0100 nb/x4x/gma.c: Add disable function This should allow set_vga_bridge_bits() in device.c to disable the integrated GPU when an external GPU is detected. UNTESTED Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 74250fe..a55eee4 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -376,6 +376,23 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); } +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + u16 ggc; + + ggc = pci_read_config16(dev_host, D0F0_GGC); + ggc &= 0xff0f; + ggc |= (1 << 1); + pci_write_config16(dev_host, D0F0_GGC, ggc); + + unsigned int reg32 = pci_read_config32(dev_host, D0F0_DEVEN); + reg32 &= ~(IGD0EN | IGD1EN); + pci_write_config32(dev_host, D0F0_DEVEN, reg32); + + dev->enabled = 0; +} + static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -420,6 +437,7 @@ static struct device_operations gma_func0_ops = { .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, + .disable = gma_func0_disable, }; static const unsigned short pci_device_ids[] =

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Patch set updated for coreboot: nb/x4x/gma.c: Add disable function
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18504 -gerrit commit f59f0195255745bb9cb27f746321e794bd68d6a3 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 26 23:04:51 2017 +0100 nb/x4x/gma.c: Add disable function This should allow set_vga_bridge_bits() in device.c to disable the integrated GPU when an external GPU is detected. UNTESTED Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 74250fe..81b681a 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -376,6 +376,23 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); } +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + u16 ggc; + + ggc = pci_read_config(dev_host, D0F0_GGC); + ggc &= 0xff0f; + ggc |= (1 << 1); + pci_write_config16(dev_host, D0F0_GGC, ggc); + + unsigned int reg32 = pci_read_config32(dev_host, D0F0_DEVEN); + reg32 &= ~(IGD0EN | IGD1EN); + pci_write_config32(dev_host, D0F0_DEVEN, reg32); + + dev->enabled = 0; +} + static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -420,6 +437,7 @@ static struct device_operations gma_func0_ops = { .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, + .disable = gma_func0_disable, }; static const unsigned short pci_device_ids[] =

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New patch to review for coreboot: nb/x4x/nortbridge.c: Fix resource allocation when IGD is disabled
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18511 -gerrit commit 372084bfb48d9354edbe8e1b358d05fb349f18d4 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 13:46:11 2017 +0100 nb/x4x/nortbridge.c: Fix resource allocation when IGD is disabled Shamelessly copied from gm45 Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 1c220b2..760e875 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -64,18 +64,25 @@ static void mch_domain_read_resources(device_t dev) /* Graphics memory comes next */ const u16 ggc = pci_read_config16(dev, D0F0_GGC); - printk(BIOS_DEBUG, "IGD decoded, subtracting "); + if (!(ggc & 2)) { + printk(BIOS_DEBUG, "IGD decoded, subtracting "); - /* Graphics memory */ - const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); - printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + /* Graphics memory */ + const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); + printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + tomk -= gms_sizek; - /* GTT Graphics Stolen Memory Size (GGMS) */ - const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); - printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + /* GTT Graphics Stolen Memory Size (GGMS) */ + const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); + printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + tomk -= gms_sizek; - uma_sizek = gms_sizek + gsm_sizek + tseg_sizek; - usable_tomk = tomk - uma_sizek; + uma_sizek = gms_sizek + gsm_sizek + tseg_sizek; + } + + usable_tomk = ALIGN_DOWN(tomk, 64 << 10); + if (tomk - usable_tomk > (16 << 10)) + usable_tomk = tomk; printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);

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Patch set updated for coreboot: nb/x4x/gma.c: Add disable function
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18504 -gerrit commit 29c538b2f7d29c55dc8187320f3b3c1023b3e314 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 26 23:04:51 2017 +0100 nb/x4x/gma.c: Add disable function This should allow set_vga_bridge_bits() in device.c to disable the integrated GPU when an external GPU is detected. UNTESTED Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 74250fe..fb49af5 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -376,6 +376,23 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); } +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + u16 gcc; + + gcc = pci_read_config(dev_host, D0F0_GGC); + gcc &= 0xff0f; + ggc |= (1 << 1); + pci_write_config16(dev_host, D0F0_GGC, gcc); + + unsigned int reg32 = pci_read_config32(dev_host, D0F0_DEVEN); + reg32 &= ~(IGD0EN | IGD1EN); + pci_write_config32(dev_host, D0F0_DEVEN, reg32); + + dev->enabled = 0; +} + static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -420,6 +437,7 @@ static struct device_operations gma_func0_ops = { .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, + .disable = gma_func0_disable, }; static const unsigned short pci_device_ids[] =

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Patch set updated for coreboot: soc/intel/skylake: Clean up CPU code
by Subrata Banik 27 Feb '17

27 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18510 -gerrit commit 1f9e67c8d661248c2e1422cf7c9c9124813c49fc Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 15:47:27 2017 +0530 soc/intel/skylake: Clean up CPU code Refer all MSRs from common x86/msr.h location. Change-Id: Ifb73c42fa3f1b0a5bcf076ff768cd7f8d1524b07 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/bootblock/cache_as_ram.S | 19 +++------ src/soc/intel/skylake/bootblock/cpu.c | 2 +- src/soc/intel/skylake/cpu.c | 2 +- src/soc/intel/skylake/include/soc/msr.h | 59 -------------------------- 4 files changed, 9 insertions(+), 73 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S index 3f8f0f0..17efdd0 100644 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S @@ -16,16 +16,11 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <rules.h> -#define IA32_PQR_ASSOC 0x0c8f -#define IA32_L3_MASK_1 0x0c91 -#define IA32_L3_MASK_2 0x0c92 -#define CACHE_INIT_VALUE 0 -#define MSR_EVICT_CTL 0x2e0 - .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -188,7 +183,7 @@ find_llc_subleaf: */ shl %cl, %eax subl $0x02, %eax - movl $IA32_L3_MASK_1, %ecx + movl $MSR_IA32_L3_MASK_1, %ecx xorl %edx, %edx wrmsr /* @@ -197,12 +192,12 @@ find_llc_subleaf: * For SKL SOC, data size remains 256K consistently. * Hence, creating 1-way associative cache for Data */ - mov $IA32_L3_MASK_2, %ecx + mov $MSR_IA32_L3_MASK_2, %ecx mov $0x01, %eax xorl %edx, %edx wrmsr /* - * Set IA32_PQR_ASSOC = 0x02 + * Set MSR_IA32_PQR_ASSOC = 0x02 * * Possible values: * 0: Default value, no way mask should be applied @@ -210,7 +205,7 @@ find_llc_subleaf: * 2: Apply way mask 2 to LLC * 3: Shouldn't be use in NEM Mode */ - movl $IA32_PQR_ASSOC, %ecx + movl $MSR_IA32_PQR_ASSOC, %ecx movl $0x02, %eax xorl %edx, %edx wrmsr @@ -218,7 +213,7 @@ find_llc_subleaf: movl $CONFIG_DCACHE_RAM_BASE, %edi movl $CONFIG_DCACHE_RAM_SIZE, %ecx shr $0x02, %ecx - movl $CACHE_INIT_VALUE, %eax + xor %eax, %eax cld rep stosl /* @@ -226,7 +221,7 @@ find_llc_subleaf: * At this stage we apply LLC_WAY_MASK_1 to the cache. * i.e. way 0 is protected from eviction. */ - movl $IA32_PQR_ASSOC, %ecx + movl $MSR_IA32_PQR_ASSOC, %ecx movl $0x01, %eax xorl %edx, %edx wrmsr diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 3cea8bd..c6ede53 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -126,7 +126,7 @@ void set_max_freq(void) } perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); + wrmsr(MSR_IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index d1a684c..6a8f48f 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -409,7 +409,7 @@ static int get_cpu_count(void) int num_threads; int num_cores; - msr = rdmsr(CORE_THREAD_COUNT_MSR); + msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 4d295e1..89ceaeb 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -18,30 +18,9 @@ #define _SOC_MSR_H_ #define MSR_PIC_MSG_CONTROL 0x2e -#define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_FEATURE_CONFIG 0x13c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MISC_PWR_MGMT_ISST_EN (1 << 6) -#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) -#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 @@ -51,53 +30,15 @@ #define EMRR_PHYS_BASE_MSR 0x1f4 #define EMRR_PHYS_MASK_MSR 0x1f5 #define IA32_PLATFORM_DCA_CAP 0x1f8 -#define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - -#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a -#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b -#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c -#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 -#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 -#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) -#define MSR_COUNTER_24_MHZ 0x637 - -/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_DDR_RAPL_LIMIT 0x618 #define MSR_VR_MISC_CONFIG2 0x636 #define MSR_PP0_POWER_LIMIT 0x638 #define MSR_PP1_POWER_LIMIT 0x640 -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c - /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22

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Patch set updated for coreboot: cpu/x86: Move x86 MSR definition into common location
by Subrata Banik 27 Feb '17

27 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18509 -gerrit commit 5d4c2031fb32a0ddec866c3979f919181c350052 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 15:42:09 2017 +0530 cpu/x86: Move x86 MSR definition into common location Move all common MSRs as per IA SDM into a common location to avoid duplication. Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/include/cpu/x86/msr.h | 85 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index f830f3b..0f5004f 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -1,6 +1,88 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H +#define MSR_CORE_THREAD_COUNT 0x35 +#define IA32_FEATURE_CONTROL 0x3a +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define MSR_PLATFORM_INFO 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define PKG_C_STATE_LIMIT_C2_MASK 0x2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +#define IO_MWAIT_REDIRECT_MASK 0x400 +/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +#define CST_CFG_LOCK_MASK 0x8000 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_IA32_PERF_CTL 0x199 +#define IA32_MISC_ENABLE 0x1a0 +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PREFETCH_CTL 0x1a4 +#define PREFETCH_L1_DISABLE (1 << 0) +#define PREFETCH_L2_DISABLE (1 << 2) +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MISC_PWR_MGMT_ISST_EN (1 << 6) +#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) +#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_POWER_CTL 0x1fc +#define MSR_EVICT_CTL 0x2e0 +#define IA32_MC0_STATUS 0x401 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a +#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b +#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c +#define MSR_PKG_POWER_LIMIT 0x610 +/* + * For Mobile, RAPL default PL1 time window value set to 28 seconds. + * RAPL time window calculation defined as follows: + * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22], + * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. + */ +#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_DDR_RAPL_LIMIT 0x618 +#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 +#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 +#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff) +#define MSR_COUNTER_24_MHZ 0x637 +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define PKG_POWER_LIMIT_MASK (0x7fff) +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK (0x7f) +#define MSR_IA32_PQR_ASSOC 0x0c8f +/* MSR bits 33:32 encode slot number 0-3 */ +#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) +#define MSR_IA32_L3_MASK_1 0x0c91 +#define MSR_IA32_L3_MASK_2 0x0c92 +#define MSR_L2_QOS_MASK(reg) (0xd10 + reg) + #if defined(__ROMCC__) typedef __builtin_msr_t msr_t; @@ -16,7 +98,7 @@ static void wrmsr(unsigned long index, msr_t msr) } #else - +#if !defined(__ASSEMBLER__) typedef struct msr_struct { unsigned lo; @@ -76,6 +158,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms } #endif /* CONFIG_SOC_SETS_MSRS */ +#endif #endif /* __ROMCC__ */ #endif /* CPU_X86_MSR_H */

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Patch set updated for coreboot: soc/intel/skylake: Clean up CPU code
by Subrata Banik 27 Feb '17

27 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18510 -gerrit commit 2d04e2f9ff28d9d77e84e76f4c4fd2043b0baa88 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 15:47:27 2017 +0530 soc/intel/skylake: Clean up CPU code Refer all MSRs from common x86/msr.h location. Change-Id: Ifb73c42fa3f1b0a5bcf076ff768cd7f8d1524b07 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/bootblock/cache_as_ram.S | 19 +++----- src/soc/intel/skylake/bootblock/cpu.c | 2 +- src/soc/intel/skylake/cpu.c | 2 +- src/soc/intel/skylake/include/soc/msr.h | 61 -------------------------- 4 files changed, 9 insertions(+), 75 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S index 3f8f0f0..17efdd0 100644 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S @@ -16,16 +16,11 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <rules.h> -#define IA32_PQR_ASSOC 0x0c8f -#define IA32_L3_MASK_1 0x0c91 -#define IA32_L3_MASK_2 0x0c92 -#define CACHE_INIT_VALUE 0 -#define MSR_EVICT_CTL 0x2e0 - .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -188,7 +183,7 @@ find_llc_subleaf: */ shl %cl, %eax subl $0x02, %eax - movl $IA32_L3_MASK_1, %ecx + movl $MSR_IA32_L3_MASK_1, %ecx xorl %edx, %edx wrmsr /* @@ -197,12 +192,12 @@ find_llc_subleaf: * For SKL SOC, data size remains 256K consistently. * Hence, creating 1-way associative cache for Data */ - mov $IA32_L3_MASK_2, %ecx + mov $MSR_IA32_L3_MASK_2, %ecx mov $0x01, %eax xorl %edx, %edx wrmsr /* - * Set IA32_PQR_ASSOC = 0x02 + * Set MSR_IA32_PQR_ASSOC = 0x02 * * Possible values: * 0: Default value, no way mask should be applied @@ -210,7 +205,7 @@ find_llc_subleaf: * 2: Apply way mask 2 to LLC * 3: Shouldn't be use in NEM Mode */ - movl $IA32_PQR_ASSOC, %ecx + movl $MSR_IA32_PQR_ASSOC, %ecx movl $0x02, %eax xorl %edx, %edx wrmsr @@ -218,7 +213,7 @@ find_llc_subleaf: movl $CONFIG_DCACHE_RAM_BASE, %edi movl $CONFIG_DCACHE_RAM_SIZE, %ecx shr $0x02, %ecx - movl $CACHE_INIT_VALUE, %eax + xor %eax, %eax cld rep stosl /* @@ -226,7 +221,7 @@ find_llc_subleaf: * At this stage we apply LLC_WAY_MASK_1 to the cache. * i.e. way 0 is protected from eviction. */ - movl $IA32_PQR_ASSOC, %ecx + movl $MSR_IA32_PQR_ASSOC, %ecx movl $0x01, %eax xorl %edx, %edx wrmsr diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 3cea8bd..c6ede53 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -126,7 +126,7 @@ void set_max_freq(void) } perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); + wrmsr(MSR_IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index d1a684c..6a8f48f 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -409,7 +409,7 @@ static int get_cpu_count(void) int num_threads; int num_cores; - msr = rdmsr(CORE_THREAD_COUNT_MSR); + msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 4d295e1..62c8cf0 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -18,30 +18,9 @@ #define _SOC_MSR_H_ #define MSR_PIC_MSG_CONTROL 0x2e -#define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_FEATURE_CONFIG 0x13c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MISC_PWR_MGMT_ISST_EN (1 << 6) -#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) -#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 @@ -51,52 +30,12 @@ #define EMRR_PHYS_BASE_MSR 0x1f4 #define EMRR_PHYS_MASK_MSR 0x1f5 #define IA32_PLATFORM_DCA_CAP 0x1f8 -#define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - -#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a -#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b -#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c -#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 -#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 -#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) -#define MSR_COUNTER_24_MHZ 0x637 - -/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_DDR_RAPL_LIMIT 0x618 #define MSR_VR_MISC_CONFIG2 0x636 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c /* SMM save state MSRs */ #define SMBASE_MSR 0xc20

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New patch to review for coreboot: soc/intel/skylake: Clean up CPU code
by Subrata Banik 27 Feb '17

27 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18510 -gerrit commit d3eb954621a79a1728da67587c133e6e1821efc7 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 15:47:27 2017 +0530 soc/intel/skylake: Clean up CPU code Refer all MSRs from common x86/msr.h location. Change-Id: Ifb73c42fa3f1b0a5bcf076ff768cd7f8d1524b07 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/bootblock/cache_as_ram.S | 19 +++----- src/soc/intel/skylake/bootblock/cpu.c | 2 +- src/soc/intel/skylake/cpu.c | 2 +- src/soc/intel/skylake/include/soc/msr.h | 61 -------------------------- 4 files changed, 9 insertions(+), 75 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S index 3f8f0f0..0876afe 100644 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S @@ -16,16 +16,11 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <rules.h> -#define IA32_PQR_ASSOC 0x0c8f -#define IA32_L3_MASK_1 0x0c91 -#define IA32_L3_MASK_2 0x0c92 -#define CACHE_INIT_VALUE 0 -#define MSR_EVICT_CTL 0x2e0 - .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -188,7 +183,7 @@ find_llc_subleaf: */ shl %cl, %eax subl $0x02, %eax - movl $IA32_L3_MASK_1, %ecx + movl $MSR_IA32_L3_MASK_1, %ecx xorl %edx, %edx wrmsr /* @@ -197,12 +192,12 @@ find_llc_subleaf: * For SKL SOC, data size remains 256K consistently. * Hence, creating 1-way associative cache for Data */ - mov $IA32_L3_MASK_2, %ecx + mov $MSR_IA32_L3_MASK_2, %ecx mov $0x01, %eax xorl %edx, %edx wrmsr /* - * Set IA32_PQR_ASSOC = 0x02 + * Set MSR_IA32_PQR_ASSOC = 0x02 * * Possible values: * 0: Default value, no way mask should be applied @@ -210,7 +205,7 @@ find_llc_subleaf: * 2: Apply way mask 2 to LLC * 3: Shouldn't be use in NEM Mode */ - movl $IA32_PQR_ASSOC, %ecx + movl $MSR_IA32_PQR_ASSOC, %ecx movl $0x02, %eax xorl %edx, %edx wrmsr @@ -218,15 +213,15 @@ find_llc_subleaf: movl $CONFIG_DCACHE_RAM_BASE, %edi movl $CONFIG_DCACHE_RAM_SIZE, %ecx shr $0x02, %ecx - movl $CACHE_INIT_VALUE, %eax cld + xor %eax, %eax rep stosl /* * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. * i.e. way 0 is protected from eviction. */ - movl $IA32_PQR_ASSOC, %ecx + movl $MSR_IA32_PQR_ASSOC, %ecx movl $0x01, %eax xorl %edx, %edx wrmsr diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 3cea8bd..c6ede53 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -126,7 +126,7 @@ void set_max_freq(void) } perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); + wrmsr(MSR_IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index d1a684c..6a8f48f 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -409,7 +409,7 @@ static int get_cpu_count(void) int num_threads; int num_cores; - msr = rdmsr(CORE_THREAD_COUNT_MSR); + msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 4d295e1..62c8cf0 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -18,30 +18,9 @@ #define _SOC_MSR_H_ #define MSR_PIC_MSG_CONTROL 0x2e -#define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_FEATURE_CONFIG 0x13c -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 -#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MISC_PWR_MGMT_ISST_EN (1 << 6) -#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) -#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 @@ -51,52 +30,12 @@ #define EMRR_PHYS_BASE_MSR 0x1f4 #define EMRR_PHYS_MASK_MSR 0x1f5 #define IA32_PLATFORM_DCA_CAP 0x1f8 -#define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) - -#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a -#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b -#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c -#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 -#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 -#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) -#define MSR_COUNTER_24_MHZ 0x637 - -/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f - #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_DDR_RAPL_LIMIT 0x618 #define MSR_VR_MISC_CONFIG2 0x636 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 - -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c /* SMM save state MSRs */ #define SMBASE_MSR 0xc20

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New patch to review for coreboot: cpu/x86: Move x86 MSR definition into common location
by Subrata Banik 27 Feb '17

27 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18509 -gerrit commit 68897a1ba1e330bf27d71cd2b8d123974af57a49 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 15:42:09 2017 +0530 cpu/x86: Move x86 MSR definition into common location Move all common MSRs as per IA SDM into a common location to avoid duplication. Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/include/cpu/x86/msr.h | 87 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 1 deletion(-) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index f830f3b..019c678 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -1,6 +1,90 @@ #ifndef CPU_X86_MSR_H #define CPU_X86_MSR_H +#define MSR_CORE_THREAD_COUNT 0x35 +#define IA32_FEATURE_CONTROL 0x3a +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define MSR_PLATFORM_INFO 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define PKG_C_STATE_LIMIT_C2_MASK 0x2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +#define IO_MWAIT_REDIRECT_MASK 0x400 +/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +#define CST_CFG_LOCK_MASK 0x8000 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_IA32_PERF_CTL 0x199 +#define IA32_MISC_ENABLE 0x1a0 +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PREFETCH_CTL 0x1a4 +#define PREFETCH_L1_DISABLE (1 << 0) +#define PREFETCH_L2_DISABLE (1 << 2) +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MISC_PWR_MGMT_ISST_EN (1 << 6) +#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) +#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_POWER_CTL 0x1fc +#define MSR_EVICT_CTL 0x2e0 +#define IA32_MC0_STATUS 0x401 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a +#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b +#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c +#define MSR_PKG_POWER_LIMIT 0x610 +/* + * For Mobile, RAPL default PL1 time window value set to 28 seconds. + * RAPL time window calculation defined as follows: + * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22], + * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. + */ +#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_DDR_RAPL_LIMIT 0x618 +#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 +#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 +#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff) +#define MSR_COUNTER_24_MHZ 0x637 +#define MSR_PP0_POWER_LIMIT 0x638 +#define MSR_PP1_POWER_LIMIT 0x640 +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define PKG_POWER_LIMIT_MASK (0x7fff) +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK (0x7f) +#define MSR_IA32_PQR_ASSOC 0x0c8f +/* MSR bits 33:32 encode slot number 0-3 */ +#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) +#define MSR_IA32_L3_MASK_1 0x0c91 +#define MSR_IA32_L3_MASK_2 0x0c92 +#define MSR_L2_QOS_MASK(reg) (0xd10 + reg) + #if defined(__ROMCC__) typedef __builtin_msr_t msr_t; @@ -16,7 +100,7 @@ static void wrmsr(unsigned long index, msr_t msr) } #else - +#if !defined(__ASSEMBLER__) typedef struct msr_struct { unsigned lo; @@ -76,6 +160,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms } #endif /* CONFIG_SOC_SETS_MSRS */ +#endif #endif /* __ROMCC__ */ #endif /* CPU_X86_MSR_H */

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Patch set updated for coreboot: soc/intel/glk: Include cache_as_ram_fsp.S inside glk/bootblock
by Subrata Banik 27 Feb '17

27 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18453 -gerrit commit d454c1ae1050fccd0c05947350b83b663e828397 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 16:22:58 2017 +0530 soc/intel/glk: Include cache_as_ram_fsp.S inside glk/bootblock Add option to use FSP APIs to initialize & Tear Down the Cache-As-Ram. Change-Id: I4964fa27967323062c6243e023d2caa82b7f0440 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Makefile.inc | 2 + src/soc/intel/glk/bootblock/cache_as_ram_fsp.S | 111 +++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc index b2a430a..8ca6162 100644 --- a/src/soc/intel/glk/Makefile.inc +++ b/src/soc/intel/glk/Makefile.inc @@ -10,6 +10,8 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../common/basecode subdirs-y += ../common/block/* +bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S + CPPFLAGS_common += -I$(src)/soc/intel/glk/include CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk diff --git a/src/soc/intel/glk/bootblock/cache_as_ram_fsp.S b/src/soc/intel/glk/bootblock/cache_as_ram_fsp.S new file mode 100644 index 0000000..f55582a --- /dev/null +++ b/src/soc/intel/glk/bootblock/cache_as_ram_fsp.S @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/cpu.h> + +#include <../../../arch/x86/walkcbfs.S> + +#define FSP_HDR_OFFSET 0x94 + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add FSP_HDR_OFFSET, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */ + add 0x1c(%ebx), %eax /* add the FSP ImageBase */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +/* + * If the TempRamInit API is successful, then when returning, the ECX and + * EDX registers will point to the temporary but writeable memory range + * available to the bootloader where ECX is the start and EDX is the end of + * the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more + * information. + * + * Return Values: + * EAX | Return Status + * ECX | Temporary Memory Start + * EDX | Temporary Memory End + * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call + */ + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0 /* Microcode Location */ + .long 0 /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "blobs/fspt.bin\x00"

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coreboot-gerrit February 2017