coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/x4x: Do not enable IGD when not supported
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18515 -gerrit commit 20764cb9edc8fd3ac79a20f9766e8863a15411c2 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 20:14:21 2017 +0100 nb/x4x: Do not enable IGD when not supported According to "Intel ® 4 Series Chipset Family datasheet" in the description about GGC and DEVEN, CAPID0 bit48 is said to reflect the presence of an internal graphic device. This would allow the P43 and P45 chipset variants to work. Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/early_init.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 7d6afc9..2a6e233 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -54,16 +54,19 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - /* Enable internal GFX */ - pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - /* Set preallocated IGD size from cmos */ - u8 gfxsize; - - if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 6 for 64MB, default if not set in cmos */ - gfxsize = 6; + if (pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32))) { + /* Enable internal GFX */ + pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); + /* Set preallocated IGD size from cmos */ + u8 gfxsize; + + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 6 for 64MB, default if not set in cmos */ + gfxsize = 6; + } + pci_write_config16(d0f0, D0F0_GGC, + 0x0100 | ((gfxsize + 1) << 4)); } - pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); } static void init_egress(void)

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New patch to review for coreboot: nb/x4x: Do not enable IGD when not supported
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18515 -gerrit commit 0176e1b98aabb8900097e212648f206ec5a9862a Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 20:14:21 2017 +0100 nb/x4x: Do not enable IGD when not supported According to "Intel ® 4 Series Chipset Family datasheet" in the description about GGC and DEVEN, CAPID0 bit48 is said to reflect the presence of an internal graphic device. This would allow the P43 and P45 chipset variants to work. UNTESTED Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/early_init.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 7d6afc9..af46b5b 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -54,16 +54,19 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - /* Enable internal GFX */ - pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - /* Set preallocated IGD size from cmos */ - u8 gfxsize; - - if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 6 for 64MB, default if not set in cmos */ - gfxsize = 6; + if (pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (48 - 32))) { + /* Enable internal GFX */ + pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); + /* Set preallocated IGD size from cmos */ + u8 gfxsize; + + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 6 for 64MB, default if not set in cmos */ + gfxsize = 6; + } + pci_write_config16(d0f0, D0F0_GGC, + 0x0100 | ((gfxsize + 1) << 4)); } - pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); } static void init_egress(void)

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New patch to review for coreboot: Broadwell/sata: Fix a typo in the IOBP setting.
by Youness Alaoui 27 Feb '17

27 Feb '17

Youness Alaoui (snifikino(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18514 -gerrit commit 189ccddcc6e33353ceefaa8a57fabb444079933b Author: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> Date: Mon Feb 27 12:03:39 2017 -0500 Broadwell/sata: Fix a typo in the IOBP setting. Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- src/soc/intel/broadwell/sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index 1f2e690..7b9bd0c 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -161,7 +161,7 @@ static void sata_init(struct device *dev) pch_iobp_update(SATA_IOBP_SP3_SECRT88, ~(SATA_SECRT88_VADJ_MASK << SATA_SECRT88_VADJ_SHIFT), - (config->sata_port2_gen3_tx & + (config->sata_port3_gen3_tx & SATA_SECRT88_VADJ_MASK) << SATA_SECRT88_VADJ_SHIFT);

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New patch to review for coreboot: nb/x4x/raminit.c: Remove ME locking code
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18513 -gerrit commit 7b2e14523348dae8598afa48ec2b32d3e31f9f14 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 16:27:21 2017 +0100 nb/x4x/raminit.c: Remove ME locking code This code ought not to run if ME is disabled. It also prohibits writing to some GMCH regs like GGC bit1. Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit_ddr2.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 9c414e2..51a98e7 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -2155,15 +2155,19 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done power settings\n"); // ME related - if (RANK_IS_POPULATED(s->dimms, 0, 0) - || RANK_IS_POPULATED(s->dimms, 1, 0)) { - MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0); + /* + * FIXME: This locks some registers like bit1 of GGC + * and is only needed in case of ME being used. + */ + if (ME_UMA_SIZEMB != 0) { + if (RANK_IS_POPULATED(s->dimms, 0, 0) + || RANK_IS_POPULATED(s->dimms, 1, 0)) + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0); + if (RANK_IS_POPULATED(s->dimms, 0, 1) + || RANK_IS_POPULATED(s->dimms, 1, 1)) + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1); + MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); } - if (RANK_IS_POPULATED(s->dimms, 0, 1) - || RANK_IS_POPULATED(s->dimms, 1, 1)) { - MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1); - } - MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); printk(BIOS_DEBUG, "Done ddr2\n"); }

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Patch set updated for coreboot: nb/x4x/gma.c: Add disable function
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18504 -gerrit commit 9b4203a9d6a1149081d644bec128a273ef650a78 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 26 23:04:51 2017 +0100 nb/x4x/gma.c: Add disable function This should allow set_vga_bridge_bits() in device.c to disable the integrated GPU when an external GPU is detected. TESTED on ga-g41m-es2l Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 74250fe..a55eee4 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -376,6 +376,23 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); } +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + u16 ggc; + + ggc = pci_read_config16(dev_host, D0F0_GGC); + ggc &= 0xff0f; + ggc |= (1 << 1); + pci_write_config16(dev_host, D0F0_GGC, ggc); + + unsigned int reg32 = pci_read_config32(dev_host, D0F0_DEVEN); + reg32 &= ~(IGD0EN | IGD1EN); + pci_write_config32(dev_host, D0F0_DEVEN, reg32); + + dev->enabled = 0; +} + static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -420,6 +437,7 @@ static struct device_operations gma_func0_ops = { .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, + .disable = gma_func0_disable, }; static const unsigned short pci_device_ids[] =

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Patch set updated for coreboot: nb/x4x/nortbridge.c: Fix resource allocation when IGD is disabled
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18511 -gerrit commit 958526e79cda37ba15e3c7f210b0e3bb4eba4a89 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 13:46:11 2017 +0100 nb/x4x/nortbridge.c: Fix resource allocation when IGD is disabled Computes TSEG size dynamically. Changes the size of legacy hole. Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 47 ++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 1c220b2..8f2068d 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -29,20 +29,20 @@ #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 128; + static void mch_domain_read_resources(device_t dev) { u8 index; u64 tom, touud; - u32 tomk, tseg_sizek, tolud, usable_tomk; + u32 tomk, tseg_sizek, tolud; u32 pcie_config_base, pcie_config_size; - u32 uma_sizek = 0; + u32 uma_sizek = 0, tseg_base; const u32 top32memk = 4 * (GiB / KiB); index = 3; - /* 1024KiB TSEG */ - tseg_sizek = 1024; - pci_domain_read_resources(dev); /* Top of Upper Usable DRAM, including remap */ @@ -64,24 +64,33 @@ static void mch_domain_read_resources(device_t dev) /* Graphics memory comes next */ const u16 ggc = pci_read_config16(dev, D0F0_GGC); - printk(BIOS_DEBUG, "IGD decoded, subtracting "); + if (!(ggc & 2)) { + printk(BIOS_DEBUG, "IGD decoded, subtracting "); - /* Graphics memory */ - const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); - printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + /* Graphics memory */ + const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); + printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + tomk -= gms_sizek; - /* GTT Graphics Stolen Memory Size (GGMS) */ - const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); - printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + /* GTT Graphics Stolen Memory Size (GGMS) */ + const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); + printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + tomk -= gms_sizek; + + uma_sizek = gms_sizek + gsm_sizek; + } - uma_sizek = gms_sizek + gsm_sizek + tseg_sizek; - usable_tomk = tomk - uma_sizek; + tseg_base = pci_read_config32(dev, D0F0_TSEG); + tseg_sizek = ((tomk * 1024ULL) - tseg_base) >> 10; + uma_sizek += tseg_sizek; + tomk -= tseg_sizek; - printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10); + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); /* Report the memory regions */ - ram_resource(dev, index++, 0, 0xa0000 >> 10); - ram_resource(dev, index++, 1*MiB >> 10, (usable_tomk - (1*MiB >> 10))); + ram_resource(dev, index++, 0, legacy_hole_base_k); + ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, + (tomk - (legacy_hole_base_k + legacy_hole_size_k))); /* * If >= 4GB installed then memory from TOLUD to 4GB @@ -95,8 +104,8 @@ static void mch_domain_read_resources(device_t dev) } printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " - "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); - fixed_mem_resource(dev, index++, usable_tomk, uma_sizek, + "size=0x%08x\n", tomk << 10, uma_sizek << 10); + fixed_mem_resource(dev, index++, tomk, uma_sizek, IORESOURCE_RESERVE); /* Reserve high memory where the NB BARs are up to 4GiB */

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New patch to review for coreboot: mb/google/poppy: [TESTONLY] report IMGU device does not support Cache Coherent DMA
by Rizwan Qureshi 27 Feb '17

27 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18512 -gerrit commit b277aadfcdf1ddc4015aa11e56d43cf09df90c22 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Mon Feb 27 21:12:41 2017 +0530 mb/google/poppy: [TESTONLY] report IMGU device does not support Cache Coherent DMA report IMGU device does not support Cache Coherent DMA via _CCA ACPI object Change-Id: I177cca42174fcb0bcc095088df30768b637f42df Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/dsdt.asl | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 2007691..503876a 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -36,6 +36,16 @@ DefinitionBlock( Scope (\_SB) { + + /* Imaging Unit - Device 05, Function 0 */ + + Device (IMGU) + { + Name (_ADR, 0x00050000) + Name (_DDN, "Imaging Unit") + Name (_CCA, ZERO) + } + Device (PWRB) { Name (_HID, EisaId ("PNP0C0C"))

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Patch set updated for coreboot: soc/intel/skylake: Clean up bootblock/systemagent.c
by Subrata Banik 27 Feb '17

27 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18505 -gerrit commit 567398f047bd9dfaf571ad085d57f28f7cb03fc8 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 11:02:19 2017 +0530 soc/intel/skylake: Clean up bootblock/systemagent.c Set up PCIEXBAR length as 256MB. Change-Id: I800fc73d49c83e35ac9ceefec5419af21ddbae2a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/bootblock/systemagent.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c index e76d4d2..911d544 100644 --- a/src/soc/intel/skylake/bootblock/systemagent.c +++ b/src/soc/intel/skylake/bootblock/systemagent.c @@ -38,6 +38,6 @@ void bootblock_systemagent_early_init(void) */ reg = 0; pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MB (buses 0-255) */ pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); }

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Patch set updated for coreboot: nb/x4x/gma.c: Add disable function
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18504 -gerrit commit e51349b01de833d96b86cbaf13f6c34577389da1 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 26 23:04:51 2017 +0100 nb/x4x/gma.c: Add disable function This should allow set_vga_bridge_bits() in device.c to disable the integrated GPU when an external GPU is detected. UNTESTED Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 74250fe..a55eee4 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -376,6 +376,23 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); } +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + u16 ggc; + + ggc = pci_read_config16(dev_host, D0F0_GGC); + ggc &= 0xff0f; + ggc |= (1 << 1); + pci_write_config16(dev_host, D0F0_GGC, ggc); + + unsigned int reg32 = pci_read_config32(dev_host, D0F0_DEVEN); + reg32 &= ~(IGD0EN | IGD1EN); + pci_write_config32(dev_host, D0F0_DEVEN, reg32); + + dev->enabled = 0; +} + static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -420,6 +437,7 @@ static struct device_operations gma_func0_ops = { .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, + .disable = gma_func0_disable, }; static const unsigned short pci_device_ids[] =

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Patch set updated for coreboot: nb/x4x/nortbridge.c: Fix resource allocation when IGD is disabled
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18511 -gerrit commit 28302dabb1caffe320e39b786254bfa7b1c81178 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 13:46:11 2017 +0100 nb/x4x/nortbridge.c: Fix resource allocation when IGD is disabled Computes TSEG size dynamically. Changes the size of legacy hole. Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 47 ++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 1c220b2..8f2068d 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -29,20 +29,20 @@ #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 128; + static void mch_domain_read_resources(device_t dev) { u8 index; u64 tom, touud; - u32 tomk, tseg_sizek, tolud, usable_tomk; + u32 tomk, tseg_sizek, tolud; u32 pcie_config_base, pcie_config_size; - u32 uma_sizek = 0; + u32 uma_sizek = 0, tseg_base; const u32 top32memk = 4 * (GiB / KiB); index = 3; - /* 1024KiB TSEG */ - tseg_sizek = 1024; - pci_domain_read_resources(dev); /* Top of Upper Usable DRAM, including remap */ @@ -64,24 +64,33 @@ static void mch_domain_read_resources(device_t dev) /* Graphics memory comes next */ const u16 ggc = pci_read_config16(dev, D0F0_GGC); - printk(BIOS_DEBUG, "IGD decoded, subtracting "); + if (!(ggc & 2)) { + printk(BIOS_DEBUG, "IGD decoded, subtracting "); - /* Graphics memory */ - const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); - printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + /* Graphics memory */ + const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); + printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + tomk -= gms_sizek; - /* GTT Graphics Stolen Memory Size (GGMS) */ - const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); - printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + /* GTT Graphics Stolen Memory Size (GGMS) */ + const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); + printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + tomk -= gms_sizek; + + uma_sizek = gms_sizek + gsm_sizek; + } - uma_sizek = gms_sizek + gsm_sizek + tseg_sizek; - usable_tomk = tomk - uma_sizek; + tseg_base = pci_read_config32(dev, D0F0_TSEG); + tseg_sizek = ((tomk * 1024ULL) - tseg_base) >> 10; + uma_sizek += tseg_sizek; + tomk -= tseg_sizek; - printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10); + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); /* Report the memory regions */ - ram_resource(dev, index++, 0, 0xa0000 >> 10); - ram_resource(dev, index++, 1*MiB >> 10, (usable_tomk - (1*MiB >> 10))); + ram_resource(dev, index++, 0, legacy_hole_base_k); + ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, + (tomk - (legacy_hole_base_k + legacy_hole_size_k))); /* * If >= 4GB installed then memory from TOLUD to 4GB @@ -95,8 +104,8 @@ static void mch_domain_read_resources(device_t dev) } printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " - "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); - fixed_mem_resource(dev, index++, usable_tomk, uma_sizek, + "size=0x%08x\n", tomk << 10, uma_sizek << 10); + fixed_mem_resource(dev, index++, tomk, uma_sizek, IORESOURCE_RESERVE); /* Reserve high memory where the NB BARs are up to 4GiB */

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coreboot-gerrit February 2017