coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: superiotool: add SMSC KBC1126
by Iru Cai 28 Feb '17

28 Feb '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18480 -gerrit commit e30005f2d78792e5378f39839e580cae45ce6662 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Fri Feb 24 15:35:55 2017 +0800 superiotool: add SMSC KBC1126 Device ID is read from HP Elitebook 2760p. LDNs come from superio/smsc/kbc1100/kbc1100.h. Keyboard and EC registers come from superio/sms/kbc1100/early_init.c. COM1 and Mailbox come from the DSDT dump of 2760p. Change-Id: Id172ae42411a6d42a4ae7c7f30f96aeda3e6c384 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- util/superiotool/smsc.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index 15ba131..3bc85fc 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -68,6 +68,36 @@ static const struct superio_registers reg_table[] = { {0x03, "FDC37C93xFR", { /* FIXME: There's another 0x03 but found on port 0x0d/0x0e! */ {EOT}}}, + {0x07, "KBC1126", { /* Found in HP Elitebook 2760p and 8470p */ + /* FIXME: The registers are mostly copied from MEC1308, + * and LDNs are from superio/smsc/kbc1100/kbc1100.h, + * which may be different in KBC1126.*/ + {NOLDN, NULL, + {0x02,0x03,0x07,0x17,0x20,0x21,0x22,0x23,0x24,0x25, + 0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f, + EOT}, + {0x00,RSVD,0x00,RSVD,0x07,0x00,0x00,0x00,0x04,0x04, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + EOT}}, + {0x1, "Power management (PM1)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x4, "COM1", /* Found in DSDT, used by Wacom serial tablet */ + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x7, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x8, "Embedded controller (EC)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x62,EOT}}, + {0x9, "Mailbox", /* Found in DSDT, named MAIO */ + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0xa, "LPC/8051 addressable GPIO (LGPIO)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {EOT}}}, {0x0a, "FDC37N971", { {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,

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New patch to review for coreboot: google/veyron: add K4B4G1646E-BYK0 ddr with ramid 000Z
by Patrick Georgi 28 Feb '17

28 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18519 -gerrit commit 6478ee76e75c03a3f75728c1af7042526a5d9c6d Author: Shunqian Zheng <zhengsq(a)rock-chips.com> Date: Thu Feb 23 09:34:40 2017 +0800 google/veyron: add K4B4G1646E-BYK0 ddr with ramid 000Z The K4B4G1646E-BYK0 shares sdram config with K4B4G1646D-BYK0. For clarity, sdram-ddr3-samsung-2GB now is used by - K4B4G1646D-BYK0 - K4B4G1646E-BYK0 - K4B4G1646Q-HYK0 BUG=chrome-os-partner:62131 BRANCH=veyron TEST=emerge Change-Id: Ie43f23bf8f5f5b1acbb74c85cac17fe181c841c4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 46d62d87101e0ee1050b00db02b3ecaa4587e9f4 Original-Change-Id: I461c6f36c28ea0eeaf7d64292c9c87ab0c9de443 Original-Signed-off-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/446197 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-(cherry picked from commit f98251a4a4fe4d49721a936a684f6ac80f3f6405) Original-Reviewed-on: https://chromium-review.googlesource.com/446300 --- src/mainboard/google/veyron/sdram_configs.c | 2 +- src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc | 2 +- src/mainboard/google/veyron_mickey/sdram_configs.c | 2 +- src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-2GB.inc | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index 04a88c4..88c0a69 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -37,7 +37,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 000Z */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 000Z */ #include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */ diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc index f5793d1..d2186ac 100644 --- a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -1,5 +1,5 @@ { - /* two Samsung K4B4G1646D-BYK0 chips */ + /* two Samsung K4B4G1646D-BYK0/K4B4G1646E-BYK0/K4B4G1646Q-HYK0 chips */ { { .rank = 0x1, diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 04a88c4..88c0a69 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -37,7 +37,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 000Z */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 000Z */ #include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */ diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-2GB.inc index f5793d1..d2186ac 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -1,5 +1,5 @@ { - /* two Samsung K4B4G1646D-BYK0 chips */ + /* two Samsung K4B4G1646D-BYK0/K4B4G1646E-BYK0/K4B4G1646Q-HYK0 chips */ { { .rank = 0x1,

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New patch to review for coreboot: google/veyron_*: Add new Micron and Hynix modules
by Patrick Georgi 28 Feb '17

28 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18518 -gerrit commit 5ebee7c5bed8e5dae54acc1574e410cbbf855cca Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Nov 17 14:19:51 2016 -0800 google/veyron_*: Add new Micron and Hynix modules This adds SDRAM entries for the following modules: - Micron: DDMT52L256M64D2PP-107 - Hynix: H9CCNNNBKTALBR-NUD They are compatible with Samsung K4E8E324EB-EGCF, so this just copies sdram-lpddr3-samsung-2GB-24EB.inc and changes the name used in the comment near the top. Notes on our "special snowflake" boards: - veyron_danger's RAM ID is hard-coded to zero, so I skipped changes involving the binary first numbering scheme. - Rialto's SDRAM mapping is different, so I padded its SDRAM entries to 24 to match other boards. - veyron_mickey requires different MR3 and ODT settings than other boards due to its unique PCB (chrome-os-partner:43626). BUG=chrome-os-partner:59997 BRANCH=none TEST=Booted new modules on Mickey (see BUG) Change-Id: If2e22c83f4a08743f12bbc49b3fabcbf1d7d07dd Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 35cac483e86e57899dbb0898dad3510f4c2ab2d3 Original-Change-Id: I22386a25b965a4b96194d053b97e3269dbdea8c7 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/412328 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Queue: Jiazi Yang <Tomato_Yang(a)asus.com> Original-Tested-by: Jiazi Yang <Tomato_Yang(a)asus.com> Original-(cherry picked from commit bd5aa1a5488b99f2edc3e79951064a1f824062f6) Original-Reviewed-on: https://chromium-review.googlesource.com/446299 Original-Commit-Ready: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron/boardid.c | 2 +- src/mainboard/google/veyron/sdram_configs.c | 10 +++ .../veyron/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc | 78 ++++++++++++++++++++++ .../sdram_inf/sdram-lpddr3-micron-2GB-D2.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_mickey/boardid.c | 2 +- src/mainboard/google/veyron_mickey/sdram_configs.c | 10 +++ .../sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc | 78 ++++++++++++++++++++++ .../sdram_inf/sdram-lpddr3-micron-2GB-D2.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_rialto/boardid.c | 2 +- src/mainboard/google/veyron_rialto/sdram_configs.c | 10 +++ 10 files changed, 345 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c index a610471..47e946e 100644 --- a/src/mainboard/google/veyron/boardid.c +++ b/src/mainboard/google/veyron/boardid.c @@ -38,7 +38,7 @@ uint32_t ram_code(void) gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ - code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); printk(BIOS_SPEW, "RAM Config: %u.\n", code); return code; diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index 76e4f76..04a88c4 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -37,8 +37,18 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 000Z */ +#include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ +#include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 01Z0 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 24, "Must have 24 sdram_configs!"); + const struct rk3288_sdram_params *get_sdram_config() { u32 ramcode = ram_code(); diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc new file mode 100644 index 0000000..8e0c37a --- /dev/null +++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc @@ -0,0 +1,78 @@ +{ + /* 2 Hynix H9CCNNNBKTALBR-NUD chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x2 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 1, +}, diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc new file mode 100644 index 0000000..94ee5b1 --- /dev/null +++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc @@ -0,0 +1,78 @@ +{ + /* 2 Micron DDMT52L256M64D2PP-107 chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x2 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 1, +}, diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c index a610471..47e946e 100644 --- a/src/mainboard/google/veyron_mickey/boardid.c +++ b/src/mainboard/google/veyron_mickey/boardid.c @@ -38,7 +38,7 @@ uint32_t ram_code(void) gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ - code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); printk(BIOS_SPEW, "RAM Config: %u.\n", code); return code; diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 76e4f76..04a88c4 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -37,8 +37,18 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 000Z */ +#include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ +#include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 01Z0 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 24, "Must have 24 sdram_configs!"); + const struct rk3288_sdram_params *get_sdram_config() { u32 ramcode = ram_code(); diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc new file mode 100644 index 0000000..8e0c37a --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc @@ -0,0 +1,78 @@ +{ + /* 2 Hynix H9CCNNNBKTALBR-NUD chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x2 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 1, +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc new file mode 100644 index 0000000..94ee5b1 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-micron-2GB-D2.inc @@ -0,0 +1,78 @@ +{ + /* 2 Micron DDMT52L256M64D2PP-107 chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x2 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 1, +}, diff --git a/src/mainboard/google/veyron_rialto/boardid.c b/src/mainboard/google/veyron_rialto/boardid.c index a610471..47e946e 100644 --- a/src/mainboard/google/veyron_rialto/boardid.c +++ b/src/mainboard/google/veyron_rialto/boardid.c @@ -38,7 +38,7 @@ uint32_t ram_code(void) gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ - code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); printk(BIOS_SPEW, "RAM Config: %u.\n", code); return code; diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 0e260c3..eba7a39 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -37,8 +37,18 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 000Z */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 001Z */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z0 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 01Z0 */ }; +_Static_assert(ARRAY_SIZE(sdram_configs) == 24, "Must have 24 sdram_configs!"); + const struct rk3288_sdram_params *get_sdram_config() { u32 ramcode = ram_code();

1 0

Patch set updated for coreboot: mainboard/google/reef: Configure SDCARD card detect pin
by Venkateswarlu V Vinjamuri 28 Feb '17

28 Feb '17

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18497 -gerrit commit bebcfc3ba8eee088ae5bbb2cfff71bf7a267898f Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Fri Feb 24 15:54:39 2017 -0800 mainboard/google/reef: Configure SDCARD card detect pin This configures GPIO_177 as GPI for SDCARD card detect. BUG=chrome-os-partner:63070 TEST=None Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 3 +++ src/mainboard/google/reef/variants/baseboard/gpio.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index b0c82e2..443918e 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -17,6 +17,9 @@ chip soc/intel/apollolake # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF register "prt0_gpio" = "GPIO_122" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPIO_177" + # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. # [14:8] steps of delay for HS400, each 125ps. diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index a9a6248..0c866b6 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -59,7 +59,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ /* Card detect is active LOW with external pull up. */ - PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_GPI(GPIO_177, NONE, DEEP), /* SDCARD_CD_N */ PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ /* CLK feedback, internal signal, needs 20K pull down */ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add PM methods to power gate SD card
by Venkateswarlu V Vinjamuri 28 Feb '17

28 Feb '17

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18496 -gerrit commit 094f8f0be2d6b69f0bdd025789b16fd046fbdc71 Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Fri Feb 24 15:37:30 2017 -0800 soc/intel/apollolake: Add PM methods to power gate SD card This implements GNVS variable to store the address of GPIO_177. _PS0/_PS3 methods to power gate the sd card controller. BUG=chrome-os-partner:63070 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should enter S0ix and resume with no issue. Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 4 +++ src/soc/intel/apollolake/acpi/globalnvs.asl | 1 + src/soc/intel/apollolake/acpi/scs.asl | 49 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 3 ++ src/soc/intel/apollolake/include/soc/nvs.h | 3 +- 5 files changed, 59 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 3c1faa5..6aa985d 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -183,6 +183,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) /* Assign address of PERST_0 if GPIO is defined in devicetree */ if (cfg->prt0_gpio != GPIO_PRT0_UDEF) gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio); + + /* Assign Gpio address of SDCARD Card detect */ + gnvs->sdcd = (uintptr_t)gpio_dwx_address(cfg->sdcard_cd_gpio); + } /* Save wake source information for calculating ACPI _SWS values */ diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 657c834..947120d 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -39,6 +39,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) NHLA, 64, // 0x19 - 0x20 - NHLT Address NHLL, 32, // 0x21 - 0x24 - NHLT Length PRT0, 32, // 0x25 - 0x28 - PERST_0 Address + SDCD, 32, // 0x29 - 0x2D - SD_CD Address /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl index 4108017..ddc239e 100644 --- a/src/soc/intel/apollolake/acpi/scs.asl +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -22,6 +22,9 @@ Scope (\_SB.PCI0) { Field (SBMM, DWordAcc, NoLock, Preserve) { GENR, 32, + Offset (0x08), + , 5, + GRR3, 1, } /* SCC power gate control method, this method must be serialized as @@ -64,4 +67,50 @@ Scope (\_SB.PCI0) { ^^SCPG(1,0x00000041) } } /* Device (SDHA) */ + + /* SD CARD */ + Device (SDC) + { + Name (_ADR, 0x001B0000) + + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 0, + "\\_SB.GPO3", 0, ResourceConsumer, , ) {26} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + OperationRegion (PCCS, PCI_Config, 0x84, 0x04) + Field (PCCS, WordAcc, NoLock, Preserve) { + PMSR, 32 /* 4h: Power Gating Control */ + } + + Method (_PS0, 0, NotSerialized) + { + + /* Extract the RXstate of SDcard Card detect pin */ + Store (\_SB.GPC0 (\SDCD), Local1) + And (Local1, 0x2, Local1) + Not (Local1, \_SB.PCI0.GRR3) + + /* Disable power gate by clearing bit 1 and 0 */ + And (^PMSR, 0xFFFFFFFC, ^PMSR) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + + /* Enable power gate by restore bit 1 and 0 */ + Store (0, \_SB.PCI0.GRR3) + Or (^PMSR, 0x3, ^PMSR) + + } + + } /* Device (SDC) */ } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index d60ffbf..22d3b4e 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -117,6 +117,9 @@ struct soc_intel_apollolake_config { /* GPIO pin for PERST_0 */ uint16_t prt0_gpio; + /* GPIO pin for SDCARD Card Detect */ + uint16_t sdcard_cd_gpio; + /* USB2 eye diagram settings per port */ struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX]; diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 21894ca..1e774b8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -39,7 +39,8 @@ typedef struct global_nvs_t { uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ - uint8_t unused[215]; + uint32_t sdcd; /* 0x29 - 0x2D - SD_CD Address */ + uint8_t unused[211]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

1 0

Patch set updated for coreboot: nb/intel/x4x: Add support for second PEG slot
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18516 -gerrit commit e3e8fe6f14fe7aa8ea8207b31d6e3f643b62a308 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 21:45:07 2017 +0100 nb/intel/x4x: Add support for second PEG slot Is only present on the P45 subtype of chipset. Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 8f2068d..7cf778a 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -182,8 +182,12 @@ static void x4x_init(void *const chip_info) struct device *const d0f0 = dev_find_slot(0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { + for (dev = 6; dev > 0; --dev) { switch (dev) { + case 6: /* PEG1: only on P45 */ + fn = 0; + bit_base = 13; + break; case 3: /* ME */ fn = 3; bit_base = 6; @@ -192,10 +196,13 @@ static void x4x_init(void *const chip_info) fn = 1; bit_base = 3; break; - case 1: /* PEG */ + case 1: /* PEG0 */ fn = 0; bit_base = 1; break; + case 4: /* Should not happen */ + case 5: + continue; } for (; fn >= 0; --fn) { const struct device *const d =

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Patch set updated for coreboot: nb/x4x: Do not enable IGD when not supported
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18515 -gerrit commit 19906decddfce25a0cd41e3d9edab75d53e7ff35 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 20:14:21 2017 +0100 nb/x4x: Do not enable IGD when not supported According to "Intel ® 4 Series Chipset Family datasheet" in the description about GGC and DEVEN, CAPID0 bit48 is said to reflect the presence of an internal graphic device. This would allow the P43 and P45 chipset variants to work. Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/early_init.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 7d6afc9..33fc797 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -54,16 +54,22 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); - /* Enable internal GFX */ - pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - /* Set preallocated IGD size from cmos */ - u8 gfxsize; - - if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 6 for 64MB, default if not set in cmos */ - gfxsize = 6; + if (pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32))) { + /* Enable internal GFX */ + pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); + /* Set preallocated IGD size from cmos */ + u8 gfxsize; + + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { + /* 6 for 64MB, default if not set in cmos */ + gfxsize = 6; + } + pci_write_config16(d0f0, D0F0_GGC, + 0x0100 | ((gfxsize + 1) << 4)); + } else { /* Does not feature internal graphics */ + pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN); + pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); } - pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); } static void init_egress(void)

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New patch to review for coreboot: .gitignore: Add autoport
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18517 -gerrit commit 6837806cb014aff7912efc71b2fa8a54403127c8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 21:54:18 2017 +0100 .gitignore: Add autoport Change-Id: I610797d5002b229211e320a814ce14131cc1dfe7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 48c9648..5383e11 100644 --- a/.gitignore +++ b/.gitignore @@ -113,6 +113,7 @@ util/runfw/googlesnow util/superiotool/superiotool util/vgabios/testbios util/viatool/viatool +util/autoport/autoport documentation/*.aux documentation/*.idx

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Patch set updated for coreboot: nb/intel/x4x: Add support for second PEG slot
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18516 -gerrit commit ad9cb86fcc584f336d6edc4cda830982acdf7072 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 21:45:07 2017 +0100 nb/intel/x4x: Add support for second PEG slot Is only present on the P45 subtype of chipset. Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 8f2068d..7cf778a 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -182,8 +182,12 @@ static void x4x_init(void *const chip_info) struct device *const d0f0 = dev_find_slot(0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { + for (dev = 6; dev > 0; --dev) { switch (dev) { + case 6: /* PEG1: only on P45 */ + fn = 0; + bit_base = 13; + break; case 3: /* ME */ fn = 3; bit_base = 6; @@ -192,10 +196,13 @@ static void x4x_init(void *const chip_info) fn = 1; bit_base = 3; break; - case 1: /* PEG */ + case 1: /* PEG0 */ fn = 0; bit_base = 1; break; + case 4: /* Should not happen */ + case 5: + continue; } for (; fn >= 0; --fn) { const struct device *const d =

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New patch to review for coreboot: nb/intel/x4x: Add support for second PEG slot
by Arthur Heymans 27 Feb '17

27 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18516 -gerrit commit bd7f65f5672b57348610b775bffb08b2cc87765d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 21:45:07 2017 +0100 nb/intel/x4x: Add support for second PEG slot Is only present on the P45 subtype of chipset. Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/northbridge.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 8f2068d..2aca8e3 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -182,8 +182,12 @@ static void x4x_init(void *const chip_info) struct device *const d0f0 = dev_find_slot(0, 0); /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { + for (dev = 6; dev > 0; --dev) { switch (dev) { + case 6: /* PEG1: only on P45 */ + fn = 0; + bit_base = 13; + break; case 3: /* ME */ fn = 3; bit_base = 6; @@ -192,10 +196,13 @@ static void x4x_init(void *const chip_info) fn = 1; bit_base = 3; break; - case 1: /* PEG */ + case 1: /* PEG0 */ fn = 0; bit_base = 1; break; + case 4: /* Should not happen */ + case 5: + break; } for (; fn >= 0; --fn) { const struct device *const d =

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coreboot-gerrit February 2017