coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: cpu/intel/model_6{e, f}x: Unify init files
by Paul Menzel 27 Feb '17

27 Feb '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18506 -gerrit commit 16fed97097debc5171e6ecc3fed3db1fa49897bd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Feb 27 01:01:55 2017 +0100 cpu/intel/model_6{e,f}x: Unify init files The init files for the Core Duo and Core 2 Duo are very similar. Reduce the differences, by using the same order for the include statements, the same blank lines, and the same comments. Change-Id: I0de060222a61a482377c760c6031d73c7e318edf Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/model_6ex/model_6ex_init.c | 13 ++++++++----- src/cpu/intel/model_6fx/model_6fx_init.c | 11 +++++------ 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index cc1260e..e1f9c2d 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -21,8 +21,8 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -34,10 +34,10 @@ static void configure_c_states(void) msr_t msr; msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // config lock until next reset. - msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States + msr.lo |= (1 << 15); // config lock until next reset + msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-states msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo |= (1 << 3); //dynamic L2 + msr.lo |= (1 << 3); // dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -50,7 +50,7 @@ static void configure_c_states(void) msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); wrmsr(MSR_PMG_IO_BASE_ADDR, msr); - /* set C_LVL controls */ + /* Set C_LVL controls and IO Capture Address */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); @@ -128,6 +128,9 @@ static void model_6ex_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index d29895b..4922e80 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -21,9 +21,9 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/hyperthreading.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/intel/common/common.h> @@ -34,12 +34,11 @@ static void configure_c_states(void) msr_t msr; msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 14); // Deeper Sleep - msr.lo |= (1 << 10); // Enable IO MWAIT redirection - msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo |= (1 << 3); // Dynamic L2 + msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-states + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + msr.lo |= (1 << 3); // dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -47,7 +46,7 @@ static void configure_c_states(void) wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); - /* Set Processor MWAIT IO BASE */ + /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); wrmsr(MSR_PMG_IO_BASE_ADDR, msr);

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Patch set updated for coreboot: drivers/spi: Measure execution time of `spi_flash_probe()`
by Paul Menzel 27 Feb '17

27 Feb '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18503 -gerrit commit 1c161da0148c17a921b0cc7aef6f7f99b4c238d9 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 26 19:58:24 2017 +0100 drivers/spi: Measure execution time of `spi_flash_probe()` Stop the time of the execution of the method `spi_flash_probe()`. It’s useful to analyze the boot process, and to compare different flash ROM chips. TEST=Build and boot on ASRock E350M1, and observe the new messages. ``` Manufacturer: ef SF: Detected W25Q32 with sector size 0x1000, total 0x400000 spi_flash_probe: Probing the flash chip took 24 usecs SF: Successfully erased 4096 bytes @ 0xffff1000 Manufacturer: ef SF: Detected W25Q32 with sector size 0x1000, total 0x400000 spi_flash_probe: Probing the flash chip took 21 usecs SF: Successfully erased 4096 bytes @ 0xffff0000 ``` Change-Id: I448e12508b09a8796c5351b17495113afe9a50ef Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/drivers/spi/spi_flash.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 95362f2..b2e928b 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -331,6 +331,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) { struct spi_slave spi; struct spi_flash *flash; + struct stopwatch sw; + + stopwatch_init(&sw); if (spi_setup_slave(bus, cs, &spi)) { printk(BIOS_WARNING, "SF: Failed to set up slave\n"); @@ -365,6 +368,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) CONFIG_BOOT_DEVICE_SPI_FLASH_BUS == bus && !spi_flash_dev) spi_flash_dev = flash; + printk(BIOS_DEBUG, "%s: Probing the flash chip took %ld usecs\n", + __func__, stopwatch_duration_usecs(&sw)); + return flash; }

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New patch to review for coreboot: soc/intel/skylake: Clean up bootblock/systemagent.c
by Subrata Banik 27 Feb '17

27 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18505 -gerrit commit 84d740468f8ab653d94b87c67d608a646be2e508 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 11:02:19 2017 +0530 soc/intel/skylake: Clean up bootblock/systemagent.c Don't need to touch PCIEXBAR reserve bit, hence removed. Change-Id: I800fc73d49c83e35ac9ceefec5419af21ddbae2a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/bootblock/systemagent.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c index e76d4d2..0ce4c6c 100644 --- a/src/soc/intel/skylake/bootblock/systemagent.c +++ b/src/soc/intel/skylake/bootblock/systemagent.c @@ -38,6 +38,6 @@ void bootblock_systemagent_early_init(void) */ reg = 0; pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 64MiB - 0-63 buses. */ pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); }

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Patch set updated for coreboot: vendorcode/amd/pi/00670F00: Clean up CAR disable
by Marshall Dawson 27 Feb '17

27 Feb '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18492 -gerrit commit 71f9703cbe32e3ac3efbe44e1531bc1e91ce9d6f Author: Marc Jones <marcj303(a)gmail.com> Date: Fri Feb 24 16:40:41 2017 -0700 vendorcode/amd/pi/00670F00: Clean up CAR disable Clean up the AMD_DISABLE_STACK_FAMILY_HOOK_F15 to be clear that it does a wbinvd to preserve the coreboot stack and CAR globals. The Stoney Ridge uses a different S3 architecture, so this is not an issue of reserving or relocating the stack on a resume. Change-Id: I77e53262212e00bce9145b0bc3909ad8651f2328 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc index d6782a3..4005057 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc @@ -401,6 +401,14 @@ fam15_enable_stack_hook_exit: * Return any family specific controls to their 'standard' * settings for using cache with main memory. * +* Note: Customized for coreboot: +* A wbinvd is used to send cache to memory to preserve stack and +* coreboot CAR globals. This should NOT be used with S3 resume IF the +* stack/cache area is not reserved and over system memory. +* +* This CPU resume path doesn't use CAR, but be careful if porting to +* other CPUs. +* * Inputs: * ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# * Outputs: @@ -634,11 +642,13 @@ fam15_disable_stack_remote_read_exit: # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. #-------------------------------------------------------------------------- - mov $HWCR, %ecx # MSR:C001_0015h - _RDMSR - btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion - _WRMSR - wbinvd #bao # Clear the cache tag RAMs + #-------------------------------------------------------------------------- + # Send cache to memory. Preserve stack and coreboot CAR globals. + # This shouldn't be used with S3 resume IF the stack/cache area is + # not reserved and over system memory. + #-------------------------------------------------------------------------- + wbinvd # Clear the cache tag RAMs + # #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? # cmp $01, %bh # jz 4f

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New patch to review for coreboot: nb/x4x/gma.c: Add disable function.
by Arthur Heymans 26 Feb '17

26 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18504 -gerrit commit bb2a6fe97daba58971b6e02fdb956b552fbd2384 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 26 23:04:51 2017 +0100 nb/x4x/gma.c: Add disable function. This should allow set_vga_bridge_bits() in device.c to disable the integrated GPU when an external GPU is detected. UNTESTED Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 74250fe..0d41afe 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -376,6 +376,19 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); } +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + + pci_write_config16(dev_host, D0F0_GGC, (1 << 1)); + + unsigned int reg32 = pci_read_config32(dev_host, D0F0_DEVEN); + reg32 &= ~(IGD0EN | IGD1EN); + pci_write_config32(dev_host, D0F0_DEVEN, reg32); + + dev->enabled = 0; +} + static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -420,6 +433,7 @@ static struct device_operations gma_func0_ops = { .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, + .disable = gma_func0_disable, }; static const unsigned short pci_device_ids[] =

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Patch set updated for coreboot: ec/lenovo/h8: Add USB Always On fields
by Alexander Couzens 26 Feb '17

26 Feb '17

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12888 -gerrit commit c85017fda3a3dd90a37066618b92092e00e625be Author: Marian Tietz <mtcoreboot(a)gmail.com> Date: Sat Jan 9 17:41:14 2016 +0100 ec/lenovo/h8: Add USB Always On fields USB AO is the internal name for the dedicated charging port on ThinkPads when in S3 or lower. AOEN is used for enabling the feature (on PTS) and AOCF is the configuration field for the different modes. The modes are (according to Peter Stuge): 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off 10, 01 => equivalent to 00 This commit also activates this feature on the X220. On PTS activate the dedicated charging port to work under AC in all states and in battery under S3. On wake-up the port is set back to USB2 mode. To test this functionality USB devices (e.g. a smartphone) should be able to negotiate full power from the dedicated charging port in S3 using a normal data cable. Without the Always On functionality this is not possible. Change-Id: Ief8de3e41fd6a701c6b3dbce81118d5eeb0fa648 Signed-off-by: Marian Tietz <mtcoreboot(a)gmail.com> --- src/ec/lenovo/h8/acpi/ec.asl | 4 ++++ src/mainboard/lenovo/x220/acpi/platform.asl | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index b69acf8..340443d 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -32,6 +32,10 @@ Device(EC) HSPA, 1, Offset (0x0C), LEDS, 8, /* LED state */ + Offset (0x0D), + AOEN, 1, /* USB Always On Enable */ + , 1, + AOCF, 2, /* USB Always On Config */ Offset (0x1a), DKR2, 1, /* Dock register 2 */ Offset (0x2a), diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index 3e9225c..70e6088 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -20,6 +20,15 @@ Method(_PTS,1) { \_SB.PCI0.LPCB.EC.RADI(0) + + Store (1, \_SB.PCI0.LPCB.EC.AOEN) + + /* + * 00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off + * 11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off + * 10, 01 => equivalent to 00 + */ + Store (0, \_SB.PCI0.LPCB.EC.AOCF) } /* The _WAK method is called on system wakeup */ @@ -30,6 +39,9 @@ Method(_WAK,1) Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) + /* Deactivate dedicated charging port, activate USB2.0 */ + Store (0, \_SB.PCI0.LPCB.EC.AOEN) + /* Not implemented. */ Return(Package(){0,0}) }

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New patch to review for coreboot: drivers/spi: Measure execution time of `spi_flash_probe()`
by Paul Menzel 26 Feb '17

26 Feb '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18503 -gerrit commit c8d16be346a2eab7e05607c0d532a3ec1d974f19 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 26 19:58:24 2017 +0100 drivers/spi: Measure execution time of `spi_flash_probe()` Stop the time of the execution of the method `spi_flash_probe()`. It’s useful to analyze the boot process, and to compare different flash ROM chips. Change-Id: I448e12508b09a8796c5351b17495113afe9a50ef Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/drivers/spi/spi_flash.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 95362f2..b2e928b 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -331,6 +331,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) { struct spi_slave spi; struct spi_flash *flash; + struct stopwatch sw; + + stopwatch_init(&sw); if (spi_setup_slave(bus, cs, &spi)) { printk(BIOS_WARNING, "SF: Failed to set up slave\n"); @@ -365,6 +368,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) CONFIG_BOOT_DEVICE_SPI_FLASH_BUS == bus && !spi_flash_dev) spi_flash_dev = flash; + printk(BIOS_DEBUG, "%s: Probing the flash chip took %ld usecs\n", + __func__, stopwatch_duration_usecs(&sw)); + return flash; }

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Patch set updated for coreboot: .gitignore: ignore *.swo and option *.roms
by Alexander Couzens 26 Feb '17

26 Feb '17

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15220 -gerrit commit 6b56ce2dde00e58c3e705beff9091d74d39ae0e4 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Jun 16 19:53:39 2016 -0700 .gitignore: ignore *.swo and option *.roms Change-Id: I7403f548bae918ca813a9295bfb095a7c4c51e21 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 48c9648..30bd579 100644 --- a/.gitignore +++ b/.gitignore @@ -58,7 +58,8 @@ site-local *.o *.out *.pyc -*.swp +*.sw[po] +/*.rom # Development friendly files tags

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Patch set updated for coreboot: libpayload: Fix and improve rtc functions
by Patrick Rudolph 26 Feb '17

26 Feb '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18498 -gerrit commit 8008c8e93c47e5688a1b719b7114fa58bea3feb1 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Feb 25 09:56:53 2017 +0100 libpayload: Fix and improve rtc functions On Lenovo T500 the RTC readings where wrong, as RTC has different encodings, depending on the statusB register. Support BCD vs binary RTC format and AM/PM vs 24h RTC format. Fixes wrong date and time on Lenovo T500. Add a function to write RTC. Writing the RTC allows payloads to easily change the RTC. Change-Id: Id773c33e228973e190a7e14c3d11979678b1a619 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- payloads/libpayload/drivers/nvram.c | 100 +++++++++++++++++++++++++++---- payloads/libpayload/include/libpayload.h | 2 + 2 files changed, 92 insertions(+), 10 deletions(-) diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c index c825331..6e2ebdc 100644 --- a/payloads/libpayload/drivers/nvram.c +++ b/payloads/libpayload/drivers/nvram.c @@ -2,6 +2,7 @@ * This file is part of the libpayload project. * * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -111,23 +112,102 @@ int nvram_updating(void) */ void rtc_read_clock(struct tm *time) { - memset(time, 0, sizeof(*time)); + u16 timeout = 10000; + u8 statusB; + u8 reg8; - while(nvram_updating()); + memset(time, 0, sizeof(*time)); - time->tm_mon = bcd2dec(nvram_read(NVRAM_RTC_MONTH)) - 1; - time->tm_sec = bcd2dec(nvram_read(NVRAM_RTC_SECONDS)); - time->tm_min = bcd2dec(nvram_read(NVRAM_RTC_MINUTES)); - time->tm_mday = bcd2dec(nvram_read(NVRAM_RTC_DAY)); - time->tm_hour = bcd2dec(nvram_read(NVRAM_RTC_HOURS)); + while (nvram_updating()) + if (!timeout--) + return; + + statusB = nvram_read(NVRAM_RTC_STATUSB); + + if (!(statusB & 0x04)) { + time->tm_mon = bcd2dec(nvram_read(NVRAM_RTC_MONTH)) - 1; + time->tm_sec = bcd2dec(nvram_read(NVRAM_RTC_SECONDS)); + time->tm_min = bcd2dec(nvram_read(NVRAM_RTC_MINUTES)); + time->tm_mday = bcd2dec(nvram_read(NVRAM_RTC_DAY)); + + if (!(statusB & 0x02)) { + reg8 = nvram_read(NVRAM_RTC_HOURS); + time->tm_hour = bcd2dec(reg8 & 0x7f); + time->tm_hour += (reg8 & 0x80) ? 12 : 0; + time->tm_hour %= 24; + } else + time->tm_hour = bcd2dec(nvram_read(NVRAM_RTC_HOURS)); + time->tm_year = bcd2dec(nvram_read(NVRAM_RTC_YEAR)); + } else { + time->tm_mon = nvram_read(NVRAM_RTC_MONTH) - 1; + time->tm_sec = nvram_read(NVRAM_RTC_SECONDS); + time->tm_min = nvram_read(NVRAM_RTC_MINUTES); + time->tm_mday = nvram_read(NVRAM_RTC_DAY); + if (!(statusB & 0x02)) { + reg8 = nvram_read(NVRAM_RTC_HOURS); + time->tm_hour = reg8 & 0x7f; + time->tm_hour += (reg8 & 0x80) ? 12 : 0; + time->tm_hour %= 24; + } else + time->tm_hour = nvram_read(NVRAM_RTC_HOURS); + time->tm_year = nvram_read(NVRAM_RTC_YEAR); + } /* Instead of finding the century register, we just make an assumption that if the year value is less then 80, then it is 2000+ */ - - time->tm_year = bcd2dec(nvram_read(NVRAM_RTC_YEAR)); - if (time->tm_year < 80) time->tm_year += 100; } + +/** + * Write the current time and date to the RTC + * + * @param time A pointer to a broken-down time structure + */ +void rtc_write_clock(struct tm *time) +{ + u16 timeout = 10000; + u8 statusB; + u8 reg8; + + while (nvram_updating()) + if (!timeout--) + return; + + statusB = nvram_read(NVRAM_RTC_STATUSB); + + if (time->tm_year > 100) + time->tm_year -= 100; + + if (!(statusB & 0x04)) { + nvram_write(dec2bcd(time->tm_mon + 1), NVRAM_RTC_MONTH); + nvram_write(dec2bcd(time->tm_sec), NVRAM_RTC_SECONDS); + nvram_write(dec2bcd(time->tm_min), NVRAM_RTC_MINUTES); + nvram_write(dec2bcd(time->tm_mday), NVRAM_RTC_DAY); + if (!(statusB & 0x02)) { + if (time->tm_hour > 12) + reg8 = dec2bcd(time->tm_hour - 12) | 0x80; + else + reg8 = dec2bcd(time->tm_hour); + } else + reg8 = dec2bcd(time->tm_hour); + nvram_write(reg8, NVRAM_RTC_HOURS); + nvram_write(dec2bcd(time->tm_year), NVRAM_RTC_YEAR); + } else { + nvram_write(time->tm_mon + 1, NVRAM_RTC_MONTH); + nvram_write(time->tm_sec, NVRAM_RTC_SECONDS); + nvram_write(time->tm_min, NVRAM_RTC_MINUTES); + nvram_write(time->tm_mday, NVRAM_RTC_DAY); + if (!(statusB & 0x02)) { + if (time->tm_hour > 12) + reg8 = (time->tm_hour - 12) | 0x80; + else + reg8 = time->tm_hour; + } else + reg8 = time->tm_hour; + nvram_write(reg8, NVRAM_RTC_HOURS); + nvram_write(time->tm_year, NVRAM_RTC_YEAR); + } +} diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 97d5944..53c96cd 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -104,6 +104,7 @@ static const char _pstruct(key)[] \ #define NVRAM_RTC_MONTH 8 /**< RTC Month offset in CMOS */ #define NVRAM_RTC_YEAR 9 /**< RTC Year offset in CMOS */ #define NVRAM_RTC_FREQ_SELECT 10 /**< RTC Update Status Register */ +#define NVRAM_RTC_STATUSB 11 /**< RTC Status Register B */ #define NVRAM_RTC_UIP 0x80 /** Broken down time structure */ @@ -123,6 +124,7 @@ u8 nvram_read(u8 addr); void nvram_write(u8 val, u8 addr); int nvram_updating(void); void rtc_read_clock(struct tm *tm); +void rtc_write_clock(struct tm *time); /** @} */ /**

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Patch set updated for coreboot: libpayload: Enable SSE and FPU when present
by Patrick Rudolph 26 Feb '17

26 Feb '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18345 -gerrit commit af7b7fcd70ebea8df74384ef0e012b28c203cb2e Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 15 10:49:48 2017 +0100 libpayload: Enable SSE and FPU when present Allows to use SSE and floating point in payloads without digging to much into x86 assembly code. Tested on Lenovo T500 (Intel Core2Duo). Both floating point operation and SSE is properly working. Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- payloads/libpayload/arch/x86/head.S | 43 +++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/payloads/libpayload/arch/x86/head.S b/payloads/libpayload/arch/x86/head.S index 94a4d41..7f2ea15 100644 --- a/payloads/libpayload/arch/x86/head.S +++ b/payloads/libpayload/arch/x86/head.S @@ -2,6 +2,7 @@ * This file is part of the libpayload project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -89,6 +90,48 @@ _init: movl $_stack, %esp pushl %eax + /* Enable special x86 functions if present. */ + pushl %eax + pushl %ebx + pushl %ecx + pushl %edx + + movl $0, %eax + cpuid + /* Test if CPUID(eax=1) is available. */ + test %eax, %eax + je cpuid_done + + /* Get CPU features. */ + movl $1, %eax + cpuid + +cpuid_fpu: + /* Test if x87 FPU is present */ + test $1, %edx + je cpuid_see + + fninit + movl %cr0, %eax + andl $0xFFFFFFFB, %eax /* clear EM */ + orl $0x00000022, %eax /* set MP, NE */ + movl %eax, %cr0 + +cpuid_see: + /* Test if SSE is available */ + test $0x02000000, %edx + je cpuid_done + + movl %cr4, %eax + orl $0x00000600, %eax /* set OSFXSR, OSXMMEXCPT */ + movl %eax, %cr4 + +cpuid_done: + popl %edx + popl %ecx + popl %ebx + popl %eax + /* Let's rock. */ call start_main

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coreboot-gerrit February 2017