coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: mb/emulation/*-riscv: Don't select ARCH_BOOTBLOCK_RISCV
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit c706eaf068515690184b3a67ee255a265a808618 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Feb 17 18:06:33 2017 +0100 mb/emulation/*-riscv: Don't select ARCH_BOOTBLOCK_RISCV It's already selected by SOC_UCB_RISCV. Change-Id: Ic8a14300cdea2a4ab763b2746434891b72843604 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/18390 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18390 for details. -gerrit

1 0

New patch to review for coreboot: [NOTFORMERGE] agesa-wrapper-killer
by Kyösti Mälkki 23 Feb '17

23 Feb '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18477 -gerrit commit 5650f0af5412f30ea9479a49ef0541436a2dffba Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 23 20:50:53 2017 +0200 [NOTFORMERGE] agesa-wrapper-killer Change-Id: I5fcfed645ccc6f3c78b5050535d97dc95e82ed94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 2 +- src/cpu/amd/agesa/Makefile.inc | 2 +- src/cpu/amd/agesa/amd_late_init.c | 42 --- src/cpu/amd/agesa/cache_as_ram.inc | 92 +++--- src/cpu/amd/agesa/family12/Makefile.inc | 1 + src/cpu/amd/agesa/family12/romstage.c | 43 +++ src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/cpu/amd/agesa/family14/romstage.c | 32 ++ src/cpu/amd/agesa/family15/Makefile.inc | 1 + src/cpu/amd/agesa/family15/fixme.c | 347 ++++++++++---------- src/cpu/amd/agesa/family15/romstage.c | 55 ++++ src/cpu/amd/agesa/family15rl/Makefile.inc | 1 + src/cpu/amd/agesa/family15rl/romstage.c | 28 ++ src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/cpu/amd/agesa/family15tn/romstage.c | 28 ++ src/cpu/amd/agesa/family16kb/Makefile.inc | 1 + src/cpu/amd/agesa/family16kb/romstage.c | 28 ++ src/cpu/amd/agesa/heapmanager.c | 3 + src/cpu/amd/agesa/romstage.c | 113 +++++++ src/cpu/amd/agesa/s3_resume.c | 2 +- src/cpu/amd/agesa/s3_resume.h | 3 + src/include/cpu/amd/car.h | 31 ++ src/mainboard/amd/dinar/romstage.c | 69 +--- src/mainboard/amd/inagua/romstage.c | 64 +--- src/mainboard/amd/olivehill/romstage.c | 79 +---- src/mainboard/amd/parmer/romstage.c | 59 +--- src/mainboard/amd/persimmon/romstage.c | 81 +---- src/mainboard/amd/south_station/romstage.c | 62 +--- src/mainboard/amd/thatcher/romstage.c | 79 +---- src/mainboard/amd/union_station/romstage.c | 64 +--- src/mainboard/asrock/e350m1/romstage.c | 80 +---- src/mainboard/asrock/imb-a180/romstage.c | 85 +---- src/mainboard/asus/f2a85-m/romstage.c | 141 +++------ src/mainboard/bap/ode_e20XX/romstage.c | 80 +---- src/mainboard/biostar/am1ml/romstage.c | 107 ++----- src/mainboard/elmex/pcm205400/romstage.c | 82 +---- src/mainboard/gizmosphere/gizmo/romstage.c | 79 +---- src/mainboard/gizmosphere/gizmo2/romstage.c | 81 +---- src/mainboard/hp/abm/romstage.c | 80 ++--- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 70 +--- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 95 +----- src/mainboard/lenovo/g505s/romstage.c | 69 +--- src/mainboard/lippert/frontrunner-af/romstage.c | 79 +---- src/mainboard/lippert/toucan-af/romstage.c | 78 +---- src/mainboard/msi/ms7721/romstage.c | 123 ++----- src/mainboard/pcengines/apu1/OemCustomize.c | 8 + src/mainboard/pcengines/apu1/OptionsIds.h | 2 +- src/mainboard/pcengines/apu1/romstage.c | 92 +----- src/mainboard/supermicro/h8qgi/romstage.c | 59 +--- src/mainboard/supermicro/h8scm/romstage.c | 75 +---- src/mainboard/tyan/s8226/romstage.c | 57 +--- src/northbridge/amd/agesa/Makefile.inc | 7 +- src/northbridge/amd/agesa/agesawrapper.c | 352 --------------------- src/northbridge/amd/agesa/agesawrapper.h | 27 +- src/northbridge/amd/agesa/eventlog.c | 38 ++- src/northbridge/amd/agesa/family12/northbridge.c | 19 -- src/northbridge/amd/agesa/family12/state_machine.c | 88 ++++++ src/northbridge/amd/agesa/family14/Makefile.inc | 3 + src/northbridge/amd/agesa/family14/northbridge.c | 25 -- src/northbridge/amd/agesa/family14/state_machine.c | 88 ++++++ src/northbridge/amd/agesa/family15/northbridge.c | 16 - src/northbridge/amd/agesa/family15/state_machine.c | 71 +++++ src/northbridge/amd/agesa/family15rl/northbridge.c | 16 - .../amd/agesa/family15rl/state_machine.c | 86 +++++ src/northbridge/amd/agesa/family15tn/northbridge.c | 16 - .../amd/agesa/family15tn/state_machine.c | 85 +++++ src/northbridge/amd/agesa/family16kb/northbridge.c | 16 - .../amd/agesa/family16kb/state_machine.c | 85 +++++ src/northbridge/amd/agesa/oem_s3.c | 2 + src/northbridge/amd/agesa/state_machine.c | 339 ++++++++++++++++++++ src/northbridge/amd/agesa/state_machine.h | 70 ++++ src/vendorcode/amd/agesa/f14/Makefile.inc | 4 +- .../amd/agesa/f14/Proc/CPU/cpuEventLog.c | 14 +- 73 files changed, 1857 insertions(+), 2646 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 74b892e..c0940b9 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1042,7 +1042,7 @@ config ENABLE_APIC_EXT_ID config WARNINGS_ARE_ERRORS bool - default y + default n # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 60bae12..b9dae57 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,10 +24,10 @@ romstage-y += s3_resume.c ramstage-y += s3_mtrr.c cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc +romstage-y += romstage.c romstage-y += heapmanager.c ramstage-y += heapmanager.c -ramstage-y += amd_late_init.c ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c deleted file mode 100644 index a55ebd8..0000000 --- a/src/cpu/amd/agesa/amd_late_init.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <bootstate.h> - -#include <northbridge/amd/agesa/agesawrapper.h> - -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif - -static void agesawrapper_post_device(void *unused) -{ - if (acpi_is_wakeup_s3()) - return; - - agesawrapper_amdinitlate(); - -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif - if (!acpi_s3_resume_allowed()) - return; - - agesawrapper_amdS3Save(); -} - -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL); diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 24db600..f43e6a4 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -26,43 +26,24 @@ #include "gcccar.inc" #include <cpu/x86/cache.h> -/* - * XMM map: - * xmm0: BIST - * xmm1: backup ebx -- cpu_init_detected - */ - .code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out +.globl cache_as_ram_setup, cache_as_ram_setup_out cache_as_ram_setup: - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3<<9), %eax - movl %eax, %cr4 - - /* Get the cpu_init_detected */ - mov $1, %eax - cpuid - shr $24, %ebx - - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - - /* for normal part %ebx already contain cpu_init_detected from fallback call */ + /* Preserve BIST. */ + movl %eax, %ebp - /* Save the cpu_init_detected */ - cvtsi2sd %ebx, %xmm1 + post_code(0xa0) post_code(0xa1) + /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */ AMD_ENABLE_STACK + /* Align the stack to 128 bits. No harm on i386, required on x86_64? */ + and $0xFFFFFFF0, %esp + #ifdef __x86_64__ /* switch to 64 bit long mode */ mov %esi, %ecx @@ -105,42 +86,36 @@ cache_as_ram_setup: # use call far to switch to 64-bit code segment ljmp $0x18, $1f 1: - /* Pass the cpu_init_detected */ - cvtsd2si %xmm1, %esi - /* Pass the BIST result */ - cvtsd2si %xmm0, %edi + .code64 + + /* Calling conventions preserve BIST in %ebp. */ - /* align the stack */ - and $0xFFFFFFF0, %esp + call early_all_cores + + movl %ebp, %edi + call romstage_main + movl %eax, %ebx - .code64 - call cache_as_ram_main .code32 #else - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx + /* Calling conventions preserve BIST in %ebp. */ - /* Restore the cpu_init_detected */ - cvtsd2si %xmm1, %ebx + call early_all_cores + + pushl %ebp + call romstage_main + movl %eax, %ebx - pushl %ebx /* init detected */ - pushl %edx /* bist */ - call cache_as_ram_main #endif - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop +/* Register %ebx is new stacktop for remaining of romstage. + * It is the only register preserved in AMD_DISABLE_STACK. + */ disable_cache_as_ram: - /* Save return stack */ - movd 0(%esp), %xmm1 - movd %esp, %xmm0 - /* Disable cache */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -152,13 +127,20 @@ disable_cache_as_ram: movl %cr0, %eax andl $0x9fffffff, %eax movl %eax, %cr0 - xorl %eax, %eax - /* Restore the return stack */ wbinvd - movd %xmm0, %esp - movd %xmm1, (%esp) - ret + +#ifdef __x86_64__ +.code64 +#endif + + movl %ebx, %esp + call romstage_after_car + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop cache_as_ram_setup_out: #ifdef __x86_64__ diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 578e178..1a7465d 100644 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -28,6 +28,7 @@ #***************************************************************************** romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c new file mode 100644 index 0000000..d789d77 --- /dev/null +++ b/src/cpu/amd/agesa/family12/romstage.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/agesawrapper.h> + +#include "sb_cimx.h" +#include "SbPlatform.h" +#include "platform_cfg.h" + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +int platform_once(struct romstage_params *params) +{ + gpioEarlyInit(); + + sb_poweron_init(); + + return mainboard_pre_agesa(); +} + +#if 0 + /* between INIT_POST and INIT_ENV */ + printk(BIOS_DEBUG, "sb_before_pci_init "); + sb_before_pci_init(); + printk(BIOS_DEBUG, "passed.\n"); +#endif diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 9b4e76b..3da8dd5 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c new file mode 100644 index 0000000..dbc8c7f --- /dev/null +++ b/src/cpu/amd/agesa/family14/romstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/agesawrapper.h> +#include <sb_cimx.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +int platform_once(struct romstage_params *params) +{ + sb_Poweron_Init(); + + return mainboard_pre_agesa(params); +} + diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc index 5742e7a..d01cb2a 100644 --- a/src/cpu/amd/agesa/family15/Makefile.inc +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -22,6 +22,7 @@ subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15/fixme.c b/src/cpu/amd/agesa/family15/fixme.c index 7b8598d..158dd4e 100644 --- a/src/cpu/amd/agesa/family15/fixme.c +++ b/src/cpu/amd/agesa/family15/fixme.c @@ -49,213 +49,204 @@ MsrWrite ( #if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR) void amd_initcpuio(void) { - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - UINT32 nodes; - UINT32 node; - UINT32 sblink; - UINT32 i; - UINT32 TOM; + return __readmsr (MsrAddress); +} - /* get the number of coherent nodes in the system */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0] +VOID +MsrWrite ( + IN UINT32 MsrAddress, + IN UINT64 Value + ) +{ + __writemsr (MsrAddress, Value); +} - /* Find out the Link ID of Node0 that connects to the - * Southbridge (system IO hub). e.g. family10 MCM Processor, - * sbLink is Processor0 Link2, internal Node0 Link3 - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - sblink = (PciData >> 8) & 3; //assume ganged +#define MMIO_NP_BIT BIT7 - /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ - for (node = 0; node < nodes; node++) { - /* clear all MMIO Mapped Base/Limit Registers */ - for (i = 0; i < 8; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* clear all IO Space Base/Limit Registers */ - for (i = 0; i < 4; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); - PciData = 0x00000B00; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); - PciData = 0x00000A03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +static void unmap_all_cpuio(uint8_t node_dev) +{ + UINT32 PciData; + PCI_ADDR PciAddress; + int i; - /* Set TOM1-FFFFFFFF to Node0 sbLink. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); - PciData = 0x00FFFF00; - PciData |= sblink << 4; + /* clear all MMIO Mapped Base/Limit Registers */ + for (i = 0; i < 8; i++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - TOM = (UINT32)MsrRead(TOP_MEM); - PciData = (TOM >> 8) | 0x03; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set MMCONF space to Node0 sbLink with NP set. - * default E0000000-EFFFFFFF - * Just have all mmio set to non-posted, - * coreboot not implemente the range by range setting yet. - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC); - PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus - PciData = (PciData >> 8) & 0xFFFFFF00; - PciData |= 0x80; //NP - PciData |= sblink << 4; + } + /* clear all IO Space Base/Limit Registers */ + for (i = 0; i < 4; i++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8); - PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } +} +static void map_pci_mmconf(uint8_t node_dev, uint8_t mmio_idx, uint8_t sblink) +{ + /* Set MMCONF space to Node0 sblink with NP set. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x94); + PciData = (CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8; + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x00FFF000; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x00000033; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x90); + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} + +static void map_vga_mmio(uint8_t node_dev, uint8_t mmio_idx, uint8_t sblink) +{ + /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sblink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x84 + 8 * mmio_idx); + PciData = 0xB0000 >> 8; + PciData &= (~0xFF); + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x80 + 8 * mmio_idx); + PciData = (0xA0000 >> 8) | 3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } + +#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR) +static void map_top_mmio(uint8_t node_dev, uint8_t mmio_idx, uint8_t sblink) +{ + UINT32 TOM = (UINT32) MsrRead(TOP_MEM); + + /* Set TOM1-FFFFFFFF to Node0 sblink. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x8C); + PciData = 0x00FFFF00; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x88); + PciData = (TOM >> 8) | 0x03; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} + #else +static void map_uma_mmio(uint8_t node_dev, uint8_t mmio_idx, uint8_t sblink) +{ + UINT64 MsrReg; + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + + UINT32 TopMem = (UINT32) MsrReg; + + /* Set UMA MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x8c); + if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) { + PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; + } else { + PciData = (0x100000000ull - 1) >> 8; + } + PciData &= (~0xFF); + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x88); + PciData = (UINT32) (MsrReg >> 8) | 0x03; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} + +static void map_apic_mmio(uint8_t node_dev, uint8_t mmio_idx, uint8_t sblink) +{ + /* Set XAPIC MMIO. 24K */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x9c); + PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8); + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); -#define MMIO_NP_BIT BIT7 + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0x98); + PciData = (0xFEC00000 >> 8) | 3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} + +static void map_lapic_mmio(uint8_t node_dev, uint8_t mmio_idx, uint8_t sblink) +{ + /* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0xA8); + PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8; + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0xA0); + PciData = (0xFEE00000 >> 8) | 3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} +#endif + +static void map_legacy_io(uint8_t node_dev, uint8_t io_idx, uint8_t sblink) +{ + /* Set PCIO: 0x0 - 0xFFF000 to Node0 sblink and enabled VGA IO*/ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0xC4 + 8 * io_idx); + PciData = 0x00FFF000; + PciData &= (~0x7F); + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + PciAddress.AddressValue = MAKE_SBDFO(0, 0, node_dev, FUNC_1, 0xC0 + 8 * io_idx); +#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR) + PciData = 0x30; +#else + PciData = 0x10; +#endif + PciData |= 0x03; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} void amd_initcpuio(void) { - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - UINT32 TopMem; - UINT32 nodes; - UINT32 node; - UINT32 SbLink; - UINT32 i; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + uint8_t node, nodes, sblink; - /* get the number of coherent nodes in the system */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - nodes = ((PciData >> 4) & 7) + 1; //nodes[6:4] /* Find out the Link ID of Node0 that connects to the * Southbridge (system IO hub). e.g. family10 MCM Processor, - * SbLink is Processor0 Link2, internal Node0 Link3 + * sbLink is Processor0 Link2, internal Node0 Link3 */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - SbLink = (PciData >> 8) & 3; //assume ganged + sblink = (PciData >> 8) & 3; //assume ganged + + /* get the number of coherent nodes in the system */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0] + /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ for (node = 0; node < nodes; node++) { - /* clear all MMIO Mapped Base/Limit Registers */ - for (i = 0; i < 8; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - /* clear all IO Space Base/Limit Registers */ - for (i = 0; i < 4; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* Enable MMIO on AMD CPU Address Map Controller */ - - /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); - PciData = (0xA0000 >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); - PciData = 0xB0000 >> 8; - PciData &= (~0xFF); - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set UMA MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); - LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); - TopMem = (UINT32) MsrReg; - MsrReg = (MsrReg >> 8) | 3; - PciData = (UINT32) MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8c); - if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) { - PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; - } else { - PciData = (0x100000000ull - 1) >> 8; - } - PciData &= (~0xFF); - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + uint8_t mmio_idx = 0, io_idx = 0; - /* Set PCIE MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x90); - PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x94); - PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) & (~0xFF); - PciData &= (~0xFF); - PciData |= MMIO_NP_BIT; - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + clear_mmio_maps(CONFIG_CDB + node); - /* Set XAPIC MMIO. 24K */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x98); - PciData = (0xFEC00000 >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x9c); - PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8); - PciData &= (~0xFF); - PciData |= MMIO_NP_BIT; - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + map_pci_mmconf(CONFIG_CDB + node, mmio_idx++, sblink); - /* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA0); - PciData = (0xFEE00000 >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA8); - PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8; - PciData &= (~0xFF); - PciData |= MMIO_NP_BIT; - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + map_vga_mmio(CONFIG_CDB + node, mmio_idx++, sblink); - /* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x13; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x00FFF000; - PciData &= (~0x7F); - PciData |= SbLink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR) + map_top_mmio(CONFIG_CDB + node, mmio_idx++, sblink); +#else + map_uma_mmio(CONFIG_CDB + node, mmio_idx++, sblink); + map_apic_mmio(CONFIG_CDB + node, mmio_idx++, sblink); + map_lapic_mmio_mmio(CONFIG_CDB + node, mmio_idx++, sblink); +#endif + map_legacy_io(CONFIG_CDB + node, io_idx++, sblink); } + } -#endif void amd_initmmio(void) { diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c new file mode 100644 index 0000000..a7a4c2a --- /dev/null +++ b/src/cpu/amd/agesa/family15/romstage.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/agesawrapper.h> + +#include "northbridge/amd/agesa/family10/reset_test.h" +#include <nb_cimx.h> +#include <sb_cimx.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +int platform_once(struct romstage_params *params) +{ + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + + nb_Poweron_Init(); + + sb_Poweron_Init(); + + return mainboard_pre_agesa(params); +} + +#if 0 + /* after AMD_INIT_EARLY, before AMD_INIT_POST */ + nb_Ht_Init(); + + /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); + distinguish_cpu_resets(0); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } +#endif diff --git a/src/cpu/amd/agesa/family15rl/Makefile.inc b/src/cpu/amd/agesa/family15rl/Makefile.inc index 98a7050..d4695b0 100644 --- a/src/cpu/amd/agesa/family15rl/Makefile.inc +++ b/src/cpu/amd/agesa/family15rl/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15rl/romstage.c b/src/cpu/amd/agesa/family15rl/romstage.c new file mode 100644 index 0000000..5735383 --- /dev/null +++ b/src/cpu/amd/agesa/family15rl/romstage.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/agesawrapper.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +int platform_once(struct romstage_params *params) +{ + return mainboard_pre_agesa(params); +} diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 98a7050..d4695b0 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c new file mode 100644 index 0000000..5735383 --- /dev/null +++ b/src/cpu/amd/agesa/family15tn/romstage.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/agesawrapper.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +int platform_once(struct romstage_params *params) +{ + return mainboard_pre_agesa(params); +} diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 9367b45..5c2ba8f 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c new file mode 100644 index 0000000..5735383 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/romstage.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/car.h> + +#include <northbridge/amd/agesa/agesawrapper.h> + +void asmlinkage early_all_cores(void) +{ + amd_initmmio(); +} + +int platform_once(struct romstage_params *params) +{ + return mainboard_pre_agesa(params); +} diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index 087959d..0665191 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -57,6 +57,9 @@ void EmptyHeap(void) { void *base = GetHeapBase(); memset(base, 0, BIOS_HEAP_SIZE); + + printk(BIOS_DEBUG, "Wiped HEAP at [%08x - %08x]\n", + (uint32_t)(uintptr_t) base, (uint32_t)(uintptr_t) base + BIOS_HEAP_SIZE - 1); } void ResumeHeap(void **heap, size_t *len) diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c new file mode 100644 index 0000000..af62f5f --- /dev/null +++ b/src/cpu/amd/agesa/romstage.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include <cpu/amd/car.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/mtrr.h> +#include <console/console.h> +#include <halt.h> +#include <program_loading.h> +#include <smp/node.h> +#include <string.h> + +#include <Porting.h> +#include <AMD.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> + +static void init(struct agesa_state *params, + struct romstage_params *romstage, AMD_INTERFACE_PARAMS *aip) +{ + memset(romstage, 0, sizeof(*romstage)); + + memset(aip, 0, sizeof(*aip)); + aip->StdHeader.CalloutPtr = GetBiosCallout; + + memset(params, 0, sizeof(*params)); + params->s3resume = acpi_is_wakeup_s3(); + params->amd_interface_params = aip; + params->romstage = romstage; + params->apic_id = (u8) (cpuid_ebx(1) >> 24); +} + + +void * asmlinkage romstage_main(unsigned long bist) +{ + AMD_INTERFACE_PARAMS aip; + struct romstage_params romstage; + struct agesa_state params; + + init(&params, &romstage, &aip); + + if ((params.apic_id == 0) && boot_cpu()) { + + platform_once(&romstage); + + console_init(); + } + + printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", + params.apic_id, cpuid_eax(1)); + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + agesa_execute_state(&params, AMD_INIT_RESET); + + agesa_execute_state(&params, AMD_INIT_EARLY); + + if (!params.s3resume) + agesa_execute_state(&params, AMD_INIT_POST); + else + agesa_execute_state(&params, AMD_INIT_RESUME); + + + uintptr_t stack_top = CACHE_TMP_RAMTOP; + if (params.s3resume) { + if (!cbmem_recovery(1)) { + printk(BIOS_EMERG, "Unable to recover CBMEM\n"); + halt(); + } + stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, + ROMSTAGE_STACK_CBMEM); + stack_top += HIGH_ROMSTAGE_STACK_SIZE; + } + + printk(BIOS_DEBUG, "Move CAR stack.\n"); + return (void*)stack_top; +} + +void asmlinkage romstage_after_car(void) +{ + struct romstage_params romstage; + AMD_INTERFACE_PARAMS aip; + struct agesa_state params; + + printk(BIOS_DEBUG, "CAR disabled.\n"); + + init(&params, &romstage, &aip); + + if (!params.s3resume) + agesa_execute_state(&params, AMD_INIT_ENV); + else + agesa_execute_state(&params, AMD_S3LATE_RESTORE); + + if (params.s3resume) + set_resume_cache(); + + run_ramstage(); +} diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 1e4aadb..ce4e247 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -50,7 +50,7 @@ static void move_stack_high_mem(void) #endif } -static void set_resume_cache(void) +void set_resume_cache(void) { msr_t msr; diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index ff23966..0c7775e 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -19,6 +19,9 @@ void restore_mtrr(void); void prepare_for_resume(void); +/* temp hack to build */ +void set_resume_cache(void); + void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); const void *OemS3Saved_MTRR_Storage(void); diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 6950a38..88b1342 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -1,6 +1,9 @@ #ifndef _CPU_AMD_CAR_H #define _CPU_AMD_CAR_H +#include <arch/cpu.h> + +#if 0 void main(unsigned long bist); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); @@ -13,5 +16,33 @@ void cache_as_ram_new_stack(void); #if CONFIG_CPU_AMD_AGESA || CONFIG_CPU_AMD_PI void disable_cache_as_ram(void); #endif +#endif + +struct romstage_params +{ + u8 dummy; +}; + +struct agesa_state +{ + u8 apic_id; + u32 func; + const char *function_name; + u32 status; //AGESA_STATUS + + struct romstage_params *romstage; + void *ramstage; + void *amd_interface_params; + + u8 s3resume; +}; + +void asmlinkage early_all_cores(void); +int mainboard_pre_agesa(struct romstage_params *params); +void * asmlinkage romstage_main(unsigned long bist); +void asmlinkage romstage_after_car(void); + +int platform_once(struct romstage_params *params); +int agesa_execute_state(struct agesa_state *params, int func); #endif diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 0edc346..96f5bc4 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -26,33 +26,23 @@ #include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> +#include "cpu/x86/bist.h" #include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sio1036/sio1036.h> -#include <cpu/x86/lapic.h> +#include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_romstage_entry(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + sch4037_early_init(0x2e); + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { - - post_code(0x30); - - sch4037_early_init(0x2e); - - sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - post_code(0x31); - console_init(); - /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. @@ -60,47 +50,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sr56x0_rd890_disable_pcie_bridge(); } - - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - - // Load MPB - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - if(boot_cpu()) { - post_code(0x34); - sb_Poweron_Init(); - } - - post_code(0x35); - agesawrapper_amdinitreset(); - - post_code(0x36); - agesawrapper_amdinitearly(); - - post_code(0x37); - nb_Poweron_Init(); - post_code(0x38); - nb_Ht_Init(); - - - post_code(0x39); - agesawrapper_amdinitpost(); - - post_code(0x40); - agesawrapper_amdinitenv(); - - - post_code(0x43); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x44); - copy_and_run(); - - post_code(0x45); // Should never see this post code. -} +#endif diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3d0eecf..1c19ce7 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -13,71 +13,13 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/smsc/kbc1100/kbc1100.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - kbc1100_early_init(0x2e); - kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + kbc1100_early_init(0x2e); + kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index bb1ad30..65feaab 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -17,29 +17,22 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +int mainboard_pre_agesa(struct romstage_params *params) { - u32 val; + /* For serial port option, plug-in card on LPC. */ + device_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + hudson_lpc_port80(); /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA @@ -49,67 +42,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); +} - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); +#if 0 + /* LPC clock? Should happen before enable_serial. */ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); +#endif - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 1f251ab..137283f 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -33,63 +33,12 @@ #include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - post_code(0x54); /* Should never see this post code. */ + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); } diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index c8a8d74..5e7d0dd 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -13,90 +13,13 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 95f6dde..5e7d0dd 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -13,71 +13,13 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 147f31a..9b3889b 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -22,88 +22,43 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> + +#include <cpu/amd/car.h> #include <superio/smsc/lpc47n217/lpc47n217.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); + byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); - *(u8 *)0xfed80101 = 0x98; - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } + post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); - post_code(0x50); - copy_and_run(); + post_code(0x31); + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - post_code(0x54); /* Should never see this post code. */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + outb(0xea, 0xcd6); + outb(0x1, 0xcd7); + *(u8 *)0xfed80101 = 0x98; } diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 7a5d348..500aeeb 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -13,68 +13,6 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" - -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 82fbecf..547eae6 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -13,87 +13,15 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ +int mainboard_pre_agesa(struct romstage_params *params) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + return 0; } diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 29d831d..c357116 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -21,44 +21,25 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" + +#include <cpu/amd/car.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627uhg/w83627uhg.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +int mainboard_pre_agesa(struct romstage_params *params) { - u32 val, t32; - u32 *addr32; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - //outb(0xD2, 0xcd6); - //outb(0x00, 0xcd7); - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); @@ -76,64 +57,28 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffbffb; *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - post_code(0x31); - - /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + device_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); - console_init(); - } + /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + return 0; +} - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); +#if 0 + /* LPC clock? Should happen before enable_serial. */ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); +#endif - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); +#endif - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 51cadc7..bd8c0d8 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -14,29 +14,19 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/pnp_def.h> -#include <southbridge/amd/common/amd_defs.h> +#include <stdint.h> + +#include <northbridge/amd/agesa/agesawrapper.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/smbus.h> -#include <stdint.h> -#include <string.h> + #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> + #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) @@ -58,15 +48,12 @@ static void sbxxx_enable_48mhzout(void) SB_MMIO_MISC32(0x40) = reg32; } -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + +int mainboard_pre_agesa(struct romstage_params *params) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif @@ -74,81 +61,41 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - if (!cpu_init_detectedx && boot_cpu()) { - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - post_code(0x30); - - /* enable SB MMIO space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - ite_enable_3vsbsw(GPIO_DEV); - console_init(); - - /* turn on secondary smbus at b20 */ - outb(0x28, 0xcd6); - byte = inb(0xcd7); - byte |= 1; - outb(byte, 0xcd7); - - /* set DDR3 voltage */ - byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; - - /* default is byte = 0x0, so no need to set it in this case */ - if (byte) - do_smbus_write_byte(0xb20, 0x15, 0x3, byte); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(GPIO_DEV); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; + + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); + + return 0; } diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index a43d035..3cd0743 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -15,36 +15,21 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> + +#include <cpu/amd/car.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> -#include "cbmem.h" + #define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); +} - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); +#if 0 /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -52,62 +37,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 1672349..b6ac771 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -14,26 +14,15 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> + #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" + +#include <cpu/amd/car.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> @@ -105,17 +94,18 @@ static void ite_gpio_conf(pnp_devfn_t dev) ite_exit_conf (dev); } - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if 0 u32 val, t32; u8 byte; pci_devfn_t dev; u32 *addr32; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -146,83 +136,36 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffbffb; *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - post_code(0x30); - post_code(0x31); - - /* run ite */ - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - printk(BIOS_DEBUG, "Console inited!\n"); - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + +#endif + +#if 0 /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); + /* This functions configure SIO as it been done under vendor bios */ printk(BIOS_DEBUG, "ITE CONFIG ENVC\n"); ite_evc_conf(ENVC_DEV); printk(BIOS_DEBUG, "ITE CONFIG GPIO\n"); ite_gpio_conf(GPIO_DEV); printk(BIOS_DEBUG, "ITE CONFIG DONE\n"); - - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index c8a8d74..2a7defb 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -13,90 +13,14 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +int mainboard_pre_agesa(struct romstage_params *params) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + return 0; } diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 6d06621..300b0fdf 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -14,84 +14,9 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +int mainboard_pre_agesa(struct romstage_params *params) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + return 0; } diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index bb1ad30..d2f06be 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -17,29 +17,22 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> +#include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; + /* For serial port option, plug-in card on LPC. */ + device_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); + hudson_lpc_port80(); /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA @@ -49,67 +42,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); +} - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); +#if 0 + /* LPC clock? Should happen before enable_serial. */ /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); +#endif - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 02ebbc9..f7d7ddb 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -25,7 +25,7 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <commonlib/loglevel.h> +#include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/x86/bist.h> @@ -33,26 +33,30 @@ #include <southbridge/amd/agesa/hudson/hudson.h> #include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> + +#include <cpu/amd/car.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val, t32; - u32 *addr32; - - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* Set LPC decode enables. */ + /* For serial port option, plug-in card on LPC. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA + * even though the register is not documented in the Kabini BKDG. + * Otherwise the serial output is bad code. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x01, 0xcd7); @@ -71,58 +75,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffff7b; // clear 2, 7 *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - post_code(0x31); - - nct5104d_enable_uartd(SERIAL_DEV); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); + nct5104d_enable_uartd(SERIAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); +} - post_code(0x61); - prepare_for_resume(); - } +#if 0 + /* Was before copy_and_run. */ outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 714743b..7a48820 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -13,76 +13,10 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> #include <southbridge/amd/agesa/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); +void mainboard_pre_agesa(void) +{ hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ } diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 85a4343..efee036 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -14,105 +14,14 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> - -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> - -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> -#include <sb_cimx.h> -#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) -/* - * Possible AGESA_STATUS values: - * - * 0x0 = AGESA_SUCCESS - * 0x1 = AGESA_UNSUPPORTED - * 0x2 = AGESA_BOUNDS_CHK - * 0x3 = AGESA_ALERT - * 0x4 = AGESA_WARNING - * 0x5 = AGESA_ERROR - * 0x6 = AGESA_CRITICAL - * 0x7 = AGESA_FATAL - */ - - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 714743b..11a1eff 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -13,76 +13,11 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> #include <southbridge/amd/agesa/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +int mainboard_pre_agesa(struct romstage_params *params) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + return 0; } diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 37dc37f..bf8335d 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -13,67 +13,17 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { +#if 0 post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ @@ -83,23 +33,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x42); agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index adc2987..e81d32d 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -13,68 +13,19 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_pre_agesa(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { +#if 0 post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ @@ -84,23 +35,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x42); agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ -} +#endif diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 9ce47f2..5ffbe58 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -15,30 +15,19 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> #include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> #include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/car.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/pnp_def.h> +#include <device/pnp.h> +#include <stdint.h> + +#include <northbridge/amd/agesa/agesawrapper.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <southbridge/amd/agesa/hudson/smbus.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> -#include <stdint.h> -#include <string.h> #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff @@ -122,15 +111,12 @@ static void sbxxx_enable_48mhzout(void) SB_MMIO_MISC32(0x40) = reg32; } -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + +int mainboard_pre_agesa(struct romstage_params *params) { - u32 val; u8 byte; pci_devfn_t dev; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif @@ -138,75 +124,30 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - if (!cpu_init_detectedx && boot_cpu()) { - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - post_code(0x30); - - /* enable SB MMIO space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - /* Initialize GPIO registers */ - gpio_init(GPIO_DEV); - - /* Enable serial console */ - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - /* turn on secondary smbus at b20 */ - outb(0x28, 0xcd6); - byte = inb(0xcd7); - byte |= 1; - outb(byte, 0xcd7); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); - agesawrapper_amdinitresume(); - amd_initcpuio(); - agesawrapper_amds3laterestore(); - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + /* Initialize GPIO registers */ + gpio_init(GPIO_DEV); + + /* Enable serial console */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + return 0; } diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index 20acb27..fd5aa38 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -158,3 +158,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { const struct OEM_HOOK OemCustomize = { .InitEarly = OemInitEarly, }; + +void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *p) +{ + OemInitEarly(p); +} + +void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *p) { } +void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *p) { } diff --git a/src/mainboard/pcengines/apu1/OptionsIds.h b/src/mainboard/pcengines/apu1/OptionsIds.h index 2d8381b..859fe5c 100644 --- a/src/mainboard/pcengines/apu1/OptionsIds.h +++ b/src/mainboard/pcengines/apu1/OptionsIds.h @@ -43,7 +43,7 @@ **/ #define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#define IDSOPT_DEBUG_ENABLED FALSE diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index a74d247..3eed8ad 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -15,99 +15,16 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> #include <southbridge/amd/cimx/cimx_util.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" +#include "SB800.h" #define SIO_PORT 0x2e #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -static void early_lpc_init(void); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - early_lpc_init(); - - - post_code(0x31); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ -} - static void early_lpc_init(void) { u32 mmio_base; @@ -140,3 +57,10 @@ static void early_lpc_init(void) configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); } + +int mainboard_pre_agesa(struct romstage_params *params) +{ + early_lpc_init(); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + return 0; +} diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 19ffbdf..ffa4045 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -20,11 +20,11 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/family10/reset_test.h> +#include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> @@ -36,34 +36,15 @@ */ #define SIO_PORT 0x164e -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_romstage_entry(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x31); - - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); - post_code(0x34); - post_code(0x35); - console_init(); - - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* @@ -76,16 +57,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); sb_Poweron_Init(); } - post_code(0x3B); - agesawrapper_amdinitearly(); +#endif - post_code(0x3C); +#if 0 /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); +#endif +#if 0 nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ @@ -95,23 +77,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - post_code(0x42); - - post_code(0x50); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x51); - copy_and_run(); - - /* We will not return, Should never see this message and post code. */ - printk(BIOS_DEBUG, "should not be here -\n"); - post_code(0x54); -} +#endif diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 918d9ad..6619b2e 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -20,49 +20,31 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/family10/reset_test.h> +#include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> +/* though UARTs are on the NUVOTON BMC, port 0x164E + * PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E + */ +#define SIO_PORT 0x164e -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define DUMMY_DEV PNP_DEV(0x2e, 0) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_romstage_entry(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x31); - - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ - wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE); + wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); - post_code(0x34); - - post_code(0x35); - console_init(); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* @@ -75,37 +57,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); sb_Poweron_Init(); } - post_code(0x3B); - agesawrapper_amdinitearly(); - - post_code(0x3C); - nb_Ht_Init(); - - post_code(0x3D); - /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ - if (!warm_reset_detect(0)) { - printk(BIOS_INFO, "...WARM RESET...\n\n\n"); - distinguish_cpu_resets(0); - soft_reset(); - die("After soft_reset_x - shouldn't see this message!!!\n"); - } - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - post_code(0x42); - - post_code(0x50); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x51); - copy_and_run(); - - /* We will not return, Should never see this message and post code. */ - printk(BIOS_DEBUG, "should not be here -\n"); - post_code(0x54); -} +#endif diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index d43c04b..0657cf6 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -20,11 +20,11 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/family10/reset_test.h> +#include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/winbond/common/winbond.h> @@ -34,39 +34,21 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void mainboard_romstage_entry(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - post_code(0x31); - /* For serial port. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - /* Halt if there was a built in self test failure */ - post_code(0x33); - report_bist_failure(bist); - sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ w83627dhg_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); - post_code(0x34); - - post_code(0x35); - console_init(); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); - agesawrapper_amdinitreset(); +} +#if 0 if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* @@ -79,16 +61,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); sb_Poweron_Init(); } - post_code(0x3B); - agesawrapper_amdinitearly(); +#endif - post_code(0x3C); +#if 0 /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); +#endif +#if 0 nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ @@ -99,22 +82,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) die("After soft_reset_x - shouldn't see this message!!!\n"); } - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - post_code(0x42); - - post_code(0x50); - printk(BIOS_DEBUG, "Disabling cache as RAM "); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "done\n"); - - post_code(0x51); - copy_and_run(); - - /* We will not return, Should never see this message and post code. */ - printk(BIOS_DEBUG, "should not be here -\n"); - post_code(0x54); -} +#endif diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 62a5df1..1d153ac 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -23,8 +23,11 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) += family15rl subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-y += def_callouts.c agesawrapper.c eventlog.c -ramstage-y += def_callouts.c agesawrapper.c eventlog.c +romstage-y += def_callouts.c eventlog.c +ramstage-y += def_callouts.c eventlog.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c romstage-y += oem_s3.c ramstage-y += oem_s3.c diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c deleted file mode 100644 index a72e239..0000000 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> - -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> - -#include "heapManager.h" - -static const struct OEM_HOOK *OemHook = &OemCustomize; - -#if defined(__PRE_RAM__) - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook. */ - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; - if (OemHook->InitEarly) - OemHook->InitEarly(AmdEarlyParamsPtr); - - status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook. */ - PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; - if (OemHook->InitPost) - OemHook->InitPost(PostParams); - - status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, &PostParams->StdHeader); - - AmdReleaseStruct(&AmdParamStruct); - - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemInitResume(AmdResumeParamsPtr); - - status = AmdInitResume(AmdResumeParamsPtr); - - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; - - status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, &EnvParam->StdHeader); - - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - - memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - -#if 0 - /* TODO: What to do with NvStorage here? */ - AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0; -#endif - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemS3LateRestore(AmdS3LateParamsPtr); - - status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - return status; -} - -#else /* __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_MID_PARAMS *MidParam; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook. */ - MidParam = (AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr; - if (OemHook->InitMid) - OemHook->InitMid(MidParam); - - status = AmdInitMid(MidParam); - AGESA_EVENTLOG(status, &MidParam->StdHeader); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - - memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - OemS3Save(AmdS3SaveParamsPtr); - - AmdReleaseStruct(&AmdInterfaceParams); - - return status; -} - -/* We will reference AmdLateParams later to copy ACPI tables. */ -static AMD_LATE_PARAMS *AmdLateParams = NULL; - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) || \ - IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; -#endif - - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); - ASSERT(status == AGESA_SUCCESS); - - /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */ - return status; -} - -void *agesawrapper_getlateinitptr(int pick) -{ - ASSERT(AmdLateParams != NULL); - - switch (pick) { - case PICK_DMI: - return AmdLateParams->DmiTable; - case PICK_PSTATE: - return AmdLateParams->AcpiPState; - case PICK_SRAT: - return AmdLateParams->AcpiSrat; - case PICK_SLIT: - return AmdLateParams->AcpiSlit; - case PICK_WHEA_MCE: - return AmdLateParams->AcpiWheaMce; - case PICK_WHEA_CMC: - return AmdLateParams->AcpiWheaCmc; - case PICK_ALIB: - return AmdLateParams->AcpiAlib; - case PICK_IVRS: -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14) - return NULL; -#else - return AmdLateParams->AcpiIvrs; -#endif - default: - return NULL; - } - return NULL; -} - -#endif /* __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) -{ - AGESA_STATUS status; - AP_EXE_PARAMS ApExeParams; - - memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - status = AmdLateRunApTask(&ApExeParams); - AGESA_EVENTLOG(status, &ApExeParams.StdHeader); - ASSERT(status == AGESA_SUCCESS); - - return status; -} diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index f5d52d6..6d1d775 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -38,6 +38,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void); AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitmid(void); +const char *agesa_struct_name(int state); +const char *heap_status_name(int status); void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); #define AGESA_EVENTLOG(status, stdheader) \ agesawrapper_trace(status, stdheader, __func__) @@ -68,8 +70,27 @@ struct OEM_HOOK extern const struct OEM_HOOK OemCustomize; /* For suspend-to-ram support. */ -AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); -AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); -AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); +AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *Resume); +AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3Late); +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3Save); + +struct romstage_params; +void board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early); +void board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post); +void board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid); + +void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset); +void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early); +void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post); +void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post); +void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env); +void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env); +void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid); +void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late); + +void platform_BeforeInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume); +void platform_BeforeS3LateRestore(struct romstage_params *cb, AMD_S3LATE_PARAMS *S3Late); +void platform_AfterS3LateRestore(struct romstage_params *cb, AMD_S3LATE_PARAMS *S3Late); +void platform_AfterS3Save(struct romstage_params *cb, AMD_S3SAVE_PARAMS *S3Save); #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c index 0a40672..a951d72 100644 --- a/src/northbridge/amd/agesa/eventlog.c +++ b/src/northbridge/amd/agesa/eventlog.c @@ -21,6 +21,40 @@ #include "AGESA.h" #include "AMD.h" +#include <heapManager.h> + +static const char undefined[] = "undefined"; + +/* Match order of enum AGESA_STRUCT_NAME. */ +static const char *AgesaFunctionNameStr[] = { + "AmdInitRecovery", "AmdCreateStruct", "AmdInitEarly", "AmdInitEnv", "AmdInitLate", + "AmdInitMid", "AmdInitPost", "AmdInitReset", "AmdInitResume", "AmdReleaseStruct", + "AmdS3LateRestore","AmdS3Save", "AmdGetApicId", "AmdGetPciAddress", "AmdIdentifyCore", + "AmdReadEventLog", "AmdGetAvailableExeCacheSize", "AmdLateRunApTask", "AmdIdentifyDimm", +}; + +/* heapManager.h */ +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +const char *agesa_struct_name(int state) +{ + if ((state < AMD_INIT_RECOVERY) || (state > AMD_IDENTIFY_DIMMS)) + return undefined; + + int index = state - AMD_INIT_RECOVERY; + return AgesaFunctionNameStr[index]; +} + +const char *heap_status_name(int status) +{ + if ((status < HEAP_DO_NOT_EXIST_YET) || (status > HEAP_S3_RESUME)) + return undefined; + + int index = status - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} /* * Possible AGESA_STATUS values: @@ -45,8 +79,6 @@ static const char * decodeAGESA_STATUS(AGESA_STATUS sret) return statusStrings[sret]; } -#if 0 - /** * */ @@ -703,7 +735,6 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event) break; } } -#endif static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader) { @@ -728,6 +759,7 @@ static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader) printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + interpret_agesa_eventlog(&AmdEventParams); AmdReadEventLog(&AmdEventParams); } } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index c8198c9..4cffd61 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -632,24 +632,6 @@ static void domain_set_resources(device_t dev) } -static void domain_enable_resources(device_t dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - /* Must be called after PCI enumeration and resource allocation */ -#if CONFIG_AMD_SB_CIMX - sb_After_Pci_Init(); - sb_Mid_Post_Init(); -#endif - - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - - /* Bus related code */ static void cpu_bus_init(device_t dev) @@ -790,7 +772,6 @@ struct chip_operations northbridge_amd_agesa_family12_ops = { static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, }; diff --git a/src/northbridge/amd/agesa/family12/state_machine.c b/src/northbridge/amd/agesa/family12/state_machine.c new file mode 100644 index 0000000..a5aa898 --- /dev/null +++ b/src/northbridge/amd/agesa/family12/state_machine.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/agesawrapper.h> + +#include <cpu/amd/agesa/s3_resume.h> + +#include <sb_cimx.h> + +void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ + /* We use AMD_S3LATE_RESTORE instead. */ + Post->MemConfig.SaveMemContextCtl = 0; + Post->MemConfig.MemRestoreCtl = 0; +} + +void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct romstage_params *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(S3Late); +} + +void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid) +{ + if (!acpi_is_wakeup_s3()) { + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + } else { + sb_After_Pci_Restore_Init(); + } + + if (!acpi_is_wakeup_s3()) { + + amd_initcpuio(); + + agesawrapper_amdinitmid(); + } +} + +void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late) +{ + sb_Late_Post(); +} + +void platform_AfterS3Save(struct romstage_params *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index 6b2ca78..ad39325 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b8d9c6f..bc517bd 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -614,30 +614,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) -{ -#if CONFIG_AMD_SB_CIMX - if (!acpi_is_wakeup_s3()) { - sb_After_Pci_Init(); - sb_Mid_Post_Init(); - } else { - sb_After_Pci_Restore_Init(); - } -#endif - - /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); -} - static const char *domain_acpi_name(struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -818,7 +794,6 @@ struct chip_operations northbridge_amd_agesa_family14_ops = { static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c new file mode 100644 index 0000000..9f9d225 --- /dev/null +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/agesawrapper.h> + +#include <cpu/amd/agesa/s3_resume.h> + +#include <sb_cimx.h> + +void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + + +void platform_BeforeInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + + +void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ + amd_initenv(); +} + +void platform_BeforeS3LateRestore(struct romstage_params *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(S3Late); +} + +void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid) +{ + if (!acpi_is_wakeup_s3()) { + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + } else { + sb_After_Pci_Restore_Init(); + } + + if (!acpi_is_wakeup_s3()) { + + amd_initcpuio(); + + // agesawrapper_amdinitmid(); + } +} + +void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late) +{ + sb_Late_Post(); +} + +void platform_AfterS3Save(struct romstage_params *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 9cfaed9..20cf7f9 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -632,21 +632,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) -{ - /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); - -#if CONFIG_AMD_SB_CIMX - sb_After_Pci_Init(); -#endif - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -849,7 +834,6 @@ static void f15_pci_domain_scan_bus(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = f15_pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family15/state_machine.c b/src/northbridge/amd/agesa/family15/state_machine.c new file mode 100644 index 0000000..21af008 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/state_machine.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void fam_init_reset(struct romstage_params *param, AMD_RESET_PARAMS *ResetParams) +{ +} + +void fam_init_post_pre(struct romstage_params *param, AMD_POST_PARAMS *PostParams) +{ + /* We use AMD_S3LATE_RESTORE instead. */ + PostParams->MemConfig.SaveMemContextCtl = 0; + PostParams->MemConfig.MemRestoreCtl = 0; +} + +void fam_init_post_post(struct romstage_params *param, AMD_POST_PARAMS *PostParams) +{ + EmptyHeap(); +} + + +void fam_init_resume_post(struct romstage_params *param, AMD_RESUME_PARAMS *ResumeParams) +{ + if (IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || + IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) || + IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB)) + amd_initcpuio(); +} + +void fam_init_env_post(struct romstage_params *param, AMD_ENV_PARAMS *EnvParams) +{ + if (IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14)) + amd_initenv(); +} + +void fam_init_env(struct romstage_params *param, AMD_MID_PARAMS *EnvParams) +{ +} + +void fam_init_late_post(struct romstage_params *param, AMD_LATE_PARAMS *LateParams) +{ + cached_late_params = LateParams; +} + +/* ACPI S3 suspend-to-ram support functions. */ +void fam_init_resume_pre(struct romstage_params *param, AMD_RESUME_PARAMS *ResumeParams) +{ + OemInitResume(ResumeParams); +} + +void fam_s3late_restore_post(struct romstage_params *param, AMD_S3LATE_PARAMS *S3LateParams) +{ + OemS3LateRestore(AmdS3LateParams); +} + +void fam_s3_save_post(struct romstage_params *param, AMD_S3SAVE_PARAMS *S3SaveParams) +{ + if (status == AGESA_SUCCESS) + OemS3Save(AmdS3SaveParams); +} diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index d003be5..8a85cf8 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -629,21 +629,6 @@ static void domain_read_resources(struct device *dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(struct device *dev) -{ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3laterestore(); - - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -842,7 +827,6 @@ static void domain_set_resources(struct device *dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family15rl/state_machine.c b/src/northbridge/amd/agesa/family15rl/state_machine.c new file mode 100644 index 0000000..f739b6f --- /dev/null +++ b/src/northbridge/amd/agesa/family15rl/state_machine.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/agesawrapper.h> + +#include <cpu/amd/agesa/s3_resume.h> + + +void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + + +void platform_BeforeInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ + amd_initcpuio(); +} + + +void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid) +{ + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3laterestore(); + + if (!acpi_is_wakeup_s3()) { + + amd_initcpuio(); + + //agesawrapper_amdinitmid(); + } +} + +void platform_BeforeS3LateRestore(struct romstage_params *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(S3Late); +} + +void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct romstage_params *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2f05334..d487638 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -628,21 +628,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) -{ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3laterestore(); - - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -839,7 +824,6 @@ static void domain_set_resources(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c new file mode 100644 index 0000000..ae43a51 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/agesawrapper.h> + +#include <cpu/amd/agesa/s3_resume.h> + + +void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ + amd_initcpuio(); +} + + +void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct romstage_params *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(S3Late); +} + +void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid) +{ + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3laterestore(); + + if (!acpi_is_wakeup_s3()) { + + amd_initcpuio(); + + //agesawrapper_amdinitmid(); + } +} + +void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct romstage_params *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 28a4f91..f0a55c7 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -643,21 +643,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void domain_enable_resources(device_t dev) -{ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3laterestore(); - - /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) { - /* Enable MMIO on AMD CPU Address Map Controller */ - amd_initcpuio(); - - agesawrapper_amdinitmid(); - } - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); -} - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -858,7 +843,6 @@ static void domain_set_resources(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .init = DEVICE_NOOP, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c new file mode 100644 index 0000000..ae43a51 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "Porting.h" +#include "AGESA.h" + +#include <northbridge/amd/agesa/agesawrapper.h> + +#include <cpu/amd/agesa/s3_resume.h> + + +void platform_BeforeInitReset(struct romstage_params *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ + EmptyHeap(); +} + +void platform_BeforeInitResume(struct romstage_params *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(Resume); +} + +void platform_AfterInitResume(struct romstage_params *cb, AMD_POST_PARAMS *Post) +{ + amd_initcpuio(); +} + + +void platform_BeforeInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_AfterInitEnv(struct romstage_params *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct romstage_params *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(S3Late); +} + +void platform_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *Mid) +{ + if (acpi_is_wakeup_s3()) + agesawrapper_fchs3laterestore(); + + if (!acpi_is_wakeup_s3()) { + + amd_initcpuio(); + + //agesawrapper_amdinitmid(); + } +} + +void platform_AfterInitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct romstage_params *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(S3Save); +} diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c index c7d23ff..e37791b 100644 --- a/src/northbridge/amd/agesa/oem_s3.c +++ b/src/northbridge/amd/agesa/oem_s3.c @@ -125,6 +125,8 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams) if (size && dataBlock->NvStorageSize) spi_SaveS3info(pos, size, dataBlock->NvStorage, dataBlock->NvStorageSize); + else + die("MISSING MEMORY TRAINING DATA\n"); /* To be consumed in AmdS3LateRestore. */ char *heap = cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH); diff --git a/src/northbridge/amd/agesa/state_machine.c b/src/northbridge/amd/agesa/state_machine.c new file mode 100644 index 0000000..edb49bc --- /dev/null +++ b/src/northbridge/amd/agesa/state_machine.c @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> + +#include <arch/acpi.h> +#include <bootstate.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> + +#include "AMD.h" +#include "heapManager.h" + +#if ENV_RAMSTAGE +static void completion_InitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late); +#endif + + +static AGESA_STATUS amd_alloc(AMD_INTERFACE_PARAMS *p, AGESA_STRUCT_NAME func) +{ + p->StdHeader.Func = AMD_CREATE_STRUCT; + p->AgesaFunctionName = func; + p->AllocationMethod = 0; + p->NewStructPtr = NULL; + p->NewStructSize = 0; + return AmdAgesaDispatcher(p); +} + +static AGESA_STATUS amd_release(AMD_INTERFACE_PARAMS *p, AGESA_STRUCT_NAME func) +{ + /* Cannot release AMD_LATE_PARAMS until ACPI tables are done. */ + if (func == AMD_INIT_LATE) + return AGESA_SUCCESS; + + p->StdHeader.Func = AMD_RELEASE_STRUCT; + p->AgesaFunctionName = func; + p->AllocationMethod = 0; + return AmdAgesaDispatcher(p); +} + +static AGESA_STATUS amd_alloc_stack(AMD_INTERFACE_PARAMS *p, AGESA_STRUCT_NAME func, void *buf, size_t len) +{ + /* By design, each valid AGESA_STRUCT_NAME + * can be casted to AMD_CONFIG_PARAMS. + */ + AMD_CONFIG_PARAMS *call = buf; + memset(call, 0, len); + + p->StdHeader.Func = AMD_CREATE_STRUCT; + p->AgesaFunctionName = func; + p->AllocationMethod = ByHost; + p->NewStructPtr = call; + p->NewStructSize = len; + + /* AMD_CREATE_STRUCT with ByHost skips this. */ + *call = p->StdHeader; + + return AmdAgesaDispatcher(p); +} + +static AGESA_STATUS amd_release_stack(AMD_INTERFACE_PARAMS *p, AGESA_STRUCT_NAME func) +{ + p->StdHeader.Func = AMD_RELEASE_STRUCT; + p->AgesaFunctionName = func; + p->AllocationMethod = ByHost; + return AmdAgesaDispatcher(p); +} + +static AGESA_STATUS amd_dispatch(AMD_CONFIG_PARAMS *call, struct agesa_state *cfg) +{ + /* By design, for each valid AGESA_STRUCT_NAME, AMD_CONFIG_PARAMS + * can be evaluated to apply correct typecast based on Func field. + */ + + switch (call->Func) + { +#if ENV_ROMSTAGE + case AMD_INIT_RESET: + { + AMD_RESET_PARAMS *param = (void *)call; + platform_BeforeInitReset(cfg->romstage, param); + cfg->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_INIT_EARLY: + { + AMD_EARLY_PARAMS *param = (void *)call; + platform_BeforeInitEarly(cfg->romstage, param); + board_BeforeInitEarly(cfg->romstage, param); + cfg->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_INIT_POST: + { + AMD_POST_PARAMS *param = (void *)call; + platform_BeforeInitPost(cfg->romstage, param); + board_BeforeInitPost(cfg->romstage, param); + cfg->status = AmdAgesaDispatcher(call); + platform_AfterInitPost(cfg->romstage, param); + break; + } + + case AMD_INIT_RESUME: + { + AMD_RESUME_PARAMS *param = (void *)call; + platform_BeforeInitResume(cfg->romstage, param); + cfg->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_INIT_ENV: + { + AMD_ENV_PARAMS *param = (void *)call; + cfg->status = AmdAgesaDispatcher(call); + platform_AfterInitEnv(cfg->romstage, param); + break; + } + + case AMD_S3LATE_RESTORE: + { + AMD_S3LATE_PARAMS *param = (void *)call; + platform_BeforeS3LateRestore(cfg->romstage, param); + cfg->status = AmdAgesaDispatcher(call); + break; + } +#endif +#if ENV_RAMSTAGE + case AMD_INIT_MID: + { + AMD_MID_PARAMS *param = (void *)call; + platform_BeforeInitMid(cfg->ramstage, param); + board_BeforeInitMid(cfg->ramstage, param); + cfg->status = AmdAgesaDispatcher(call); + break; + } + + case AMD_S3_SAVE: + { + AMD_S3SAVE_PARAMS *param = (void *)call; + cfg->status = AmdAgesaDispatcher(call); + platform_AfterS3Save(cfg->ramstage, param); + break; + } + case AMD_INIT_LATE: + { + AMD_LATE_PARAMS *param = (void *)call; + cfg->status = AmdAgesaDispatcher(call); + platform_AfterInitLate(cfg->ramstage, param); + completion_InitLate(cfg->ramstage, param); + break; + } +#endif + default: + { + cfg->status = AGESA_UNSUPPORTED; + break; + } + + } + return cfg->status; +} + +static void state_on_entry(struct agesa_state *params, AGESA_STRUCT_NAME func) +{ + params->func = func; + params->function_name = agesa_struct_name(func); + + printk(BIOS_DEBUG, "\nAPIC %02d: ** Enter %s [%08x]\n", + params->apic_id, params->function_name, params->func); +} + +static void state_on_exit(struct agesa_state *params) +{ + AMD_INTERFACE_PARAMS *mm = params->amd_interface_params; + AMD_CONFIG_PARAMS *call = &mm->StdHeader; + + agesawrapper_trace(params->status, call, params->function_name); + + printk(BIOS_DEBUG, "APIC %02d: Heap in %s (%d) at 0x%08x\n", + params->apic_id, heap_status_name(call->HeapStatus), call->HeapStatus, + (u32)call->HeapBasePtr); + + printk(BIOS_DEBUG, "APIC %02d: ** Exit %s [%08x]\n", + params->apic_id, params->function_name, params->func); +} + +//int agesa_execute_state(struct agesa_state *params, AGESA_STRUCT_NAME func) +int agesa_execute_state(struct agesa_state *params, int func) +{ + AMD_INTERFACE_PARAMS *mm = params->amd_interface_params; + AMD_RESET_PARAMS reset; + AGESA_STATUS status; + + state_on_entry(params, func); + + if (func == AMD_INIT_RESET) + status = amd_alloc_stack(mm, func, &reset, sizeof(reset)); + else + status = amd_alloc(mm, func); + ASSERT(status == AGESA_SUCCESS); + + AMD_CONFIG_PARAMS *call = mm->NewStructPtr; + /* Must call the function buffer was allocated for.*/ + ASSERT(call->Func == func); + + status = amd_dispatch(call, params); + ASSERT(status < AGESA_FATAL); + + if (func == AMD_INIT_RESET) + status = amd_release_stack(mm, func); + else + status = amd_release(mm, func); + ASSERT(status == AGESA_SUCCESS); + + state_on_exit(params); + + return 0; +} + +#if !defined(__PRE_RAM__) + +static struct agesa_state state_machine; +static AMD_INTERFACE_PARAMS amd_interface_params; +static AMD_INTERFACE_PARAMS *aip = NULL; + +static void agesa_mid(void *unused) +{ + memset(&amd_interface_params, 0, sizeof(AMD_INTERFACE_PARAMS)); + aip = &amd_interface_params; + aip->StdHeader.CalloutPtr = GetBiosCallout; + + state_machine.amd_interface_params = aip; + agesa_execute_state(&state_machine, AMD_INIT_MID); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, agesa_mid, NULL); + +static void agesa_late(void *unused) +{ + if (acpi_is_wakeup_s3()) + return; + + agesa_execute_state(&state_machine, AMD_INIT_LATE); + + if (!acpi_s3_resume_allowed()) + return; + + agesa_execute_state(&state_machine, AMD_S3_SAVE); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesa_late, NULL); + + +/* We will reference AmdLateParams later to copy ACPI tables. */ +static AMD_LATE_PARAMS *AmdLateParams; + +static void completion_InitLate(struct romstage_params *cb, AMD_LATE_PARAMS *Late) +{ + AmdLateParams = Late; +} + +void *agesawrapper_getlateinitptr(int pick) +{ + ASSERT(AmdLateParams != NULL); + + switch (pick) { + case PICK_DMI: + return AmdLateParams->DmiTable; + case PICK_PSTATE: + return AmdLateParams->AcpiPState; + case PICK_SRAT: + return AmdLateParams->AcpiSrat; + case PICK_SLIT: + return AmdLateParams->AcpiSlit; + case PICK_WHEA_MCE: + return AmdLateParams->AcpiWheaMce; + case PICK_WHEA_CMC: + return AmdLateParams->AcpiWheaCmc; + case PICK_ALIB: + return AmdLateParams->AcpiAlib; + case PICK_IVRS: +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY14) + return NULL; +#else + return AmdLateParams->AcpiIvrs; +#endif + default: + return NULL; + } + return NULL; +} + +#endif /* __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ +#if 0 + AGESA_STATUS status; + AP_EXE_PARAMS ApExeParams; + + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); + ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; + + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + status = AmdLateRunApTask(&ApExeParams); + AGESA_EVENTLOG(status, &ApExeParams.StdHeader); + ASSERT(status == AGESA_SUCCESS); + + return status; +#else + return AGESA_SUCCESS; +#endif +} + +#if 0 +void __attribute__((weak)) board_BeforeInitEarly(struct romstage_params *cb, AMD_EARLY_PARAMS *p) { } +void __attribute__((weak)) board_BeforeInitPost(struct romstage_params *cb, AMD_POST_PARAMS *p) { } +void __attribute__((weak)) board_BeforeInitMid(struct romstage_params *cb, AMD_MID_PARAMS *p) { } +#endif diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h new file mode 100644 index 0000000..9a76d3c --- /dev/null +++ b/src/northbridge/amd/agesa/state_machine.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _STATE_MACHINE_H_ +#define _STATE_MACHINE_H_ + +#include <stdint.h> +#include "Porting.h" +#include "AGESA.h" + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ +}; + +AGESA_STATUS agesawrapper_amdinitlate(void); +AGESA_STATUS agesawrapper_amdinitmid(void); + +const char *agesa_struct_name(int state); +const char *heap_status_name(int status); +void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); + +void amd_initcpuio(void); +void amd_initmmio(void); +void amd_initenv(void); + +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +void *agesawrapper_getlateinitptr (int pick); + +AGESA_STATUS agesawrapper_fchs3earlyrestore(void); +AGESA_STATUS agesawrapper_fchs3laterestore(void); + +struct OEM_HOOK +{ + /* romstage */ + AGESA_STATUS (*InitEarly)(AMD_EARLY_PARAMS *); + AGESA_STATUS (*InitPost)(AMD_POST_PARAMS *); + + /* ramstage */ + AGESA_STATUS (*InitMid)(AMD_MID_PARAMS *); +}; + +extern const struct OEM_HOOK OemCustomize; + +/* For suspend-to-ram support. */ +AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams); +AGESA_STATUS OemS3LateRestore(AMD_S3LATE_PARAMS *S3LateParams); +AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams); + + +#endif /* _STATE_MACHINE_H_ */ diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 022eb09..e0693f8 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -324,5 +324,5 @@ $(obj)/libagesa.fam14.a: $$(libagesa-objs) @printf " AGESA $(subst $(obj)/,,$(@))\n" $(AR_romstage) rcs $@ $+ -romstage-libs += $(obj)/libagesa.fam14.a -ramstage-libs += $(obj)/libagesa.fam14.a +## romstage-libs += $(obj)/libagesa.fam14.a +## ramstage-libs += $(obj)/libagesa.fam14.a diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c index e0ad3c6..a2cee80 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c @@ -124,6 +124,8 @@ AmdReadEventLog ( ASSERT (Event != NULL); Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader); Status = GetEventLog (&LogEvent, &Event->StdHeader); + if (Status != AGESA_SUCCESS) + return Status; Event->EventClass = LogEvent.EventClass; Event->EventInfo = LogEvent.EventInfo; @@ -206,7 +208,15 @@ PutEventLog ( UINT16 Index; AGESA_STRUCT_BUFFER *AgesaEventAlloc; - IDS_HDT_CONSOLE (MAIN_FLOW, "\n * %s Event: %08x Data: %x, %x, %x, %x\n\n", + /* Suppress error of S3 SCRIPT TABLE appearing only after INIT_POST. */ + if ((DataParam1 == AMD_S3_SCRIPT_SAVE_TABLE_HANDLE) && + (EventInfo == CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT) && + (StdHeader->Func != AMD_INIT_LATE) && + (StdHeader->Func != AMD_INIT_ENV) && + (StdHeader->Func != AMD_INIT_MID)) + return; + + IDS_HDT_CONSOLE (MAIN_FLOW, "%s Event: %08x Data: %x, %x, %x, %x\n", (EventClass == AGESA_FATAL) ? "FATAL" : (EventClass == AGESA_CRITICAL) ? "CRITICAL" : (EventClass == AGESA_ERROR) ? "ERROR" : @@ -281,6 +291,8 @@ GetEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return (AGESA_BOUNDS_CHK); if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) {

1 0

Patch set updated for coreboot: MAINTAINERS: Add myself as me_cleaner maintainer
by Martin Roth 23 Feb '17

23 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18474 -gerrit commit 019eae9134b9d81f37a9c3a41b3b0f25ac343668 Author: Nicola Corna <nicola(a)corna.info> Date: Thu Feb 23 16:53:45 2017 +0100 MAINTAINERS: Add myself as me_cleaner maintainer Change-Id: Ia95f6beb1546efdb75a49bccfe293822f0785d7a Signed-off-by: Nicola Corna <nicola(a)corna.info> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 015dbbf..e672fd7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -384,6 +384,12 @@ INTELMETOOL M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> F: util/intelmetool/ +ME_CLEANER +M: Nicola Corna <nicola(a)corna.info> +W: https://github.com/corna/me_cleaner +S: Maintained +F: util/me_cleaner/ + IFDTOOL M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> F: util/ifdtool/

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Patch set updated for coreboot: nb/i945: Clean "Programming DLL Timings" function
by Martin Roth 23 Feb '17

23 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18472 -gerrit commit cc2c595bf1c4e06a7e13891c89c71afbf1bd8053 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Feb 23 13:14:44 2017 +0100 nb/i945: Clean "Programming DLL Timings" function As we drive both channels with the same speed, chen0dll and chen1dll are the same. Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a8bb5e7..8fada16 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1227,7 +1227,7 @@ static void sdram_enable_rcomp(void) static void sdram_program_dll_timings(struct sys_info *sysinfo) { - u32 chan0dll = 0, chan1dll = 0; + u32 channeldll = 0; int i; printk(BIOS_DEBUG, "Programming DLL Timings...\n"); @@ -1238,26 +1238,26 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) /* We drive both channels with the same speed */ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ + case 400: channeldll = 0x26262626; break; + case 533: channeldll = 0x22222222; break; + case 667: channeldll = 0x11111111; break; } } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ - case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ - case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ + case 400: channeldll = 0x33333333; break; + case 533: channeldll = 0x24242424; break; + case 667: channeldll = 0x25252525; break; } } for (i = 0; i < 4; i++) { - MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll; - MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = chan0dll & 0xff; - MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = chan1dll & 0xff; + MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; + MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } } }

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Patch set updated for coreboot: soc/intel/skylake: disable voltage margining
by Martin Roth 23 Feb '17

23 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18469 -gerrit commit 2f555f3e83cae845646eb5089fce9870275a47b4 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 23 14:43:39 2017 +0530 soc/intel/skylake: disable voltage margining Voltage margining should be disabled for S0ix to work, use the UPD provided by FSP to enable/disable the voltage margining when SLP_S0# is asserted. Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/chip.h | 8 ++++++++ src/soc/intel/skylake/chip_fsp20.c | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2e4adb2..8e6fa69 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -333,6 +333,14 @@ struct soc_intel_skylake_config { * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s */ u8 PmConfigPwrBtnOverridePeriod; + + /* + * PCH Pm Slp S0 Voltage Margining Enable + * Indicates platform has support for VCCPrim_Core Voltage Margining + * in SLP_S0# asserted state. + */ + u8 PchPmSlpS0VmEnable; + /* * Reset Power Cycle Duration could be customized in the unit of second. * PCH HW default is 4 seconds, and range is 1~4 seconds. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 8b8c37c..3d2f2cb 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -220,6 +220,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + + /* Disable Voltage margining if S0ix is enabled */ + if (config->s0ix_enable) + params->PchPmSlpS0VmEnable = 0x0; + params->PchSirqEnable = config->SerialIrqConfigSirqEnable; params->PchSirqMode = config->SerialIrqConfigSirqMode;

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Patch merged into coreboot/master: google/gru: whitespace fix
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit 96af0afcd76dc8a40afbd4c73bd6369aa9f8daed Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Feb 23 17:44:13 2017 +0100 google/gru: whitespace fix Follow up to https://review.coreboot.org/#/c/18460/ Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/18475 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18475 for details. -gerrit

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Patch merged into coreboot/master: google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit ebbdd2882e49c6f94a573ebcf11d04ae1129a928 Author: William wu <wulf(a)rock-chips.com> Date: Mon Jan 23 20:54:22 2017 +0800 google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold According to USB 2.0 Spec Table 7-7, the High-speed squelch detection threshold Min 100mV and Max 150mV, and we set USB 2.0 PHY0 and PHY1 squelch detection threshold to 150mV by default, so if the amplitude of differential voltage envelope is < 150 mV, the USB 2.0 PHYs envelope detector will indicate it as squelch. On Kevin board, if we connect usb device with Samsung U2 cable, we can see that the impedance of U2 cable is too big according to the eye-diagram test report, and this cause serious signal attenuation at the end of receiver, the amplitude of differential voltage falls below 150mV. This patch aims to reduce the PHY0 and PHY1 otg-ports squelch detection threshold to 125mV (host-ports still use 150mV by default), this is helpful to increase USB 2.0 PHY compatibility. BRANCH=gru BUG=chrome-os-partner:62320 TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into Type-C port, check if the USB device can be detected. Change-Id: Ia0a2d354781c2ac757938409490f7c4eecdffe61 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7d74311c25762668386061234df0562f84b7203e Original-Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8 Original-Signed-off-by: William wu <wulf(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/431015 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Inno Park <ih.yoo.park(a)samsung.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18462 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18462 for details. -gerrit

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Patch merged into coreboot/master: google/gru: update the pwm regulator
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit 8c454aaafaf5bc13a50c4f4b3631e6be32fa0bca Author: Caesar Wang <wxt(a)rock-chips.com> Date: Wed Jan 4 18:26:04 2017 +0800 google/gru: update the pwm regulator As David commented the "Bob and other follow-ons match Gru, Kevin should be the special case here", and update the calculations value for gru/bob board. From the actual tests, some regulator voltage than the actual set of less than 20mv on bob board. (e.g: little-cpus and Center-logic) Update the {min, max} regulator voltage for Bob board. Make sure we get the accurate voltage. BUG=chrome-os-partner:61497 BRANCH=none TEST=boot up Bob, measure the voltage for little cpu and C-logic. Change-Id: Iad881b41d67708776bfb681487cf8cec8518064e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 25e133815f49018e7496c75077b8559c207350a4 Original-Change-Id: I3098c742c7ec355c88f45bd1d93f878a7976a6b4 Original-Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao(a)asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/424523 Original-Reviewed-by: David Schneider <dnschneid(a)chromium.org> Original-Reviewed-by: Brian Norris <briannorris(a)chromium.org> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao(a)asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/430403 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/18460 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18460 for details. -gerrit

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Patch merged into coreboot/master: mb/google/poppy: Enable support for DPTF
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit d56fae18dcb650271d9664ccfa7ca12364f2228f Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Feb 20 10:34:01 2017 +0530 mb/google/poppy: Enable support for DPTF This patch adds the DPTF settings specfic to the mainboard and enables the CPU and other thermal sensors as participant device for poppy. It enables the DPTF flag in the device tree for poppy. It also includes the DPTF specific ASL file in the main DSDT definition. BUG=None BRANCH=None TEST=Built for poppy. Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/17926 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17926 for details. -gerrit

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Patch set updated for coreboot: mb/google/poppy: Enable support for DPTF
by Martin Roth 23 Feb '17

23 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17926 -gerrit commit e734827c60c6aaf3bfcf2fc466d37aaf1d72e04b Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Feb 20 10:34:01 2017 +0530 mb/google/poppy: Enable support for DPTF This patch adds the DPTF settings specfic to the mainboard and enables the CPU and other thermal sensors as participant device for poppy. It enables the DPTF flag in the device tree for poppy. It also includes the DPTF specific ASL file in the main DSDT definition. BUG=None BRANCH=None TEST=Built for poppy. Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/mainboard/google/poppy/acpi/dptf.asl | 83 ++++++++++++++++++++++++++++++++ src/mainboard/google/poppy/devicetree.cb | 4 ++ src/mainboard/google/poppy/dsdt.asl | 6 +++ 3 files changed, 93 insertions(+) diff --git a/src/mainboard/google/poppy/acpi/dptf.asl b/src/mainboard/google/poppy/acpi/dptf.asl new file mode 100644 index 0000000..7f6cd8e --- /dev/null +++ b/src/mainboard/google/poppy/acpi/dptf.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 94 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Ambient" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Charger" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "DRAM" +#define DPTF_TSR2_PASSIVE 52 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 4500, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 3000, /* PowerLimitMinimum */ + 7000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index b3b7623..3beea63 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -19,6 +19,9 @@ chip soc/intel/skylake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Enable DPTF + register "dptf_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" @@ -184,6 +187,7 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tdp_pl2_override" = "7" + register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_G7" diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index c678dfc..2007691 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -61,4 +61,10 @@ DefinitionBlock( /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + Scope (\_SB) + { + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } }

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coreboot-gerrit February 2017