coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: nb/i945: Clean Programming DLL Timings
by HAOUAS Elyes 23 Feb '17

23 Feb '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18472 -gerrit commit 857ceefb6e1d009de24d7b62a05058bc174492d6 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Feb 23 13:14:44 2017 +0100 nb/i945: Clean Programming DLL Timings Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a8bb5e7..50ab635 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1238,15 +1238,15 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) /* We drive both channels with the same speed */ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ + case 400: chan0dll = chan1dll = 0x26262626; break; + case 533: chan0dll = chan1dll = 0x22222222; break; + case 667: chan0dll = chan1dll = 0x11111111; break; } } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ - case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ - case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ + case 400: chan0dll = chan1dll = 0x33333333; break; + case 533: chan0dll = chan1dll = 0x24242424; break; + case 667: chan0dll = chan1dll = 0x25252525; break; } }

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Patch set updated for coreboot: soc/intel/skylake: Use intel/common/basecode/bootblock stage
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18459 -gerrit commit 3ef1159e9ac037604d3030b2edbe2ebfab56b20d Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 19:30:21 2017 +0530 soc/intel/skylake: Use intel/common/basecode/bootblock stage TEST=Booted till post code 0x2b and ensure its execute PCIEXBAR programming bootblock_systemagent_early_init() Change-Id: I120aceb55e58fb11f97dcc3bd04bf5cfdc8c3826 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/bootblock.c | 51 ----------------------------- 3 files changed, 1 insertion(+), 52 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 90f87ab..cc26b3f 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select RTC + select SOC_INTEL_BASECODE select SOC_INTEL_CAR_BIG_CORE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index dfda301..425ef41 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c deleted file mode 100644 index 93a031f..0000000 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation.. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> -#include <soc/bootblock.h> - -void asmlinkage bootblock_c_entry(uint64_t base_timestamp) -{ - /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp); -} - -void bootblock_soc_early_init(void) -{ - bootblock_systemagent_early_init(); - bootblock_pch_early_init(); - bootblock_cpu_init(); - pch_early_iorange_init(); - - if (IS_ENABLED(CONFIG_UART_DEBUG)) - pch_uart_init(); -} - -void bootblock_soc_init(void) -{ - /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */ - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) - bootblock_fsp_temp_ram_init(); - - /* - * Perform early chipset initialization before fsp memory init - * example: pirq->irq programming, enabling smbus, set pmcbase - * and abase, i2c programming and print platform info - */ - report_platform_info(); - set_max_freq(); - pch_early_init(); - i2c_early_init(); -}

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Patch set updated for coreboot: soc/intel/glk: Use intel/common/basecode/bootblock stage
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18458 -gerrit commit 5ed94a90bc38f66ba100fce6617eaec047cedb07 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 19:26:33 2017 +0530 soc/intel/glk: Use intel/common/basecode/bootblock stage TEST=Booted till post code 0x2b and ensure its execute PCIEXBAR programming bootblock_systemagent_early_init() Change-Id: I86bd9e777e23ca1a77008ea9b087d45aec382ccc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index f2fe32f..bf3fa87 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select RTC select SMM_TSEG + select SOC_INTEL_BASECODE select SOC_INTEL_CAR_SMALL_CORE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI

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Patch set updated for coreboot: soc/intel/common: Add bootblock common stage file [WIP]
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18457 -gerrit commit f8c647f1879d9a9288ee1d0301db04f9a93703ad Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Feb 21 18:25:30 2017 +0530 soc/intel/common: Add bootblock common stage file [WIP] Currently added till bootblock_systemagent_early_init and expectation to reach post code 0x2b. Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/basecode/Kconfig | 4 ++ src/soc/intel/common/basecode/Makefile.inc | 5 +++ src/soc/intel/common/basecode/bootblock.c | 52 +++++++++++++++++++++++ src/soc/intel/common/basecode/include/bootblock.h | 40 +++++++++++++++++ 5 files changed, 102 insertions(+) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 675b9b5..12b310e 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -36,6 +36,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c +CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include/ CPPFLAGS_common += -I$(src)/soc/intel/common/block/include # Create and add the MRC cache to the cbfs image diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig new file mode 100644 index 0000000..24cd7a3 --- /dev/null +++ b/src/soc/intel/common/basecode/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_BASECODE + bool + help + Base code driver for non IP code diff --git a/src/soc/intel/common/basecode/Makefile.inc b/src/soc/intel/common/basecode/Makefile.inc new file mode 100644 index 0000000..074c782 --- /dev/null +++ b/src/soc/intel/common/basecode/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_INTEL_BASECODE),y) + +bootblock-y += bootblock.c + +endif diff --git a/src/soc/intel/common/basecode/bootblock.c b/src/soc/intel/common/basecode/bootblock.c new file mode 100644 index 0000000..6deac95 --- /dev/null +++ b/src/soc/intel/common/basecode/bootblock.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation.. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <bootblock.h> + +void asmlinkage bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_timestamp(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_systemagent_early_init(); + /* TODO: Add PCH and CPU driver + bootblock_pch_early_init(); + bootblock_cpu_early_init(); + */ + if (IS_ENABLED(CONFIG_UART_DEBUG)) + pch_uart_init(); +} + +void bootblock_soc_init(void) +{ + /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */ + if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + bootblock_fsp_temp_ram_init(); + + /* + * Perform early chipset initialization before fsp memory init + * example: pirq->irq programming, enabling smbus, set pmcbase + * and abase, i2c programming and print platform info + */ + /* TODO: Add PCH and CPU driver + report_platform_info(); + bootblock_cpu_init(); + bootblock_pch_init(); + */ +} diff --git a/src/soc/intel/common/basecode/include/bootblock.h b/src/soc/intel/common/basecode/include/bootblock.h new file mode 100644 index 0000000..a59b5bf --- /dev/null +++ b/src/soc/intel/common/basecode/include/bootblock.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BASECODE_BOOTBLOCK_H_ +#define _SOC_BASECODE_BOOTBLOCK_H_ + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#include <fsp/bootblock.h> +#else +static inline void bootblock_fsp_temp_ram_init(void) {} +#endif + +#include <intelblocks/systemagent.h> + +/* Bootblock pre console init programing */ +void bootblock_cpu_early_init(void); +void bootblock_pch_early_init(void); +void pch_uart_init(void); + +/* Bootblock post console init programing */ +void enable_smbus(void); +void pch_early_iorange_init(void); +void report_platform_info(void); +void report_memory_config(void); +void bootblock_cpu_init(void); +void bootblock_pch_init(void); + +#endif

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Patch set updated for coreboot: soc/intel/skylake: Use intel/common/block/systemagent code
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18456 -gerrit commit fe6300ca1d17d4772b297fdd00a147fc418708e8 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Feb 22 18:43:43 2017 +0530 soc/intel/skylake: Use intel/common/block/systemagent code Change-Id: Ib471ef3d3ae96b69e2bdfaf81554325d0393900d Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/systemagent.c | 43 --------------------------- 3 files changed, 1 insertion(+), 44 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 132fa6d..90f87ab 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_SA select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select SOC_INTEL_COMMON_XHCI select SMM_TSEG diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 181e17b..dfda301 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += bootblock/smbus.c -bootblock-y += bootblock/systemagent.c bootblock-y += flash_controller.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c deleted file mode 100644 index e76d4d2..0000000 --- a/src/soc/intel/skylake/bootblock/systemagent.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/bootblock.h> -#include <soc/pci_devs.h> -#include <soc/systemagent.h> - -void bootblock_systemagent_early_init(void) -{ - uint32_t reg; - - /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. - * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. - */ - reg = 0; - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); -}

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Patch set updated for coreboot: soc/intel/glk: Use intel/common/block/systemagent code
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18455 -gerrit commit ac8cb762dd45942e736bc56c86a14d85493f3378 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Feb 22 18:39:08 2017 +0530 soc/intel/glk: Use intel/common/block/systemagent code Change-Id: Ibde64058e9f23f25daabab82956cc360e693e422 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/glk/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index c8ecaaf..f2fe32f 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_LPSS_I2C + select SOC_INTEL_COMMON_SA select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select SOC_INTEL_COMMON_XHCI

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Patch set updated for coreboot: soc/intel/common/block: [WIP]Add Intel common systemagent support
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18454 -gerrit commit f6dc1ce49833cdce2dd7d96c44100070bfd70bd9 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Feb 15 20:09:10 2017 +0530 soc/intel/common/block: [WIP]Add Intel common systemagent support Create common Intel systemagent code. This code currently contains the SA initialization required in Bootblock phase, which has the following programming- * Set PCIEXBAR * Clear TSEG register More code will get added up in the subsequent phases. Change-Id: Ib8a77aec8b20bafd4175048d442701250f1aa9c8 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- .../common/block/include/intelblocks/pci_devs.h | 37 +++++++++++++++++ .../common/block/include/intelblocks/systemagent.h | 31 ++++++++++++++ src/soc/intel/common/block/systemagent/Kconfig | 4 ++ .../intel/common/block/systemagent/Makefile.inc | 5 +++ .../intel/common/block/systemagent/systemagent.c | 48 ++++++++++++++++++++++ 5 files changed, 125 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/pci_devs.h b/src/soc/intel/common/block/include/intelblocks/pci_devs.h new file mode 100644 index 0000000..d42e930 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pci_devs.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PCI_DEVS_H_ +#define _SOC_PCI_DEVS_H_ + +#include <device/pci_def.h> +#include <rules.h> + +#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if ENV_RAMSTAGE +#include <device/device.h> +#include <device/pci_def.h> +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) +#else +#include <arch/io.h> +#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +#endif + diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h new file mode 100644 index 0000000..16ef426 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_SYSTEM_AGENT_H_ +#define _SOC_SYSTEM_AGENT_H_ + +/* System Agent Devices */ +#define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) +#define SA_DEV_ROOT _SA_DEV(ROOT) + +/* PCI Config Registers */ +#define PCIEXBAR 0x60 +#define TSEG 0xb8 /* TSEG base */ + +void bootblock_systemagent_early_init(void); + +#endif + diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig new file mode 100644 index 0000000..b060bd1 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_SA + bool + help + Intel Processor common System Agent support diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc new file mode 100644 index 0000000..9544767 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_INTEL_COMMON_SA),y) + +bootblock-y += systemagent.c + +endif diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c new file mode 100644 index 0000000..1c59d1f --- /dev/null +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <intelblocks/systemagent.h> +#include <intelblocks/pci_devs.h> + +void bootblock_systemagent_early_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); + + /* + * Clear TSEG register - TSEG register comes out of reset with a + * non-zero default value. Clear this register to ensure that there are + * no surprises in CBMEM handling. + */ + pci_io_write_config32(SA_DEV_ROOT, TSEG, 0); +} +

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Patch set updated for coreboot: soc/intel/skylake: Use intel/common/basecode/bootblock stage
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18459 -gerrit commit ed1694e48df159f6e46b3ef5b5a4c25b8325cda5 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 19:30:21 2017 +0530 soc/intel/skylake: Use intel/common/basecode/bootblock stage TEST=Booted till post code 0x2b and ensure its execute PCIEXBAR programming bootblock_systemagent_early_init() Change-Id: I120aceb55e58fb11f97dcc3bd04bf5cfdc8c3826 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/bootblock.c | 51 ----------------------------- 3 files changed, 1 insertion(+), 52 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 90f87ab..cc26b3f 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select RTC + select SOC_INTEL_BASECODE select SOC_INTEL_CAR_BIG_CORE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index dfda301..425ef41 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c deleted file mode 100644 index 93a031f..0000000 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation.. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> -#include <soc/bootblock.h> - -void asmlinkage bootblock_c_entry(uint64_t base_timestamp) -{ - /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(base_timestamp); -} - -void bootblock_soc_early_init(void) -{ - bootblock_systemagent_early_init(); - bootblock_pch_early_init(); - bootblock_cpu_init(); - pch_early_iorange_init(); - - if (IS_ENABLED(CONFIG_UART_DEBUG)) - pch_uart_init(); -} - -void bootblock_soc_init(void) -{ - /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */ - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) - bootblock_fsp_temp_ram_init(); - - /* - * Perform early chipset initialization before fsp memory init - * example: pirq->irq programming, enabling smbus, set pmcbase - * and abase, i2c programming and print platform info - */ - report_platform_info(); - set_max_freq(); - pch_early_init(); - i2c_early_init(); -}

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Patch set updated for coreboot: soc/intel/glk: Use intel/common/basecode/bootblock stage
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18458 -gerrit commit d656d40236d94b72cfe17045e81d4cfe0a1e75cd Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 19:26:33 2017 +0530 soc/intel/glk: Use intel/common/basecode/bootblock stage TEST=Booted till post code 0x2b and ensure its execute PCIEXBAR programming bootblock_systemagent_early_init() Change-Id: I86bd9e777e23ca1a77008ea9b087d45aec382ccc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index f2fe32f..bf3fa87 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select RTC select SMM_TSEG + select SOC_INTEL_BASECODE select SOC_INTEL_CAR_SMALL_CORE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI

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Patch set updated for coreboot: soc/intel/common: Add bootblock common stage file [WIP]
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18457 -gerrit commit 56fec38ba3a30c4b7b19400962bbe004dd77f858 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Feb 21 18:25:30 2017 +0530 soc/intel/common: Add bootblock common stage file [WIP] Currently added till bootblock_systemagent_early_init and expectation to reach post code 0x2b. Change-Id: If84c08d33f6f8fd3cd9722ee893653f1d1ae90c1 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/basecode/Kconfig | 4 ++ src/soc/intel/common/basecode/Makefile.inc | 5 +++ src/soc/intel/common/basecode/bootblock.c | 52 +++++++++++++++++++++++ src/soc/intel/common/basecode/include/bootblock.h | 40 +++++++++++++++++ 5 files changed, 102 insertions(+) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 675b9b5..12b310e 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -36,6 +36,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c +CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include/ CPPFLAGS_common += -I$(src)/soc/intel/common/block/include # Create and add the MRC cache to the cbfs image diff --git a/src/soc/intel/common/basecode/Kconfig b/src/soc/intel/common/basecode/Kconfig new file mode 100644 index 0000000..24cd7a3 --- /dev/null +++ b/src/soc/intel/common/basecode/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_BASECODE + bool + help + Base code driver for non IP code diff --git a/src/soc/intel/common/basecode/Makefile.inc b/src/soc/intel/common/basecode/Makefile.inc new file mode 100644 index 0000000..074c782 --- /dev/null +++ b/src/soc/intel/common/basecode/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_SOC_INTEL_BASECODE),y) + +bootblock-y += bootblock.c + +endif diff --git a/src/soc/intel/common/basecode/bootblock.c b/src/soc/intel/common/basecode/bootblock.c new file mode 100644 index 0000000..6deac95 --- /dev/null +++ b/src/soc/intel/common/basecode/bootblock.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation.. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <bootblock.h> + +void asmlinkage bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_timestamp(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + bootblock_systemagent_early_init(); + /* TODO: Add PCH and CPU driver + bootblock_pch_early_init(); + bootblock_cpu_early_init(); + */ + if (IS_ENABLED(CONFIG_UART_DEBUG)) + pch_uart_init(); +} + +void bootblock_soc_init(void) +{ + /* FSP 2.0 does not provide FSP-T/TempRamInit init support yet */ + if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + bootblock_fsp_temp_ram_init(); + + /* + * Perform early chipset initialization before fsp memory init + * example: pirq->irq programming, enabling smbus, set pmcbase + * and abase, i2c programming and print platform info + */ + /* TODO: Add PCH and CPU driver + report_platform_info(); + bootblock_cpu_init(); + bootblock_pch_init(); + */ +} diff --git a/src/soc/intel/common/basecode/include/bootblock.h b/src/soc/intel/common/basecode/include/bootblock.h new file mode 100644 index 0000000..a59b5bf --- /dev/null +++ b/src/soc/intel/common/basecode/include/bootblock.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BASECODE_BOOTBLOCK_H_ +#define _SOC_BASECODE_BOOTBLOCK_H_ + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#include <fsp/bootblock.h> +#else +static inline void bootblock_fsp_temp_ram_init(void) {} +#endif + +#include <intelblocks/systemagent.h> + +/* Bootblock pre console init programing */ +void bootblock_cpu_early_init(void); +void bootblock_pch_early_init(void); +void pch_uart_init(void); + +/* Bootblock post console init programing */ +void enable_smbus(void); +void pch_early_iorange_init(void); +void report_platform_info(void); +void report_memory_config(void); +void bootblock_cpu_init(void); +void bootblock_pch_init(void); + +#endif

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coreboot-gerrit February 2017