coreboot-gerrit December 2017

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Change in coreboot[master]: soc/amd/stoneyridge: Add USB OC support
by Marc Jones (Code Review) 02 Dec '17

02 Dec '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22678 Change subject: soc/amd/stoneyridge: Add USB OC support ...................................................................... soc/amd/stoneyridge: Add USB OC support Add USB overcurrent support. Adds a weak call for mainboards that don't suport USB OC. BUG=b:69229635 Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/usb.c 2 files changed, 65 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/22678/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f840fd9..44e6f4c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -268,6 +268,28 @@ #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD BIT(1) +#define XHCI_PM_INDIRECT_INDEX 0x48 +#define XHCI_PM_INDIRECT_DATA 0x4C +#define XHCI_OVER_CURRENT_CONTROL 0x30 + +#define EHCI_OVER_CURRENT_CONTROL 0x70 + +#define USB_OC0 0 +#define USB_OC1 1 +#define USB_OC2 2 +#define USB_OC3 3 +#define USB_OC4 4 +#define USB_OC5 5 +#define USB_OC6 6 +#define USB_OC7 7 +#define USB_OC_DISABLE 0xf +#define USB_OC_DISABLE_ALL 0xffff + +#define OC_PORT0_SHIFT 0 +#define OC_PORT1_SHIFT 4 +#define OC_PORT2_SHIFT 8 +#define OC_PORT3_SHIFT 12 + static inline int sb_sata_enable(void) { /* True if IDE or AHCI. */ @@ -322,4 +344,13 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos); void bootblock_fch_early_init(void); +/* + * Call the mainboard to get the USB Over Current Map. The mainboard + * returns the map and 0 on Success or -1 on error or no map. There is + * a default weak function in usb.c if the mainboard doesn't have any + * over current support. + */ +int get_xhci_oc_map(uint16_t *usb_oc_map); +int get_ehci_oc_map(uint16_t *usb_oc_map); + #endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index 82984b9..b61370e 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -20,7 +20,40 @@ #include <device/pci_ops.h> #include <device/pci_ehci.h> #include <arch/io.h> +#include <soc/pci_devs.h> #include <soc/southbridge.h> + + +static void set_usb_over_current(device_t dev) +{ + uint16_t map = 0xFFFF; + + + if (dev->path.pci.devfn == XHCI_DEVFN) { + if (get_xhci_oc_map(&map) == 0) { + xhci_pm_write32(XHCI_PM_INDIRECT_INDEX, + XHCI_OVER_CURRENT_CONTROL); + xhci_pm_write16(XHCI_PM_INDIRECT_DATA, (uint32_t)map); + } + } + + if (dev->path.pci.devfn == EHCI1_DEVFN) { + if (get_ehci_oc_map(&map) == 0) + pci_write_config16(dev, EHCI_OVER_CURRENT_CONTROL, map); + } +} + +int __attribute__((weak)) get_xhci_oc_map(uint16_t *map) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} + +int __attribute__((weak)) get_ehci_oc_map(uint16_t *map) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, @@ -30,7 +63,7 @@ .read_resources = pci_ehci_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = NULL, + .init = set_usb_over_current, .scan_bus = NULL, .ops_pci = &lops_pci, }; -- To view, visit https://review.coreboot.org/22678 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674 Gerrit-Change-Number: 22678 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: google/kahlee: Set USB OC pins
by Marc Jones (Code Review) 02 Dec '17

02 Dec '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22679 Change subject: google/kahlee: Set USB OC pins ...................................................................... google/kahlee: Set USB OC pins Set the USB over current pins for the Grunt baseboard and Kahlee mainboard. Removes the ACPI ASL OC code, which is not used on Stoney Ridge SOC. BUG=b:69229635 TEST=Build and boot Kahlee. Not tested with OC test fixture. Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/google/kahlee/dsdt.asl M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h D src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/usb_oc.asl M src/mainboard/google/kahlee/variants/kahlee/gpio.c D src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/usb_oc.asl 8 files changed, 45 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22679/1 diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl index ded0dc8..ff3bb73 100644 --- a/src/mainboard/google/kahlee/dsdt.asl +++ b/src/mainboard/google/kahlee/dsdt.asl @@ -33,9 +33,6 @@ /* Globals for the platform */ #include "acpi/mainboard.asl" - /* Describe the USB Overcurrent pins */ - #include "variant/acpi/usb_oc.asl" - /* PCI IRQ mapping for the Southbridge */ #include <pcie.asl> diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index f757504..67a9fec 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -23,6 +23,7 @@ #include <boardid.h> #include <soc/nvs.h> #include <soc/smi.h> +#include <soc/southbridge.h> #include <variant/ec.h> #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -125,6 +126,16 @@ } } +int get_xhci_oc_map(uint16_t *map) +{ + return variant_get_xhci_oc_map(map); +} + +int get_ehci_oc_map(uint16_t *map) +{ + return variant_get_ehci_oc_map(map); +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = kahlee_enable, diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 4dc6d45..0f0015f 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -42,3 +42,17 @@ *num = ARRAY_SIZE(gpe_table); return gpe_table; } + +int __attribute__((weak)) variant_get_xhci_oc_map(uint16_t *map) +{ + *map = USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0 = OC0 */ + *map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1 = OC1 */ + return 0; +} + +int __attribute__((weak)) variant_get_ehci_oc_map(uint16_t *map) +{ + *map = USB_OC2 << OC_PORT0_SHIFT; /* USB-A Port0 = OC2 */ + *map |= USB_OC3 << OC_PORT1_SHIFT; /* USB-A Port1 = OC3 */ + return 0; +} diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl deleted file mode 100644 index 72f26d8..0000000 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* USB overcurrent mapping pins. */ -Name (UOM0, 0) -Name (UOM1, 0) -Name (UOM2, 0) -Name (UOM3, 0) -Name (UOM4, 0) -Name (UOM5, 0) -Name (UOM6, 0) -Name (UOM7, 0) -Name (UOM8, 0) -Name (UOM9, 0) - -/* USB Overcurrent GPEs */ diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index 1d38bd4..33054f5 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -25,5 +25,7 @@ const struct sci_source *get_gpe_table(size_t *num); uint8_t variant_memory_sku(void); int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); +int variant_get_xhci_oc_map(uint16_t *usb_oc_map); +int variant_get_ehci_oc_map(uint16_t *usb_oc_map); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/usb_oc.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/usb_oc.asl deleted file mode 100644 index d22628c..0000000 --- a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/usb_oc.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/acpi/usb_oc.asl> diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index d90a99c..5cc0608 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -148,3 +148,21 @@ *num = ARRAY_SIZE(gpe_table); return gpe_table; } + +int variant_get_xhci_oc_map(uint16_t *map) +{ + *map = USB_OC_DISABLE_ALL; + *map &= ~(USB_OC_DISABLE << OC_PORT0_SHIFT); + *map |= USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0 = OC0 */ + *map &= ~(USB_OC_DISABLE << OC_PORT1_SHIFT); + *map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1 = OC1 */ + return 0; +} + +int variant_get_ehci_oc_map(uint16_t *map) +{ + *map = USB_OC_DISABLE_ALL; + *map &= ~(USB_OC_DISABLE << OC_PORT0_SHIFT); + *map |= USB_OC2 << OC_PORT0_SHIFT; /* USB-A Port0 = OC2 */ + return 0; +} diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/usb_oc.asl b/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/usb_oc.asl deleted file mode 100644 index 068d6fd..0000000 --- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/acpi/usb_oc.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* - * DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) - * { - * #include "usb.asl" - * } - */ - -/* USB overcurrent mapping pins. */ -Name (UOM0, 0) -Name (UOM1, 2) -Name (UOM2, 0) -Name (UOM3, 7) -Name (UOM4, 2) -Name (UOM5, 2) -Name (UOM6, 6) -Name (UOM7, 2) -Name (UOM8, 6) -Name (UOM9, 6) - -/* USB Overcurrent GPEs */ -- To view, visit https://review.coreboot.org/22679 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342 Gerrit-Change-Number: 22679 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Add XHCI PM register access functions
by Marc Jones (Code Review) 02 Dec '17

02 Dec '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22677 Change subject: soc/amd/stoneyridge: Add XHCI PM register access functions ...................................................................... soc/amd/stoneyridge: Add XHCI PM register access functions Add functions to access the XHCI PM MMIO registers. Change-Id: I81b4c0a448eb17c5ee0562a2c3548a074d533a98 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/22677/1 diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 53eb712..64a9b30 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -31,6 +31,7 @@ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 #define APU_SMI_BASE 0xfed80200 #define PM_MMIO_BASE 0xfed80300 +#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index d911472..f840fd9 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -312,6 +312,12 @@ void smi_write32(uint8_t offset, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); uint16_t pm_acpi_pm_evt_blk(void); +void xhci_pm_write8(uint8_t reg, uint8_t value); +uint8_t xhci_pm_read8(uint8_t reg); +void xhci_pm_write16(uint8_t reg, uint16_t value); +uint16_t xhci_pm_read16(uint8_t reg); +void xhci_pm_write32(uint8_t reg, uint32_t value); +uint32_t xhci_pm_read32(uint8_t reg); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); void bootblock_fch_early_init(void); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index f7c6b45..053e8dd 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -84,3 +84,32 @@ { return pm_read16(PM_EVT_BLK); } + +void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); +} + +uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); +} +void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); +} + +uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); +} + +void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); +} + +uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); +} -- To view, visit https://review.coreboot.org/22677 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I81b4c0a448eb17c5ee0562a2c3548a074d533a98 Gerrit-Change-Number: 22677 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v69_51
by build bot (Jenkins) (Code Review) 02 Dec '17

02 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22391 ) Change subject: vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v69_51 ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64009/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18858/ : SUCCESS -- To view, visit https://review.coreboot.org/22391 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5 Gerrit-Change-Number: 22391 Gerrit-PatchSet: 3 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Dec 2017 23:25:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Fix guarded code in ACPI ASL
by build bot (Jenkins) (Code Review) 02 Dec '17

02 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22634 ) Change subject: soc/amd/stoneyridge: Fix guarded code in ACPI ASL ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64008/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18857/ : SUCCESS -- To view, visit https://review.coreboot.org/22634 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I71c6acb235df9aa8642dca4c85d2bf604e244bf4 Gerrit-Change-Number: 22634 Gerrit-PatchSet: 7 Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Dec 2017 23:03:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Add RunOnAP support
by build bot (Jenkins) (Code Review) 01 Dec '17

01 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22194 ) Change subject: soc/amd/stoneyridge: Add RunOnAP support ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64007/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18856/ : SUCCESS -- To view, visit https://review.coreboot.org/22194 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id30cb2e0c6cc474158f3a7710dbb8ecf54f1ffe4 Gerrit-Change-Number: 22194 Gerrit-PatchSet: 7 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Dec 2017 22:22:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Create new name/IRQ association
by build bot (Jenkins) (Code Review) 01 Dec '17

01 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22667 ) Change subject: amd/stoneyridge: Create new name/IRQ association ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64006/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18855/ : SUCCESS -- To view, visit https://review.coreboot.org/22667 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d Gerrit-Change-Number: 22667 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Dec 2017 21:39:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/kahlee: Update Kconfig string used in makefiles
by build bot (Jenkins) (Code Review) 01 Dec '17

01 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22656 ) Change subject: mainboard/google/kahlee: Update Kconfig string used in makefiles ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64005/ : SUCCESS -- To view, visit https://review.coreboot.org/22656 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ieffabaae5516a893f1dc1f7195a17c4cdeae8853 Gerrit-Change-Number: 22656 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Dec 2017 21:22:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add support for D0 stepping
by build bot (Jenkins) (Code Review) 01 Dec '17

01 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22676 ) Change subject: soc/intel/cannonlake: Add support for D0 stepping ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64004/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18854/ : SUCCESS -- To view, visit https://review.coreboot.org/22676 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931 Gerrit-Change-Number: 22676 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Dec 2017 21:03:25 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add support for D0 stepping
by build bot (Jenkins) (Code Review) 01 Dec '17

01 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22676 ) Change subject: soc/intel/cannonlake: Add support for D0 stepping ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64003/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/18853/ : ABORTED -- To view, visit https://review.coreboot.org/22676 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931 Gerrit-Change-Number: 22676 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Dec 2017 20:56:18 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017