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Change in coreboot[master]: intel/dcp847ske: Add Intel NUC DCP847SKE
by build bot (Jenkins) (Code Review) 03 Dec '17

03 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22683 ) Change subject: intel/dcp847ske: Add Intel NUC DCP847SKE ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64022/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/18871/ : SUCCESS -- To view, visit https://review.coreboot.org/22683 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Gerrit-Change-Number: 22683 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Dec 2017 10:05:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/dcp847ske: Add Intel NUC DCP847SKE
by Tobias Diedrich (Code Review) 03 Dec '17

03 Dec '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22683 Change subject: intel/dcp847ske: Add Intel NUC DCP847SKE ...................................................................... intel/dcp847ske: Add Intel NUC DCP847SKE https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE Tested: - RAM slots with 2x4GB Kingston KVR1333D3S9/4G - SeaBIOS payload - Linux payload - Booting into Linux 4.13.14 with Debian/unstable installed on the internal mSATA slot. - Non-native raminit (works) - Native raminit (doesn't work with the given ram) - Native VGA init, HDMI port detection with libgfxinit - Basic ACPI functions (power button event; power-off; reboot) - Suspend to RAM and resume works - PCIe WLAN in half-minicard slot - USB device in half-minicard slot - PCIe device in full-minicard slot - mSATA device in full-minicard slot - Fan spins up/down in response to CPU load Known issues: - Native raminit fails timC calibration with the RAM I have - Technical Product Specification mentions overcurrent protection for back panel and front panel USB connectors, but I haven't been able to trigger it with either native fw or coreboot (tried up to 2.5A load). Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- A src/mainboard/intel/dcp847ske/Kconfig A src/mainboard/intel/dcp847ske/Kconfig.name A src/mainboard/intel/dcp847ske/Makefile.inc A src/mainboard/intel/dcp847ske/acpi/ec.asl A src/mainboard/intel/dcp847ske/acpi/platform.asl A src/mainboard/intel/dcp847ske/acpi/superio.asl A src/mainboard/intel/dcp847ske/acpi_tables.c A src/mainboard/intel/dcp847ske/board_info.txt A src/mainboard/intel/dcp847ske/devicetree.cb A src/mainboard/intel/dcp847ske/dsdt.asl A src/mainboard/intel/dcp847ske/early_southbridge.c A src/mainboard/intel/dcp847ske/gma-mainboard.ads A src/mainboard/intel/dcp847ske/gnvs.c A src/mainboard/intel/dcp847ske/gpio.c A src/mainboard/intel/dcp847ske/hda_verb.c A src/mainboard/intel/dcp847ske/mainboard.c A src/mainboard/intel/dcp847ske/romstage.c A src/mainboard/intel/dcp847ske/smihandler.c A src/mainboard/intel/dcp847ske/superio.h A src/mainboard/intel/dcp847ske/thermal.h A src/mainboard/intel/dcp847ske/usb.h A src/southbridge/intel/bd82x6x/acpi/gbe.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl 23 files changed, 1,076 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/22683/1 diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig new file mode 100644 index 0000000..6c99bc4 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -0,0 +1,94 @@ +if BOARD_INTEL_DCP847SKE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_RPGA989 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select SERIRQ_CONTINUOUS_MODE + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + +menu "Debugging" + +config ENABLE_UART_ON_TESTPADS + bool "Enable UART on testpads" + default n + help + Serial output requires soldering to the testpad next to + NCT5577D pin 18 (txd) and gnd. + +endmenu + +config NO_UART_ON_SUPERIO + def_bool y + depends on !ENABLE_UART_ON_TESTPADS + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default intel/dcp847ske + +config MAINBOARD_PART_NUMBER + string + default "Intel NUC DCP847SKE" + +config VGA_BIOS_FILE + string + default "pci8086,0106.rom" + +config VGA_BIOS_ID + string + default "8086,0106" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2044 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config MAX_CPUS + int + default 2 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config IFD_GBE_SECTION + string + default "0x00001000:0x00002fff" + +config IFD_ME_SECTION + string + default "0x00003000:0x001bffff" + +config IFD_BIOS_SECTION + string + default "0x001c0000:0x007fffff" + +config CBFS_SIZE + hex + default 0x00640000 + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Intel Corporation" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + string + default "DCP847SKE" + +endif # BOARD_INTEL_DCP847SKE diff --git a/src/mainboard/intel/dcp847ske/Kconfig.name b/src/mainboard/intel/dcp847ske/Kconfig.name new file mode 100644 index 0000000..e55b90d --- /dev/null +++ b/src/mainboard/intel/dcp847ske/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_DCP847SKE + bool "Intel NUC DCP847SKE" diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc new file mode 100644 index 0000000..4435806 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -0,0 +1,5 @@ +romstage-y += early_southbridge.c +romstage-y += gpio.c +ramstage-y += gnvs.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/mainboard/intel/dcp847ske/acpi/ec.asl b/src/mainboard/intel/dcp847ske/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/acpi/ec.asl diff --git a/src/mainboard/intel/dcp847ske/acpi/platform.asl b/src/mainboard/intel/dcp847ske/acpi/platform.asl new file mode 100644 index 0000000..ff5b176 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +/* The _WAK method is called on system wakeup */ +Method(_PTS,1) +{ +} diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/acpi_tables.c @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/dcp847ske/board_info.txt b/src/mainboard/intel/dcp847ske/board_info.txt new file mode 100644 index 0000000..32d4eba --- /dev/null +++ b/src/mainboard/intel/dcp847ske/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb new file mode 100644 index 0000000..6bc2ed5 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -0,0 +1,67 @@ +chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + # Enable DisplayPort 1 Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable DisplayPort 0 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable DVI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" + + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" + end + end + device domain 0x0 on + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 (unused) + device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA) + device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe) + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl new file mode 100644 index 0000000..f637648 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c new file mode 100644 index 0000000..9dcba5d --- /dev/null +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -0,0 +1,199 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +#include "superio.h" +#include "thermal.h" + +#if IS_ENABLED(CONFIG_ENABLE_UART_ON_TESTPADS) +#define DEBUG_UART_EN COMA_LPC_EN +#else +#define DEBUG_UART_EN 0 +#endif + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF2_LPC_EN | DEBUG_UART_EN); + /* Decode SuperIO 0x0a00 */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01); +} + +void rcba_config(void) +{ + /* Disable devices */ + RCBA32(FD) |= PCH_DISABLE_ALWAYS | PCH_DISABLE_P2P | PCH_DISABLE_XHCI; + +#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) + /* Enable Gigabit Ethernet */ + if (RCBA32(BUC) & PCH_DISABLE_GBE) { + RCBA32(BUC) &= ~PCH_DISABLE_GBE; + /* Datasheet says clearing the bit requires a reset after */ + printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n"); + outb(0xe, 0xcf9); + halt(); + } +#endif + + /* Set "mobile" bit in MCH (which makes sense layout-wise). */ + /* Note sure if this has any effect at all though. */ + MCHBAR32(0x0004) |= 0x00001000; + MCHBAR32(0x0104) |= 0x00001000; +} + +void mainboard_early_init(int s3resume) +{ +} + +static const u16 hwm_initvals[] = { + HWM_BANK(0), + HWM_INITVAL(0xae, 0x01), /* Enable PECI Agent0 */ + + HWM_BANK(7), /* PECI */ + HWM_INITVAL(0x01, 0x95), /* Enable PECI */ + HWM_INITVAL(0x03, 0x10), /* Enable Agent 0 */ + HWM_INITVAL(0x09, 0x64), /* Tbase0 */ + + HWM_BANK(2), /* CPUFAN control */ + HWM_INITVAL(0x00, 0x0c), /* PECI Agent 0 as CPUFAN monitoring source */ + HWM_INITVAL(0x01, 50), /* Target temperature */ + HWM_INITVAL(0x02, 0x40), /* Enable Smart Fan IV mode */ + HWM_INITVAL(0x03, 0x01), /* Step-up time */ + HWM_INITVAL(0x04, 0x01), /* Step-down time */ + HWM_INITVAL(0x05, 0x10), /* Stop PWM value */ + HWM_INITVAL(0x06, 0x20), /* Start PWM value */ + HWM_INITVAL(0x21, 45), /* Smart Fan IV Temp1 */ + HWM_INITVAL(0x22, 46), /* Smart Fan IV Temp2 */ + HWM_INITVAL(0x23, 47), /* Smart Fan IV Temp3 */ + HWM_INITVAL(0x24, PASSIVE_TEMPERATURE), /* Smart Fan IV Temp4 */ + HWM_INITVAL(0x27, 0x01), /* Smart Fan IV PWM1 */ + HWM_INITVAL(0x28, 0x02), /* Smart Fan IV PWM2 */ + HWM_INITVAL(0x29, 0x03), /* Smart Fan IV PWM3 */ + HWM_INITVAL(0x2a, 0xff), /* Smart Fan IV PWM4 */ + /* Smart Fan IV Critical temp */ + HWM_INITVAL(0x35, CRITICAL_TEMPERATURE), + HWM_INITVAL(0x38, 3), /* Smart Fan IV Critical temp tolerance */ + HWM_INITVAL(0x39, 0x81), /* Enable SYSTIN weight value */ + HWM_INITVAL(0x3a, 1), /* SYSTIN temperature step */ + HWM_INITVAL(0x3b, 2), /* SYSTIN step tolerance */ + HWM_INITVAL(0x3c, 1), /* SYSTIN weight step */ + HWM_INITVAL(0x3d, 40), /* SYSTIN temperature base */ + HWM_INITVAL(0x3e, 0x00), /* SYSTIN fan duty base */ + + HWM_BANK(0), +}; + +static void hwm_init(void) +{ + /* Set up fan control */ + for (int i = 0; i < ARRAY_SIZE(hwm_initvals); i++) + HWM_WRITE_INITVAL(hwm_initvals[i]); +} + +static const u16 superio_initvals[] = { + /* Global config registers */ + SUPERIO_INITVAL(0x1a, 0x02), + SUPERIO_INITVAL(0x1b, 0x6a), + SUPERIO_INITVAL(0x27, 0x80), +#if IS_ENABLED(CONFIG_ENABLE_UART_ON_TESTPADS) + SUPERIO_INITVAL(0x2a, 0x00), +#else + SUPERIO_INITVAL(0x2a, 0x80), +#endif + SUPERIO_INITVAL(0x2c, 0x00), + + SUPERIO_BANK(2), /* UART A */ + SUPERIO_INITVAL(0x30, 0x01), + SUPERIO_INITVAL(0x60, 0x03), + SUPERIO_INITVAL(0x61, 0xf8), + SUPERIO_INITVAL(0x70, 0x04), + + SUPERIO_BANK(7), /* GPIO config */ + SUPERIO_INITVAL(0x30, 0x01), + SUPERIO_INITVAL(0xe0, 0xcf), + SUPERIO_INITVAL(0xe1, 0x0f), + SUPERIO_INITVAL(0xe4, 0xed), + SUPERIO_INITVAL(0xe5, 0x4d), + SUPERIO_INITVAL(0xec, 0x30), + SUPERIO_INITVAL(0xee, 0xff), + + SUPERIO_BANK(8), + SUPERIO_INITVAL(0x30, 0x06), + SUPERIO_INITVAL(0x60, GPIO_PORT >> 8), + SUPERIO_INITVAL(0x61, GPIO_PORT & 0xff), + + SUPERIO_BANK(9), + SUPERIO_INITVAL(0x30, 0x8c), + SUPERIO_INITVAL(0xe1, 0x90), + + SUPERIO_BANK(0xa), + SUPERIO_INITVAL(0xe4, 0x20), + SUPERIO_INITVAL(0xe6, 0x4c), + + SUPERIO_BANK(0xb), /* HWM & LED */ + SUPERIO_INITVAL(0x30, 0x01), + SUPERIO_INITVAL(0x60, HWM_PORT >> 8), + SUPERIO_INITVAL(0x61, HWM_PORT & 0xff), + SUPERIO_INITVAL(0xf7, 0x67), + SUPERIO_INITVAL(0xf8, 0x60), + + SUPERIO_BANK(0x16), + SUPERIO_INITVAL(0x30, 0x00), +}; + +static void superio_init(void) +{ + SUPERIO_UNLOCK; + for (int i = 0; i < ARRAY_SIZE(superio_initvals); i++) + SUPERIO_WRITE_INITVAL(superio_initvals[i]); + SUPERIO_LOCK; +} + +void mainboard_config_superio(void) +{ + superio_init(); + hwm_init(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { +#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin } +#include "usb.h" +}; diff --git a/src/mainboard/intel/dcp847ske/gma-mainboard.ads b/src/mainboard/intel/dcp847ske/gma-mainboard.ads new file mode 100644 index 0000000..493051e --- /dev/null +++ b/src/mainboard/intel/dcp847ske/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; version 2 of +-- the License. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/intel/dcp847ske/gnvs.c b/src/mainboard/intel/dcp847ske/gnvs.c new file mode 100644 index 0000000..e92c421 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/gnvs.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // No LID: open by default. + gnvs->lids = 1; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} diff --git a/src/mainboard/intel/dcp847ske/gpio.c b/src/mainboard/intel/dcp847ske/gpio.c new file mode 100644 index 0000000..50da50e --- /dev/null +++ b/src/mainboard/intel/dcp847ske/gpio.c @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, /* BIOS jumper: 1 = normal, 0 = setup */ + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +/* + * GPIO8: HIGH crashes kernel, maybe selects 1.35V for RAM + * GPIO27: Set to HIGH on S3/S4/S5 by original fw dsdt. + * GPIO29: Actually NATIVE? Can't clear, stays 1. + * SLP_LAN# is affected by soft-strap according to docs. + * Others: No visible effect when toggling. + */ +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, /* mSATA presence detect */ + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio66 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/intel/dcp847ske/hda_verb.c b/src/mainboard/intel/dcp847ske/hda_verb.c new file mode 100644 index 0000000..b000347 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/intel/dcp847ske/mainboard.c b/src/mainboard/intel/dcp847ske/mainboard.c new file mode 100644 index 0000000..96e6e54 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/mainboard.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <smbios.h> + +static void mainboard_enable(device_t dev) +{ + printk(BIOS_DEBUG, "BIOS_CFG jumper: %s\n", + get_gpio(22) ? "normal (1-2)" : "setup (2-3)"); + printk(BIOS_DEBUG, "mSATA: %s\n", + get_gpio(35) ? "present" : "absent"); + + install_intel_vga_int15_handler( + GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c new file mode 100644 index 0000000..57d71c6 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> + +#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pei_data_template = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 0, + .gbe_enable = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1333, + .usb_port_config = { +#define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current } +#include "usb.h" + }, + }; + *pei_data = pei_data_template; +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} +#endif diff --git a/src/mainboard/intel/dcp847ske/smihandler.c b/src/mainboard/intel/dcp847ske/smihandler.c new file mode 100644 index 0000000..8bd5c1c --- /dev/null +++ b/src/mainboard/intel/dcp847ske/smihandler.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <device/pnp.h> +#include <ec/acpi/ec.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/nuvoton/common/nuvoton.h> + +#include "superio.h" + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ != 0) { + /* Enable GRN_LED [Power LED] fading */ + SUPERIO_UNLOCK; + SUPERIO_WRITE(0xf7, 0x68); + SUPERIO_LOCK; + } +} diff --git a/src/mainboard/intel/dcp847ske/superio.h b/src/mainboard/intel/dcp847ske/superio.h new file mode 100644 index 0000000..841353d --- /dev/null +++ b/src/mainboard/intel/dcp847ske/superio.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DCP847SKE_SUPERIO_H +#define DCP847SKE_SUPERIO_H + +#define NUVOTON_PORT 0x4e +#define HWM_PORT 0x0a30 +#define GPIO_PORT 0x0a80 + +#define SUPERIO_BANK(x) (0x0700 | x) +#define SUPERIO_INITVAL(reg, data) ((reg << 8) | (data)) +#define HWM_BANK(x) (0x4e00 | x) +#define HWM_INITVAL SUPERIO_INITVAL + +#define SUPERIO_UNLOCK do { \ + outb(0x87, NUVOTON_PORT); \ + outb(0x87, NUVOTON_PORT); \ +} while (0) + +#define SUPERIO_LOCK do { \ + outb(0xaa, NUVOTON_PORT); \ +} while (0) + +#define SUPERIO_WRITE(reg, data) do { \ + outb((reg), NUVOTON_PORT); \ + outb((data), NUVOTON_PORT + 1); \ +} while (0) + +#define SUPERIO_WRITE_INITVAL(val) SUPERIO_WRITE((val) >> 8, (val) & 0xff) + +#define HWM_WRITE(reg, data) do { \ + outb((reg), HWM_PORT + 5); \ + outb((data), HWM_PORT + 6); \ +} while (0) + +#define HWM_WRITE_INITVAL(val) HWM_WRITE((val) >> 8, (val) & 0xff) + +#endif /* DCP847SKE_SUPERIO_H */ diff --git a/src/mainboard/intel/dcp847ske/thermal.h b/src/mainboard/intel/dcp847ske/thermal.h new file mode 100644 index 0000000..e60daaa --- /dev/null +++ b/src/mainboard/intel/dcp847ske/thermal.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DCP847SKE_THERMAL_H +#define DPC847SKE_THERMAL_H + +/* TODO: These should be generated at runtime from + * MSR_IA32_TEMPERATURE_TARGET (0x1a2) */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 86 + +#endif diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h new file mode 100644 index 0000000..c6a5295 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/usb.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DCP847SKE_USB_H +#define DPC847SKE_USB_H + +USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */ +USB_CONFIG(1, 1, 0), /* back, towards power plug */ +USB_CONFIG(1, 1, 1), /* half-width miniPCIe */ +USB_CONFIG(1, 1, 1), /* full-width miniPCIe */ +USB_CONFIG(1, 1, 2), /* front-panel header */ +USB_CONFIG(1, 1, 2), /* front-panel header */ +USB_CONFIG(1, 1, 3), /* front connector */ +USB_CONFIG(0, 1, 3), /* not available */ +USB_CONFIG(0, 1, 4), /* not available */ +USB_CONFIG(0, 1, 4), /* not available */ +USB_CONFIG(0, 1, 5), /* not available */ +USB_CONFIG(0, 1, 5), /* not available */ +USB_CONFIG(0, 1, 6), /* not available */ +USB_CONFIG(0, 1, 6), /* not available */ + +#endif diff --git a/src/southbridge/intel/bd82x6x/acpi/gbe.asl b/src/southbridge/intel/bd82x6x/acpi/gbe.asl new file mode 100644 index 0000000..e0a2460 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/acpi/gbe.asl @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2017 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel PCH Gigabit Ethernet 0:19.0 */ + +Device (GLAN) +{ + Name (_ADR, 0x00190000) + + // Power Resources for Wake + Name (_PRW, Package(){ + 13, // Bit 13 of GPE + 4 // Can wake from S4 state. + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + * Arg3 - Function Arg + */ + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + // Device label GUID, used by systemd for naming. + If (Arg0 == ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D")) + { + Switch (ToInteger(Arg2)) { + // Function 0 (Report supported functions) + Case (0) { + // Supports functions 7 & 0 + Return (Buffer() { 0x81 }) + } + // Function 7 (DEVICE_LABEL_DSM) + Case (7) { + Return (Package(){ + 1, // Instance number + "LAN", // Optional name + }) + } + } + } + + // No functions supported for the given GUID + Return (Buffer() { 0 }) + } +} diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index cfa27d2..7d8d5df 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -234,6 +234,9 @@ } } +// Gigabit Ethernet 0:19.0 +#include "gbe.asl" + // High Definition Audio (Azalia) 0:1b.0 #include "audio.asl" -- To view, visit https://review.coreboot.org/22683 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Gerrit-Change-Number: 22683 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: mb/hp/8460p: Add TPM support
by build bot (Jenkins) (Code Review) 03 Dec '17

03 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22602 ) Change subject: mb/hp/8460p: Add TPM support ...................................................................... Patch Set 14: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64021/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18870/ : SUCCESS -- To view, visit https://review.coreboot.org/22602 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3b845928954d203d1c3608b6704fedbd590e1fa9 Gerrit-Change-Number: 22602 Gerrit-PatchSet: 14 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Dec 2017 01:45:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] mb/dell/inspiron_660s: Initial working port
by build bot (Jenkins) (Code Review) 02 Dec '17

02 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22682 ) Change subject: [WIP] mb/dell/inspiron_660s: Initial working port ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64020/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/18869/ : SUCCESS -- To view, visit https://review.coreboot.org/22682 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8dabb1e1d14e60957e8c8800b0c30921d6bb5d8e Gerrit-Change-Number: 22682 Gerrit-PatchSet: 1 Gerrit-Owner: Jean Lucas <jean(a)4ray.co> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Dec 2017 22:09:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] mb/dell/inspiron_660s: Initial working port
by Jean Lucas (Code Review) 02 Dec '17

02 Dec '17

Jean Lucas has uploaded this change for review. ( https://review.coreboot.org/22682 Change subject: [WIP] mb/dell/inspiron_660s: Initial working port ...................................................................... [WIP] mb/dell/inspiron_660s: Initial working port System is quite functional with state of port. libgfxinit gives more consistent graphics initialization than Intel's VGA BIOS; however, both options present graphics corruption during GRUB's graphical console (Intel's VGA BIOS), or immediately after menu selection (libgfxinit). Graphics work fine with either option once Linux takes over. Tested components: * VGA * HDMI (not working during boot with libgfxinit) * USB 2/3 * NICs (onboard and PCIe) * S3 and resume * Onboard audio * SD card reader Other notes: * "mce: [Hardware Error]: Machine check events logged" with Linux * PCIe discrete graphics untested cbmem and mce logs are in the board "logs" directory. Change-Id: I8dabb1e1d14e60957e8c8800b0c30921d6bb5d8e Signed-off-by: Jean Lucas <jean(a)4ray.co> --- A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/inspiron_660s/Kconfig A src/mainboard/dell/inspiron_660s/Kconfig.name A src/mainboard/dell/inspiron_660s/Makefile.inc A src/mainboard/dell/inspiron_660s/acpi/ec.asl A src/mainboard/dell/inspiron_660s/acpi/mainboard.asl A src/mainboard/dell/inspiron_660s/acpi/platform.asl A src/mainboard/dell/inspiron_660s/acpi/superio.asl A src/mainboard/dell/inspiron_660s/acpi/thermal.asl A src/mainboard/dell/inspiron_660s/acpi_tables.c A src/mainboard/dell/inspiron_660s/board_info.txt A src/mainboard/dell/inspiron_660s/cmos.default A src/mainboard/dell/inspiron_660s/cmos.layout A src/mainboard/dell/inspiron_660s/devicetree.cb A src/mainboard/dell/inspiron_660s/dsdt.asl A src/mainboard/dell/inspiron_660s/early_southbridge.c A src/mainboard/dell/inspiron_660s/gma-mainboard.ads A src/mainboard/dell/inspiron_660s/gnvs.c A src/mainboard/dell/inspiron_660s/gpio.c A src/mainboard/dell/inspiron_660s/hda_verb.c A src/mainboard/dell/inspiron_660s/logs/cbmem A src/mainboard/dell/inspiron_660s/logs/mce A src/mainboard/dell/inspiron_660s/mainboard.c A src/mainboard/dell/inspiron_660s/romstage.c 25 files changed, 2,328 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22682/1 diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig new file mode 100644 index 0000000..c12e54a --- /dev/null +++ b/src/mainboard/dell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_DELL + +choice + prompt "Mainboard model" + +source "src/mainboard/dell/*/Kconfig.name" + +endchoice + +source "src/mainboard/dell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Dell" + +endif # VENDOR_DELL diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name new file mode 100644 index 0000000..8a508ea --- /dev/null +++ b/src/mainboard/dell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_DELL + bool "Dell" diff --git a/src/mainboard/dell/inspiron_660s/Kconfig b/src/mainboard/dell/inspiron_660s/Kconfig new file mode 100644 index 0000000..5cb94af --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/Kconfig @@ -0,0 +1,63 @@ +if BOARD_DELL_INSPIRON_660S + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_LGA1155 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select SUPERIO_ITE_IT8772F + select BOARD_ROMSIZE_KB_8192 + select SERIRQ_CONTINUOUS_MODE + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_INT15 + select SANDYBRIDGE_IVYBRIDGE_LVDS + select MAINBOARD_HAS_LIBGFXINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default dell/inspiron_660s + +config MAINBOARD_PART_NUMBER + string + default "Inspiron 660s" + +config VGA_BIOS_FILE + string + default "pci8086,0152.rom" + +config VGA_BIOS_ID + string + default "8086,0152" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x574 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1028 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/dell/inspiron_660s/Kconfig.name b/src/mainboard/dell/inspiron_660s/Kconfig.name new file mode 100644 index 0000000..e3828bb --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_INSPIRON_660S + bool "Inspiron 660s" diff --git a/src/mainboard/dell/inspiron_660s/Makefile.inc b/src/mainboard/dell/inspiron_660s/Makefile.inc new file mode 100644 index 0000000..cd0b8a6 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/Makefile.inc @@ -0,0 +1,4 @@ +romstage-y += early_southbridge.c +romstage-y += gpio.c +ramstage-y += gnvs.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/inspiron_660s/acpi/ec.asl b/src/mainboard/dell/inspiron_660s/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/acpi/ec.asl diff --git a/src/mainboard/dell/inspiron_660s/acpi/mainboard.asl b/src/mainboard/dell/inspiron_660s/acpi/mainboard.asl new file mode 100644 index 0000000..34de86f --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/acpi/mainboard.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/dell/inspiron_660s/acpi/platform.asl b/src/mainboard/dell/inspiron_660s/acpi/platform.asl new file mode 100644 index 0000000..0222986 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/dell/inspiron_660s/acpi/superio.asl b/src/mainboard/dell/inspiron_660s/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/acpi/superio.asl diff --git a/src/mainboard/dell/inspiron_660s/acpi/thermal.asl b/src/mainboard/dell/inspiron_660s/acpi/thermal.asl new file mode 100644 index 0000000..c2bc80c --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/acpi/thermal.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/dell/inspiron_660s/acpi_tables.c b/src/mainboard/dell/inspiron_660s/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/acpi_tables.c diff --git a/src/mainboard/dell/inspiron_660s/board_info.txt b/src/mainboard/dell/inspiron_660s/board_info.txt new file mode 100644 index 0000000..aec4932 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: http://www.dell.com/en-us/shop/cty/inspiron-660s-desktop/spd/inspiron-660s +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/dell/inspiron_660s/cmos.default b/src/mainboard/dell/inspiron_660s/cmos.default new file mode 100644 index 0000000..a313f68 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +sata_mode=AHCI +hyper_threading=Enable diff --git a/src/mainboard/dell/inspiron_660s/cmos.layout b/src/mainboard/dell/inspiron_660s/cmos.layout new file mode 100644 index 0000000..e27b4a2 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/cmos.layout @@ -0,0 +1,117 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/dell/inspiron_660s/devicetree.cb b/src/mainboard/dell/inspiron_660s/devicetree.cb new file mode 100644 index 0000000..aeb12cc --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/devicetree.cb @@ -0,0 +1,115 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/socket_LGA1155 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + # Magic APID ID to locate this chip + device lapic 0xacac off + end + end + end + + register "pci_mmio_size" = "2048" + + # IGD display + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.ndid" = "3" + + device domain 0x0 on + device pci 00.0 on # Host bridge + subsystemid 0x1028 0x0574 + end + device pci 01.0 on # PCIe bridge for discrete graphics + subsystemid 0x1028 0x0574 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1028 0x0574 + end + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1028 0x0574 + end + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1028 0x0574 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1028 0x0574 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1028 0x0574 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x1028 0x0574 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x1028 0x0574 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x1028 0x0574 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1028 0x0574 + end + device pci 1e.0 on # PCI bridge + subsystemid 0x1028 0x0574 + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1028 0x0574 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1028 0x0574 + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x0574 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/dell/inspiron_660s/dsdt.asl b/src/mainboard/dell/inspiron_660s/dsdt.asl new file mode 100644 index 0000000..3b7fb7e --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/dell/inspiron_660s/early_southbridge.c b/src/mainboard/dell/inspiron_660s/early_southbridge.c new file mode 100644 index 0000000..a7e289d --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/early_southbridge.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1400); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x003c0a01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void rcba_config(void) +{ + /* Disable devices. */ + RCBA32(0x3414) = 0x00000020; + RCBA32(0x3418) = 0x17d81fe1; + +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/dell/inspiron_660s/gma-mainboard.ads b/src/mainboard/dell/inspiron_660s/gma-mainboard.ads new file mode 100644 index 0000000..fe0ff75 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/gma-mainboard.ads @@ -0,0 +1,15 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/inspiron_660s/gnvs.c b/src/mainboard/dell/inspiron_660s/gnvs.c new file mode 100644 index 0000000..7aecacb --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/gnvs.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + // Disable USB ports in S3 by default + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + // Disable USB ports in S5 by default + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // Lid is open by default + gnvs->lids = 1; + + // Critical temperature + gnvs->tcrt = 100; + + // Passive cooling activation temperature + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/inspiron_660s/gpio.c b/src/mainboard/dell/inspiron_660s/gpio.c new file mode 100644 index 0000000..724b5e2 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/gpio.c @@ -0,0 +1,252 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, + .gpio9 = GPIO_RESET_RSMRST, + .gpio10 = GPIO_RESET_RSMRST, + .gpio11 = GPIO_RESET_RSMRST, + .gpio12 = GPIO_RESET_RSMRST, + .gpio13 = GPIO_RESET_RSMRST, + .gpio14 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, + .gpio24 = GPIO_RESET_RSMRST, + .gpio27 = GPIO_RESET_RSMRST, + .gpio28 = GPIO_RESET_RSMRST, + .gpio29 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, + .gpio31 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio40 = GPIO_RESET_RSMRST, + .gpio41 = GPIO_RESET_RSMRST, + .gpio42 = GPIO_RESET_RSMRST, + .gpio43 = GPIO_RESET_RSMRST, + .gpio44 = GPIO_RESET_RSMRST, + .gpio45 = GPIO_RESET_RSMRST, + .gpio46 = GPIO_RESET_RSMRST, + .gpio57 = GPIO_RESET_RSMRST, + .gpio58 = GPIO_RESET_RSMRST, + .gpio59 = GPIO_RESET_RSMRST, + .gpio60 = GPIO_RESET_RSMRST, + .gpio61 = GPIO_RESET_RSMRST, + .gpio62 = GPIO_RESET_RSMRST, + .gpio63 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio72 = GPIO_RESET_RSMRST, + .gpio74 = GPIO_RESET_RSMRST, + .gpio75 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/inspiron_660s/hda_verb.c b/src/mainboard/dell/inspiron_660s/hda_verb.c new file mode 100644 index 0000000..0f48730 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/hda_verb.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek */ + 0x10280574, /* Subsystem ID */ + + 0x0000000c, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x10280574), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014010), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x02a19820), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x01a19c21), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181342f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x0221401f), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x411111f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x10280574, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x10280574), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/inspiron_660s/logs/cbmem b/src/mainboard/dell/inspiron_660s/logs/cbmem new file mode 100644 index 0000000..5f719b8 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/logs/cbmem @@ -0,0 +1,1367 @@ +Looking for coreboot table at 0 4096 bytes. +Mapping 4096B of physical memory at 0x0 (requested 0x0). +Mapping 1320B of physical memory at 0x0 (requested 0x518). + ... padding virtual address with 0x518 bytes. +Found! + coreboot table entry 0x11 + Found forwarding entry. +Looking for coreboot table at 7fe9e000 4096 bytes. +Mapping 4096B of physical memory at 0x7fe9e000 (requested 0x7fe9e000). +Mapping 2196B of physical memory at 0x7fe9e000 (requested 0x7fe9e018). + ... padding virtual address with 0x18 bytes. +Found! + coreboot table entry 0xc8 + coreboot table entry 0xcc + coreboot table entry 0x01 + Found memory map. + LB_MEM_TABLE found. + LB_MEM_TABLE found. + coreboot table entry 0x03 + coreboot table entry 0x04 + coreboot table entry 0x05 + coreboot table entry 0x06 + coreboot table entry 0x07 + coreboot table entry 0x26 + coreboot table entry 0x12 + coreboot table entry 0x29 + coreboot table entry 0x16 + Found timestamp table. + cbmem_addr = 7ffdd000 + coreboot table entry 0x17 + Found cbmem console. + cbmem_addr = 7ffde000 + coreboot table entry 0x24 + coreboot table entry 0x30 + coreboot table entry 0x32 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 + coreboot table entry 0x31 +Mapping 8B of physical memory at 0x7ffde000 (requested 0x7ffde000). +Mapping 131072B of physical memory at 0x7ffde000 (requested 0x7ffde000). +*** Pre-CBMEM romstage console overflowed, log truncated! *** +ked entry 0 from cache block +Trying stored timings. +Starting Ivybridge RAM training (1). +100MHz reference clock support: yes +Trying CAS 10, tCK 320. +Found compatible clock, CAS pair. +Selected DRAM frequency: 800 MHz +Selected CAS latency : 10T +PLL busy... done in 70 us +MCU frequency is set at : 800 MHz +Done dimm mapping +Update PCI-E configuration space: +PCI(0, 0, 0)[a0] = 0 +PCI(0, 0, 0)[a4] = 4 +PCI(0, 0, 0)[bc] = 82a00000 +PCI(0, 0, 0)[a8] = 7d600000 +PCI(0, 0, 0)[ac] = 4 +PCI(0, 0, 0)[b8] = 80000000 +PCI(0, 0, 0)[b0] = 80a00000 +PCI(0, 0, 0)[b4] = 80800000 +Done memory map +Done io registers +t123: 1767, 6000, 7620 +ME: FW Partition Table : OK +ME: Bringup Loader Failure : NO +ME: Firmware Init Complete : NO +ME: Manufacturing Mode : YES +ME: Boot Options Present : NO +ME: Update In Progress : NO +ME: Current Working State : Initializing +ME: Current Operation State : Bring up +ME: Current Operation Mode : Security Override via Jumper +ME: Error Code : No Error +ME: Progress Phase : BUP Phase +ME: Power Management Event : Clean Moff->Mx wake +ME: Progress Phase State : Check to see if straps say ME DISABLED +ME: Wrong mode : 4 +ME: FWS2: 0x100a0140 +ME: Bist in progress: 0x0 +ME: ICC Status : 0x0 +ME: Invoke MEBx : 0x0 +ME: CPU replaced : 0x0 +ME: MBP ready : 0x0 +ME: MFS failure : 0x1 +ME: Warm reset req : 0x0 +ME: CPU repl valid : 0x1 +ME: (Reserved) : 0x0 +ME: FW update req : 0x0 +ME: (Reserved) : 0x0 +ME: Current state : 0xa +ME: Current PM event: 0x0 +ME: Progress code : 0x1 +PASSED! Tell ME that DRAM is ready +ME: FWS2: 0x100a0140 +ME: Bist in progress: 0x0 +ME: ICC Status : 0x0 +ME: Invoke MEBx : 0x0 +ME: CPU replaced : 0x0 +ME: MBP ready : 0x0 +ME: MFS failure : 0x1 +ME: Warm reset req : 0x0 +ME: CPU repl valid : 0x1 +ME: (Reserved) : 0x0 +ME: FW update req : 0x0 +ME: (Reserved) : 0x0 +ME: Current state : 0xa +ME: Current PM event: 0x0 +ME: Progress code : 0x1 +ME: Requested BIOS Action: Continue to boot +ME: FW Partition Table : OK +ME: Bringup Loader Failure : NO +ME: Firmware Init Complete : NO +ME: Manufacturing Mode : YES +ME: Boot Options Present : NO +ME: Update In Progress : NO +ME: Current Working State : Initializing +ME: Current Operation State : Bring up +ME: Current Operation Mode : Security Override via Jumper +ME: Error Code : No Error +ME: Progress Phase : BUP Phase +ME: Power Management Event : Clean Moff->Mx wake +ME: Progress Phase State : Check to see if straps say ME DISABLED +memcfg DDR3 ref clock 133 MHz +memcfg DDR3 clock 1596 MHz +memcfg channel assignment: A: 0, B 1, C 2 +memcfg channel[0] config (00620020): + ECC inactive + enhanced interleave mode on + rank interleave on + DIMMA 8192 MB width x8 dual rank, selected + DIMMB 0 MB width x8 single rank +memcfg channel[1] config (00620020): + ECC inactive + enhanced interleave mode on + rank interleave on + DIMMA 8192 MB width x8 dual rank, selected + DIMMB 0 MB width x8 single rank +CBMEM entry for DIMM info: 0x7fffe960 +MTRR Range: Start=ff800000 End=0 (Size 800000) +MTRR Range: Start=0 End=1000000 (Size 1000000) +MTRR Range: Start=7f800000 End=80000000 (Size 800000) +MTRR Range: Start=80000000 End=80800000 (Size 800000) +Jumping to image. + + +coreboot-4.6-2209-g3fbef82ca0-dirty Sat Dec 2 16:19:00 UTC 2017 ramstage starting... +S3 Resume. +BS: BS_PRE_DEVICE times (us): entry 8 run 0 exit 0 +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 0 exit 0 +Enumerating buses... +Show all devs... Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +APIC: acac: enabled 0 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:14.0: enabled 1 +PCI: 00:16.0: enabled 0 +PCI: 00:16.1: enabled 0 +PCI: 00:16.2: enabled 0 +PCI: 00:16.3: enabled 0 +PCI: 00:19.0: enabled 0 +PCI: 00:1a.0: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 0 +PCI: 00:1c.4: enabled 0 +PCI: 00:1c.5: enabled 1 +PCI: 00:1c.6: enabled 0 +PCI: 00:1c.7: enabled 0 +PCI: 00:1d.0: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 00:1f.0: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +PCI: 00:1f.5: enabled 0 +PCI: 00:1f.6: enabled 0 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + APIC: acac: enabled 0 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:01.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:14.0: enabled 1 + PCI: 00:16.0: enabled 0 + PCI: 00:16.1: enabled 0 + PCI: 00:16.2: enabled 0 + PCI: 00:16.3: enabled 0 + PCI: 00:19.0: enabled 0 + PCI: 00:1a.0: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1c.2: enabled 1 + PCI: 00:1c.3: enabled 0 + PCI: 00:1c.4: enabled 0 + PCI: 00:1c.5: enabled 1 + PCI: 00:1c.6: enabled 0 + PCI: 00:1c.7: enabled 0 + PCI: 00:1d.0: enabled 1 + PCI: 00:1e.0: enabled 1 + PCI: 00:1f.0: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + PCI: 00:1f.5: enabled 0 + PCI: 00:1f.6: enabled 0 +Root Device scanning... +root_dev_scan_bus for Root Device +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/0150] ops +PCI: 00:00.0 [8086/0150] enabled +Capability: type 0x0d @ 0x88 +Capability: type 0x01 @ 0x80 +Capability: type 0x05 @ 0x90 +Capability: type 0x10 @ 0xa0 +Capability: type 0x0d @ 0x88 +Capability: type 0x01 @ 0x80 +Capability: type 0x05 @ 0x90 +Capability: type 0x10 @ 0xa0 +PCI: 00:01.0 subordinate bus PCI Express +PCI: 00:01.0 [8086/0151] enabled +PCI: 00:02.0 [8086/0000] ops +PCI: 00:02.0 [8086/0152] enabled +PCI: 00:14.0 [8086/0000] ops +PCI: 00:14.0 [8086/1e31] enabled +PCI: 00:16.0: Disabling device +PCI: 00:16.0 [8086/1e3a] ops +PCI: 00:16.0 [8086/1e3a] disabled +PCI: 00:16.1: Disabling device +PCI: 00:16.2: Disabling device +PCI: 00:16.3: Disabling device +PCI: 00:19.0: Disabling device +PCI: 00:1a.0 [8086/0000] ops +PCI: 00:1a.0 [8086/1e2d] enabled +PCI: 00:1b.0 [8086/0000] ops +PCI: 00:1b.0 [8086/1e20] enabled +PCH: PCIe Root Port coalescing is enabled +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/1e10] enabled +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/1e12] enabled +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/1e14] enabled +PCI: 00:1c.3: Disabling device +PCI: 00:1c.4: Disabling device +PCI: 00:1c.4: check set enabled +PCH: Remap PCIe function 5 to 3 +PCI: 00:1c.5 [8086/0000] bus ops +PCI: 00:1c.5 [8086/1e1a] enabled +PCI: 00:1c.6: Disabling device +PCI: 00:1c.7: Disabling device +PCH: RPFN 0x76543210 -> 0xfe3cd210 +PCH: PCIe map 1c.3 -> 1c.5 +PCH: PCIe map 1c.5 -> 1c.3 +PCI: 00:1d.0 [8086/0000] ops +PCI: 00:1d.0 [8086/1e26] enabled +Capability: type 0x0d @ 0x50 +Capability: type 0x0d @ 0x50 +PCI: 00:1e.0 [8086/244e] enabled +PCI: 00:1f.0 [8086/0000] bus ops +PCI: 00:1f.0 [8086/1e49] enabled +PCI: 00:1f.2 [8086/0000] ops +CBFS: 'Master Header Locator' located CBFS at [600100:7fffc0) +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 18a80 size 4cc +PCI: 00:1f.2 [8086/1e00] enabled +PCI: 00:1f.3 [8086/0000] bus ops +PCI: 00:1f.3 [8086/1e22] enabled +PCI: 00:1f.5: Disabling device +PCI: 00:1f.6: Disabling device +PCI: 00:01.0 scanning... +do_pci_scan_bridge for PCI: 00:01.0 +PCI: pci_scan_bus for bus 01 +scan_bus: scanning of bus PCI: 00:01.0 took 11 usecs +PCI: 00:1c.0 scanning... +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 02 +scan_bus: scanning of bus PCI: 00:1c.0 took 41 usecs +PCI: 00:1c.1 scanning... +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 03 +PCI: 03:00.0 [10ec/8168] enabled +Capability: type 0x01 @ 0x40 +Capability: type 0x05 @ 0x50 +Capability: type 0x10 @ 0x70 +Capability: type 0x10 @ 0x40 +Enabling Common Clock Configuration +ASPM: Enabled L0s and L1 +Capability: type 0x01 @ 0x40 +Capability: type 0x05 @ 0x50 +Capability: type 0x10 @ 0x70 +Failed to enable LTR for dev = PCI: 03:00.0 +scan_bus: scanning of bus PCI: 00:1c.1 took 234 usecs +PCI: 00:1c.2 scanning... +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 04 +PCI: 04:00.0 [8086/0000] ops +PCI: 04:00.0 [8086/08b1] enabled +Capability: type 0x01 @ 0xc8 +Capability: type 0x05 @ 0xd0 +Capability: type 0x10 @ 0x40 +Capability: type 0x10 @ 0x40 +Enabling Common Clock Configuration +ASPM: Enabled L1 +Capability: type 0x01 @ 0xc8 +Capability: type 0x05 @ 0xd0 +Capability: type 0x10 @ 0x40 +scan_bus: scanning of bus PCI: 00:1c.2 took 280 usecs +PCI: 00:1c.3 scanning... +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 05 +PCI: 05:00.0 [10ec/8168] enabled +Capability: type 0x01 @ 0x40 +Capability: type 0x05 @ 0x50 +Capability: type 0x10 @ 0x70 +Capability: type 0x10 @ 0x40 +Enabling Common Clock Configuration +ASPM: Enabled L1 +Capability: type 0x01 @ 0x40 +Capability: type 0x05 @ 0x50 +Capability: type 0x10 @ 0x70 +Failed to enable LTR for dev = PCI: 05:00.0 +scan_bus: scanning of bus PCI: 00:1c.3 took 211 usecs +PCI: 00:1e.0 scanning... +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 06 +scan_bus: scanning of bus PCI: 00:1e.0 took 41 usecs +PCI: 00:1f.0 scanning... +scan_lpc_bus for PCI: 00:1f.0 +scan_lpc_bus for PCI: 00:1f.0 done +scan_bus: scanning of bus PCI: 00:1f.0 took 5 usecs +PCI: 00:1f.3 scanning... +scan_generic_bus for PCI: 00:1f.3 +scan_generic_bus for PCI: 00:1f.3 done +scan_bus: scanning of bus PCI: 00:1f.3 took 5 usecs +scan_bus: scanning of bus DOMAIN: 0000 took 1289 usecs +root_dev_scan_bus for Root Device done +scan_bus: scanning of bus Root Device took 1298 usecs +done +BS: BS_DEV_ENUMERATE times (us): entry 0 run 1399 exit 0 +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. +PCI: 00:01.0 read_resources bus 1 link: 0 +PCI: 00:01.0 read_resources bus 1 link: 0 done +PCI: 00:1c.0 read_resources bus 2 link: 0 +PCI: 00:1c.0 read_resources bus 2 link: 0 done +PCI: 00:1c.1 read_resources bus 3 link: 0 +PCI: 00:1c.1 read_resources bus 3 link: 0 done +PCI: 00:1c.2 read_resources bus 4 link: 0 +PCI: 00:1c.2 read_resources bus 4 link: 0 done +PCI: 00:1c.3 read_resources bus 5 link: 0 +PCI: 00:1c.3 read_resources bus 5 link: 0 done +PCI: 00:1e.0 read_resources bus 6 link: 0 +PCI: 00:1e.0 read_resources bus 6 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: acac + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 + PCI: 00:01.0 + PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 + PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 + PCI: 00:14.0 + PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:16.0 + PCI: 00:16.1 + PCI: 00:16.2 + PCI: 00:16.3 + PCI: 00:19.0 + PCI: 00:1a.0 + PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.1 child on link 0 PCI: 03:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 + PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18 + PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 + PCI: 00:1c.2 child on link 0 PCI: 04:00.0 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 04:00.0 + PCI: 04:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.5 + PCI: 00:1c.4 + PCI: 00:1c.3 child on link 0 PCI: 05:00.0 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18 + PCI: 05:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 + PCI: 00:1c.6 + PCI: 00:1c.7 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1f.0 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1f.5 + PCI: 00:1f.6 +DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 03:00.0 10 * [0x0 - 0xff] io +PCI: 00:1c.1 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 10 * [0x0 - 0xff] io +PCI: 00:1c.3 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 1c * [0x0 - 0xfff] io +PCI: 00:1c.3 1c * [0x1000 - 0x1fff] io +PCI: 00:02.0 20 * [0x2000 - 0x203f] io +PCI: 00:1f.2 20 * [0x2040 - 0x205f] io +PCI: 00:1f.2 10 * [0x2060 - 0x2067] io +PCI: 00:1f.2 18 * [0x2068 - 0x206f] io +PCI: 00:1f.2 14 * [0x2070 - 0x2073] io +PCI: 00:1f.2 1c * [0x2074 - 0x2077] io +DOMAIN: 0000 io: base: 2078 size: 2078 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem +PCI: 00:1c.1 prefmem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 03:00.0 18 * [0x0 - 0xfff] mem +PCI: 00:1c.1 mem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 04:00.0 10 * [0x0 - 0x1fff] mem +PCI: 00:1c.2 mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 20 * [0x0 - 0x3fff] prefmem +PCI: 05:00.0 18 * [0x4000 - 0x4fff] prefmem +PCI: 00:1c.3 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem +PCI: 00:1c.1 24 * [0x10400000 - 0x104fffff] prefmem +PCI: 00:1c.1 20 * [0x10500000 - 0x105fffff] mem +PCI: 00:1c.2 20 * [0x10600000 - 0x106fffff] mem +PCI: 00:1c.3 24 * [0x10700000 - 0x107fffff] prefmem +PCI: 00:14.0 10 * [0x10800000 - 0x1080ffff] mem +PCI: 00:1b.0 10 * [0x10810000 - 0x10813fff] mem +PCI: 00:1f.2 24 * [0x10814000 - 0x108147ff] mem +PCI: 00:1a.0 10 * [0x10815000 - 0x108153ff] mem +PCI: 00:1d.0 10 * [0x10816000 - 0x108163ff] mem +PCI: 00:1f.3 10 * [0x10817000 - 0x108170ff] mem +DOMAIN: 0000 mem: base: 10817100 size: 10817100 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: PCI: 00:00.0 60 base f8000000 limit fbffffff mem (fixed) +constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) +avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit f7ffffff +Setting resources... +DOMAIN: 0000 io: base:1000 size:2078 align:12 gran:0 limit:ffff +PCI: 00:1c.1 1c * [0x1000 - 0x1fff] io +PCI: 00:1c.3 1c * [0x2000 - 0x2fff] io +PCI: 00:02.0 20 * [0x3000 - 0x303f] io +PCI: 00:1f.2 20 * [0x3040 - 0x305f] io +PCI: 00:1f.2 10 * [0x3060 - 0x3067] io +PCI: 00:1f.2 18 * [0x3068 - 0x306f] io +PCI: 00:1f.2 14 * [0x3070 - 0x3073] io +PCI: 00:1f.2 1c * [0x3074 - 0x3077] io +DOMAIN: 0000 io: next_base: 3078 size: 2078 align: 12 gran: 0 done +PCI: 00:01.0 io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:01.0 io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.1 io: base:1000 size:1000 align:12 gran:12 limit:1fff +PCI: 03:00.0 10 * [0x1000 - 0x10ff] io +PCI: 00:1c.1 io: next_base: 1100 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.2 io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 io: base:2000 size:1000 align:12 gran:12 limit:2fff +PCI: 05:00.0 10 * [0x2000 - 0x20ff] io +PCI: 00:1c.3 io: next_base: 2100 size: 1000 align: 12 gran: 12 done +PCI: 00:1e.0 io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1e.0 io: next_base: ffff size: 0 align: 12 gran: 12 done +DOMAIN: 0000 mem: base:e0000000 size:10817100 align:28 gran:0 limit:f7ffffff +PCI: 00:02.0 18 * [0xe0000000 - 0xefffffff] prefmem +PCI: 00:02.0 10 * [0xf0000000 - 0xf03fffff] mem +PCI: 00:1c.1 24 * [0xf0400000 - 0xf04fffff] prefmem +PCI: 00:1c.1 20 * [0xf0500000 - 0xf05fffff] mem +PCI: 00:1c.2 20 * [0xf0600000 - 0xf06fffff] mem +PCI: 00:1c.3 24 * [0xf0700000 - 0xf07fffff] prefmem +PCI: 00:14.0 10 * [0xf0800000 - 0xf080ffff] mem +PCI: 00:1b.0 10 * [0xf0810000 - 0xf0813fff] mem +PCI: 00:1f.2 24 * [0xf0814000 - 0xf08147ff] mem +PCI: 00:1a.0 10 * [0xf0815000 - 0xf08153ff] mem +PCI: 00:1d.0 10 * [0xf0816000 - 0xf08163ff] mem +PCI: 00:1f.3 10 * [0xf0817000 - 0xf08170ff] mem +DOMAIN: 0000 mem: next_base: f0817100 size: 10817100 align: 28 gran: 0 done +PCI: 00:01.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff +PCI: 00:01.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done +PCI: 00:01.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff +PCI: 00:01.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff +PCI: 00:1c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff +PCI: 00:1c.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 prefmem: base:f0400000 size:100000 align:20 gran:20 limit:f04fffff +PCI: 03:00.0 20 * [0xf0400000 - 0xf0403fff] prefmem +PCI: 00:1c.1 prefmem: next_base: f0404000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 mem: base:f0500000 size:100000 align:20 gran:20 limit:f05fffff +PCI: 03:00.0 18 * [0xf0500000 - 0xf0500fff] mem +PCI: 00:1c.1 mem: next_base: f0501000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff +PCI: 00:1c.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 mem: base:f0600000 size:100000 align:20 gran:20 limit:f06fffff +PCI: 04:00.0 10 * [0xf0600000 - 0xf0601fff] mem +PCI: 00:1c.2 mem: next_base: f0602000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.3 prefmem: base:f0700000 size:100000 align:20 gran:20 limit:f07fffff +PCI: 05:00.0 20 * [0xf0700000 - 0xf0703fff] prefmem +PCI: 05:00.0 18 * [0xf0704000 - 0xf0704fff] prefmem +PCI: 00:1c.3 prefmem: next_base: f0705000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.3 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff +PCI: 00:1c.3 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff +PCI: 00:1e.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff +PCI: 00:1e.0 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +TOUUD 0x47d600000 TOLUD 0x82a00000 TOM 0x400000000 +MEBASE 0x7ffff00000 +IGD decoded, subtracting 32M UMA and 2M GTT +TSEG base 0x80000000 size 8M +Available memory below 4GB: 2048M +Available memory above 4GB: 14294M +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io +PCI: 00:01.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:01.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 mem +PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f03fffff] size 0x00400000 gran 0x16 mem64 +PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64 +PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io +PCI: 00:14.0 10 <- [0x00f0800000 - 0x00f080ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:1a.0 10 <- [0x00f0815000 - 0x00f08153ff] size 0x00000400 gran 0x0a mem +PCI: 00:1b.0 10 <- [0x00f0810000 - 0x00f0813fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 mem +PCI: 00:1c.1 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io +PCI: 00:1c.1 24 <- [0x00f0400000 - 0x00f04fffff] size 0x00100000 gran 0x14 bus 03 prefmem +PCI: 00:1c.1 20 <- [0x00f0500000 - 0x00f05fffff] size 0x00100000 gran 0x14 bus 03 mem +PCI: 00:1c.1 assign_resources, bus 3 link: 0 +PCI: 03:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io +PCI: 03:00.0 18 <- [0x00f0500000 - 0x00f0500fff] size 0x00001000 gran 0x0c mem64 +PCI: 03:00.0 20 <- [0x00f0400000 - 0x00f0403fff] size 0x00004000 gran 0x0e prefmem64 +PCI: 00:1c.1 assign_resources, bus 3 link: 0 +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:1c.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:1c.2 20 <- [0x00f0600000 - 0x00f06fffff] size 0x00100000 gran 0x14 bus 04 mem +PCI: 00:1c.2 assign_resources, bus 4 link: 0 +PCI: 04:00.0 10 <- [0x00f0600000 - 0x00f0601fff] size 0x00002000 gran 0x0d mem64 +PCI: 00:1c.2 assign_resources, bus 4 link: 0 +PCI: 00:1c.3 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 05 io +PCI: 00:1c.3 24 <- [0x00f0700000 - 0x00f07fffff] size 0x00100000 gran 0x14 bus 05 prefmem +PCI: 00:1c.3 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 05 mem +PCI: 00:1c.3 assign_resources, bus 5 link: 0 +PCI: 05:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io +PCI: 05:00.0 18 <- [0x00f0704000 - 0x00f0704fff] size 0x00001000 gran 0x0c prefmem64 +PCI: 05:00.0 20 <- [0x00f0700000 - 0x00f0703fff] size 0x00004000 gran 0x0e prefmem64 +PCI: 00:1c.3 assign_resources, bus 5 link: 0 +PCI: 00:1d.0 10 <- [0x00f0816000 - 0x00f08163ff] size 0x00000400 gran 0x0a mem +PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 06 io +PCI: 00:1e.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 06 prefmem +PCI: 00:1e.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 06 mem +PCI: 00:1f.2 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io +PCI: 00:1f.2 24 <- [0x00f0814000 - 0x00f08147ff] size 0x00000800 gran 0x0b mem +PCI: 00:1f.3 10 <- [0x00f0817000 - 0x00f08170ff] size 0x00000100 gran 0x08 mem64 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: acac + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 1000 size 2078 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base e0000000 size 10817100 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base 100000000 size 37d600000 align 0 gran 0 limit 0 flags e0004200 index 5 + DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6 + DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7 + DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8 + DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 + DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a + PCI: 00:00.0 + PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60 + PCI: 00:01.0 + PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:01.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 + PCI: 00:01.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 + PCI: 00:02.0 + PCI: 00:02.0 resource base f0000000 size 400000 align 22 gran 22 limit f03fffff flags 60000201 index 10 + PCI: 00:02.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18 + PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20 + PCI: 00:14.0 + PCI: 00:14.0 resource base f0800000 size 10000 align 16 gran 16 limit f080ffff flags 60000201 index 10 + PCI: 00:16.0 + PCI: 00:16.1 + PCI: 00:16.2 + PCI: 00:16.3 + PCI: 00:19.0 + PCI: 00:1a.0 + PCI: 00:1a.0 resource base f0815000 size 400 align 12 gran 10 limit f08153ff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base f0810000 size 4000 align 14 gran 14 limit f0813fff flags 60000201 index 10 + PCI: 00:1c.0 + PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 + PCI: 00:1c.1 child on link 0 PCI: 03:00.0 + PCI: 00:1c.1 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c + PCI: 00:1c.1 resource base f0400000 size 100000 align 20 gran 20 limit f04fffff flags 60081202 index 24 + PCI: 00:1c.1 resource base f0500000 size 100000 align 20 gran 20 limit f05fffff flags 60080202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10 + PCI: 03:00.0 resource base f0500000 size 1000 align 12 gran 12 limit f0500fff flags 60000201 index 18 + PCI: 03:00.0 resource base f0400000 size 4000 align 14 gran 14 limit f0403fff flags 60001201 index 20 + PCI: 00:1c.2 child on link 0 PCI: 04:00.0 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base f0600000 size 100000 align 20 gran 20 limit f06fffff flags 60080202 index 20 + PCI: 04:00.0 + PCI: 04:00.0 resource base f0600000 size 2000 align 13 gran 13 limit f0601fff flags 60000201 index 10 + PCI: 00:1c.5 + PCI: 00:1c.4 + PCI: 00:1c.3 child on link 0 PCI: 05:00.0 + PCI: 00:1c.3 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c + PCI: 00:1c.3 resource base f0700000 size 100000 align 20 gran 20 limit f07fffff flags 60081202 index 24 + PCI: 00:1c.3 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 10 + PCI: 05:00.0 resource base f0704000 size 1000 align 12 gran 12 limit f0704fff flags 60001201 index 18 + PCI: 05:00.0 resource base f0700000 size 4000 align 14 gran 14 limit f0703fff flags 60001201 index 20 + PCI: 00:1c.6 + PCI: 00:1c.7 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base f0816000 size 400 align 12 gran 10 limit f08163ff flags 60000200 index 10 + PCI: 00:1e.0 + PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20 + PCI: 00:1f.0 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 3060 size 8 align 3 gran 3 limit 3067 flags 60000100 index 10 + PCI: 00:1f.2 resource base 3070 size 4 align 2 gran 2 limit 3073 flags 60000100 index 14 + PCI: 00:1f.2 resource base 3068 size 8 align 3 gran 3 limit 306f flags 60000100 index 18 + PCI: 00:1f.2 resource base 3074 size 4 align 2 gran 2 limit 3077 flags 60000100 index 1c + PCI: 00:1f.2 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 20 + PCI: 00:1f.2 resource base f0814000 size 800 align 12 gran 11 limit f08147ff flags 60000200 index 24 + PCI: 00:1f.3 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + PCI: 00:1f.3 resource base f0817000 size 100 align 12 gran 8 limit f08170ff flags 60000201 index 10 + PCI: 00:1f.5 + PCI: 00:1f.6 +Done allocating resources. +BS: BS_DEV_RESOURCES times (us): entry 0 run 2605 exit 0 +Enabling resources... +PCI: 00:00.0 subsystem <- 1028/0574 +PCI: 00:00.0 cmd <- 06 +PCI: 00:01.0 bridge ctrl <- 0003 +PCI: 00:01.0 cmd <- 00 +PCI: 00:02.0 subsystem <- 1028/0574 +PCI: 00:02.0 cmd <- 03 +PCI: 00:14.0 subsystem <- 1028/0574 +PCI: 00:14.0 cmd <- 102 +PCI: 00:1a.0 subsystem <- 1028/0574 +PCI: 00:1a.0 cmd <- 102 +PCI: 00:1b.0 subsystem <- 1028/0574 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 1028/0574 +PCI: 00:1c.0 cmd <- 100 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 1028/0574 +PCI: 00:1c.1 cmd <- 107 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 subsystem <- 1028/0574 +PCI: 00:1c.2 cmd <- 106 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 subsystem <- 1028/0574 +PCI: 00:1c.3 cmd <- 107 +PCI: 00:1d.0 subsystem <- 1028/0574 +PCI: 00:1d.0 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 cmd <- 100 +pch_decode_init +PCI: 00:1f.0 subsystem <- 1028/0574 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.2 subsystem <- 1028/0574 +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 1028/0574 +PCI: 00:1f.3 cmd <- 103 +PCI: 03:00.0 cmd <- 03 +PCI: 04:00.0 cmd <- 02 +PCI: 05:00.0 cmd <- 03 +done. +BS: BS_DEV_ENABLE times (us): entry 0 run 159 exit 0 +Initializing devices... +Root Device init ... +Root Device init finished in 0 usecs +CPU_CLUSTER: 0 init ... +start_eip=0x00001000, code_size=0x00000031 +Setting up SMI for CPU +Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 +Processing 12 relocs. Offset value of 0x00038000 +Adjusting 00038002: 0x00000024 -> 0x00038024 +Adjusting 0003801d: 0x0000003c -> 0x0003803c +Adjusting 00038026: 0x00000024 -> 0x00038024 +Adjusting 00038054: 0x00000120 -> 0x00038120 +Adjusting 00038066: 0x000001a8 -> 0x000381a8 +Adjusting 0003806f: 0x00000100 -> 0x00038100 +Adjusting 00038077: 0x00000104 -> 0x00038104 +Adjusting 00038081: 0x00000110 -> 0x00038110 +Adjusting 0003808a: 0x00000114 -> 0x00038114 +Adjusting 000380ab: 0x00000118 -> 0x00038118 +Adjusting 000380b2: 0x0000010c -> 0x0003810c +Adjusting 000380b8: 0x00000108 -> 0x00038108 +SMM Module: stub loaded at 00038000. Will call 7ff85a91(7ffcd380) +Installing SMM handler to 0x80000000 +Loading module at 80010000 with entry 80010554. filesize: 0x15d0 memsize: 0x55f0 +Processing 68 relocs. Offset value of 0x80010000 +Adjusting 80010036: 0x000014bc -> 0x800114bc +Adjusting 80010055: 0x000014bc -> 0x800114bc +Adjusting 80010108: 0x000014bc -> 0x800114bc +Adjusting 8001019d: 0x000014cc -> 0x800114cc +Adjusting 800104cb: 0x000015d0 -> 0x800115d0 +Adjusting 80010521: 0x000015c8 -> 0x800115c8 +Adjusting 80010537: 0x00001520 -> 0x80011520 +Adjusting 8001055d: 0x000015d0 -> 0x800115d0 +Adjusting 8001056b: 0x000015d0 -> 0x800115d0 +Adjusting 80010578: 0x000015c0 -> 0x800115c0 +Adjusting 80010583: 0x000015c0 -> 0x800115c0 +Adjusting 80010597: 0x000015c4 -> 0x800115c4 +Adjusting 8001059d: 0x000015d4 -> 0x800115d4 +Adjusting 800105a5: 0x000015c4 -> 0x800115c4 +Adjusting 800105c2: 0x000015d4 -> 0x800115d4 +Adjusting 800105cb: 0x000015c0 -> 0x800115c0 +Adjusting 800105e2: 0x000015d8 -> 0x800115d8 +Adjusting 800105f2: 0x000015d8 -> 0x800115d8 +Adjusting 80010618: 0x000015d8 -> 0x800115d8 +Adjusting 80010680: 0x000014ec -> 0x800114ec +Adjusting 80010792: 0x000014a8 -> 0x800114a8 +Adjusting 80010a8e: 0x000015dc -> 0x800115dc +Adjusting 80010abd: 0x000015e0 -> 0x800115e0 +Adjusting 80010ad0: 0x000015dc -> 0x800115dc +Adjusting 80010af3: 0x000015e0 -> 0x800115e0 +Adjusting 80010bb6: 0x000015dc -> 0x800115dc +Adjusting 80010dee: 0x000015e0 -> 0x800115e0 +Adjusting 80010ff5: 0x000015e0 -> 0x800115e0 +Adjusting 800110d4: 0x000015c8 -> 0x800115c8 +Adjusting 800110e4: 0x000015c8 -> 0x800115c8 +Adjusting 800110f9: 0x000015c8 -> 0x800115c8 +Adjusting 8001111a: 0x000015c8 -> 0x800115c8 +Adjusting 80011147: 0x000015c8 -> 0x800115c8 +Adjusting 80011167: 0x000015c8 -> 0x800115c8 +Adjusting 8001117d: 0x000015ec -> 0x800115ec +Adjusting 800111cb: 0x000015ec -> 0x800115ec +Adjusting 800111d1: 0x000015e8 -> 0x800115e8 +Adjusting 800111d9: 0x000015e4 -> 0x800115e4 +Adjusting 800111f6: 0x000015e4 -> 0x800115e4 +Adjusting 80011211: 0x000015c8 -> 0x800115c8 +Adjusting 80011267: 0x000015e8 -> 0x800115e8 +Adjusting 800112bd: 0x000014fc -> 0x800114fc +Adjusting 800112da: 0x000015c8 -> 0x800115c8 +Adjusting 800112f9: 0x00001510 -> 0x80011510 +Adjusting 800112fe: 0x000015e8 -> 0x800115e8 +Adjusting 800113cf: 0x000015c8 -> 0x800115c8 +Adjusting 800113fd: 0x000015c8 -> 0x800115c8 +Adjusting 8001142b: 0x000015c8 -> 0x800115c8 +Adjusting 80011451: 0x000015c8 -> 0x800115c8 +Adjusting 8001145e: 0x000015e8 -> 0x800115e8 +Adjusting 80011472: 0x000015c8 -> 0x800115c8 +Adjusting 800114a0: 0x00001488 -> 0x80011488 +Adjusting 800114a8: 0x00000021 -> 0x80010021 +Adjusting 800114ac: 0x00001488 -> 0x80011488 +Adjusting 800114b4: 0x00000092 -> 0x80010092 +Adjusting 800114c0: 0x000014d8 -> 0x800114d8 +Adjusting 800114d8: 0x000002d5 -> 0x800102d5 +Adjusting 800114dc: 0x000002e1 -> 0x800102e1 +Adjusting 800114e0: 0x000002e4 -> 0x800102e4 +Adjusting 80011530: 0x000012a4 -> 0x800112a4 +Adjusting 80011534: 0x0000112a -> 0x8001112a +Adjusting 80011540: 0x00001428 -> 0x80011428 +Adjusting 80011544: 0x000010d1 -> 0x800110d1 +Adjusting 80011548: 0x000010f2 -> 0x800110f2 +Adjusting 8001154c: 0x000010ed -> 0x800110ed +Adjusting 80011554: 0x0000120e -> 0x8001120e +Adjusting 80011558: 0x000010e1 -> 0x800110e1 +Adjusting 80011574: 0x00001252 -> 0x80011252 +Loading module at 80008000 with entry 80008000. filesize: 0x1a8 memsize: 0x1a8 +Processing 12 relocs. Offset value of 0x80008000 +Adjusting 80008002: 0x00000024 -> 0x80008024 +Adjusting 8000801d: 0x0000003c -> 0x8000803c +Adjusting 80008026: 0x00000024 -> 0x80008024 +Adjusting 80008054: 0x00000120 -> 0x80008120 +Adjusting 80008066: 0x000001a8 -> 0x800081a8 +Adjusting 8000806f: 0x00000100 -> 0x80008100 +Adjusting 80008077: 0x00000104 -> 0x80008104 +Adjusting 80008081: 0x00000110 -> 0x80008110 +Adjusting 8000808a: 0x00000114 -> 0x80008114 +Adjusting 800080ab: 0x00000118 -> 0x80008118 +Adjusting 800080b2: 0x0000010c -> 0x8000810c +Adjusting 800080b8: 0x00000108 -> 0x80008108 +SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd +SMM Module: placing jmp sequence at 80007800 rel16 0x07fd +SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd +SMM Module: stub loaded at 80008000. Will call 80010554(00000000) +Initializing southbridge SMI... ... pmbase = 0x0500 + +SMI_STS: PM1 +PM1_STS: WAK PWRBTN +GPE0_STS: GPIO14 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO0 +ALT_GP_SMI_STS: GPI14 GPI12 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI0 +TCO_STS: + ... raise SMI# +In relocation handler: cpu 0 +New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00 +Writing SMRR. base = 0x80000006, mask=0xff800800 +Relocation complete. +Locking SMM. +Initializing CPU #0 +CPU: vendor Intel device 306a9 +CPU: family 06, model 3a, stepping 09 +Enabling cache +CBFS: 'Master Header Locator' located CBFS at [600100:7fffc0) +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: Found @ offset 12bc0 size 5800 +microcode: sig=0x306a9 pf=0x2 revision=0x1b +CPU: Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 +0x0000000080000000 - 0x00000000e0000000 size 0x60000000 type 0 +0x00000000e0000000 - 0x00000000f0000000 size 0x10000000 type 1 +0x00000000f0000000 - 0x0000000100000000 size 0x10000000 type 0 +0x0000000100000000 - 0x000000047d600000 size 0x37d600000 type 6 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits +MTRR: default type WB/UC MTRR counts: 4/8. +MTRR: WB selected as default type. +MTRR: 0 base 0x0000000080000000 mask 0x0000000fc0000000 type 0 +MTRR: 1 base 0x00000000c0000000 mask 0x0000000fe0000000 type 0 +MTRR: 2 base 0x00000000e0000000 mask 0x0000000ff0000000 type 1 +MTRR: 3 base 0x00000000f0000000 mask 0x0000000ff0000000 type 0 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local APIC... apic_id: 0x00 done. +VMX status: enabled, unlocked +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 3200 +Turbo is available but hidden +Turbo has been enabled +CPU: 0 has 4 cores, 1 threads per core +CPU: 0 has core 2 +CPU1: stack_base 7ffb4000, stack_end 7ffb4ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 2. +After apic_write. +In relocation handler: cpu 1 +Startup point 1. +Waiting for send to finish... ++New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00 +Sending STARTUP #2 to 2. +After apic_write. +Writing SMRR. base = 0x80000006, mask=0xff800800 +Startup point 1. +Waiting for send to finish... ++After Startup. +CPU: 0 has core 4 +Initializing CPU #1 +CPU: vendor Intel device 306a9 +CPU: family 06, model 3a, stepping 09 +Enabling cache +CBFS: 'Master Header Locator' located CBFS at [600100:7fffc0) +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: Found @ offset 12bc0 size 5800 +microcode: sig=0x306a9 pf=0x2 revision=0x0 +microcode: updated to revision 0x1b date=2014-05-29 +CPU: Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local APIC... apic_id: 0x02 done. +VMX status: enabled, unlocked +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 3200 +CPU #1 initialized +CPU2: stack_base 7ffb3000, stack_end 7ffb3ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 4. +After apic_write. +In relocation handler: cpu 2 +Startup point 1. +Waiting for send to finish... ++New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00 +Sending STARTUP #2 to 4. +After apic_write. +Writing SMRR. base = 0x80000006, mask=0xff800800 +Startup point 1. +Waiting for send to finish... ++After Startup. +CPU: 0 has core 6 +Initializing CPU #2 +CPU: vendor Intel device 306a9 +CPU: family 06, model 3a, stepping 09 +Enabling cache +CBFS: 'Master Header Locator' located CBFS at [600100:7fffc0) +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: Found @ offset 12bc0 size 5800 +microcode: sig=0x306a9 pf=0x2 revision=0x0 +microcode: updated to revision 0x1b date=2014-05-29 +CPU: Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local APIC... apic_id: 0x04 done. +VMX status: enabled, unlocked +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 3200 +CPU #2 initialized +CPU3: stack_base 7ffb2000, stack_end 7ffb2ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 6. +After apic_write. +In relocation handler: cpu 3 +Startup point 1. +Waiting for send to finish... ++New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00 +Sending STARTUP #2 to 6. +After apic_write. +Writing SMRR. base = 0x80000006, mask=0xff800800 +Startup point 1. +Waiting for send to finish... ++After Startup. +CPU #0 initialized +Waiting for 1 CPUS to stop +Initializing CPU #3 +CPU: vendor Intel device 306a9 +CPU: family 06, model 3a, stepping 09 +Enabling cache +CBFS: 'Master Header Locator' located CBFS at [600100:7fffc0) +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: Found @ offset 12bc0 size 5800 +microcode: sig=0x306a9 pf=0x2 revision=0x0 +microcode: updated to revision 0x1b date=2014-05-29 +CPU: Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local APIC... apic_id: 0x06 done. +VMX status: enabled, unlocked +model_x06ax: energy policy set to 6 +model_x06ax: frequency set to 3200 +CPU #3 initialized +All AP CPUs stopped (3196 loops) +CPU0: stack: 7ffb5000 - 7ffb6000, lowest used address 7ffb5a20, stack used: 1504 bytes +CPU1: stack: 7ffb4000 - 7ffb5000, lowest used address 7ffb4be0, stack used: 1056 bytes +CPU2: stack: 7ffb3000 - 7ffb4000, lowest used address 7ffb3be0, stack used: 1056 bytes +CPU3: stack: 7ffb2000 - 7ffb3000, lowest used address 7ffb2be0, stack used: 1056 bytes +CPU_CLUSTER: 0 init finished in 142737 usecs +PCI: 00:00.0 init ... +Disabling PEG12. +Disabling PEG11. +Disabling Device 4. +Disabling PEG60. +Disabling Device 7. +Set BIOS_RESET_CPL +CPU TDP: 77 Watts +PCI: 00:00.0 init finished in 1014 usecs +PCI: 00:02.0 init ... +GT Power Management Init +IVB GT1 Power Meter Weights +GT Power Management Init (post VBIOS) +Error: GNVS or ASLB not set. +PCI: 00:02.0 init finished in 496 usecs +PCI: 00:14.0 init ... +XHCI: Setting up controller.. done. +PCI: 00:14.0 init finished in 7 usecs +PCI: 00:1a.0 init ... +EHCI: Setting up controller.. done. +PCI: 00:1a.0 init finished in 13 usecs +PCI: 00:1b.0 init ... +Azalia: base = f0810000 +Azalia: codec_mask = 0c +Azalia: Initializing codec #3 +Azalia: codec viddid: 80862806 +Azalia: verb_size: 16 +Azalia: verb loaded. +Azalia: Initializing codec #2 +Azalia: codec viddid: 10ec0662 +Azalia: verb_size: 48 +Azalia: verb loaded. +PCI: 00:1b.0 init finished in 4767 usecs +PCI: 00:1c.0 init ... +Initializing PCH PCIe bridge. +PCI: 00:1c.0 init finished in 8 usecs +PCI: 00:1c.1 init ... +Initializing PCH PCIe bridge. +PCI: 00:1c.1 init finished in 8 usecs +PCI: 00:1c.2 init ... +Initializing PCH PCIe bridge. +PCI: 00:1c.2 init finished in 8 usecs +PCI: 00:1c.3 init ... +Initializing PCH PCIe bridge. +PCI: 00:1c.3 init finished in 8 usecs +PCI: 00:1d.0 init ... +EHCI: Setting up controller.. done. +PCI: 00:1d.0 init finished in 12 usecs +PCI: 00:1f.0 init ... +pch: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +CBFS: 'Master Header Locator' located CBFS at [600100:7fffc0) +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 18a80 size 4cc +Set power on after power failure. +CBFS: 'Master Header Locator' located CBFS at [600100:7fffc0) +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 18a80 size 4cc +NMI sources enabled. +PantherPoint PM init +rtc_failed = 0x0 +Enabling BIOS updates outside of SMM... pch_spi_init +PCI: 00:1f.0 init finished in 717 usecs +PCI: 00:1f.2 init ... +SATA: Initializing... +CBFS: 'Master Header Locator' located CBFS at [600100:7fffc0) +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 18a80 size 4cc +SATA: Controller in AHCI mode. +ABAR: f0814000 +PCI: 00:1f.2 init finished in 372 usecs +PCI: 00:1f.3 init ... +PCI: 00:1f.3 init finished in 7 usecs +PCI: 03:00.0 init ... +PCI: 03:00.0 init finished in 0 usecs +PCI: 04:00.0 init ... +PCI: 04:00.0 init finished in 0 usecs +PCI: 05:00.0 init ... +PCI: 05:00.0 init finished in 0 usecs +Devices initialized +Show all devs... After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +APIC: acac: enabled 0 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:14.0: enabled 1 +PCI: 00:16.0: enabled 0 +PCI: 00:16.1: enabled 0 +PCI: 00:16.2: enabled 0 +PCI: 00:16.3: enabled 0 +PCI: 00:19.0: enabled 0 +PCI: 00:1a.0: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.5: enabled 0 +PCI: 00:1c.4: enabled 0 +PCI: 00:1c.3: enabled 1 +PCI: 00:1c.6: enabled 0 +PCI: 00:1c.7: enabled 0 +PCI: 00:1d.0: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 00:1f.0: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +PCI: 00:1f.5: enabled 0 +PCI: 00:1f.6: enabled 0 +PCI: 03:00.0: enabled 1 +PCI: 04:00.0: enabled 1 +PCI: 05:00.0: enabled 1 +APIC: 02: enabled 1 +APIC: 04: enabled 1 +APIC: 06: enabled 1 +Updating MRC cache data. +BS: BS_DEV_INIT times (us): entry 5 run 150226 exit 0 +Finalize devices... +PCI: 00:1f.0 final +Devices finalized +BS: BS_POST_DEVICE times (us): entry 0 run 36 exit 0 +Trying to find the wakeup vector... +Looking on 000f6930 for valid checksum +Checksum 1 passed +Checksum 2 passed all OK +RSDP found at 000f6930 +RSDT found at 7fe7a030 ends at 7fe7a070 +FADT found at 7fe7ca80 +FACS found at 7fe7a240 +OS waking vector is 0009a1d0 +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 75 exit 0 + diff --git a/src/mainboard/dell/inspiron_660s/logs/mce b/src/mainboard/dell/inspiron_660s/logs/mce new file mode 100644 index 0000000..d99106b --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/logs/mce @@ -0,0 +1,22 @@ +# dmesg | grep mce +[ 0.010727] mce: CPU supports 9 MCE banks +[ 0.050022] mce: [Hardware Error]: Machine check events logged +[ 0.050024] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 7: ee2000000003110a +[ 0.050031] mce: [Hardware Error]: TSC 0 ADDR feffff40 MISC 1040000086 +[ 0.050038] mce: [Hardware Error]: PROCESSOR 0:306a9 TIME 1512242705 SOCKET 0 APIC 0 microcode 1b +[ 0.050042] mce: [Hardware Error]: Machine check events logged +[ 0.050044] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 8: ee2000000003110a +[ 0.050047] mce: [Hardware Error]: TSC 0 ADDR feffff00 MISC 1040000086 +[ 0.050053] mce: [Hardware Error]: PROCESSOR 0:306a9 TIME 1512242705 SOCKET 0 APIC 0 microcode 1b + + +$ ras-mc-ctl --errors +No Memory errors. + +No PCIe AER errors. + +No Extlog errors. + +MCE events: +1 2017-12-02 15:46:44 -0500 error: corrected filtering (some unreported errors in same region) Generic CACHE Level-2 Generic Error, mcg mcgstatus=0, mci Error_overflow Uncorrected_error Processor_context_corrupt, mcgcap=0x00000c09, status=0xee2000000003110a, addr=0xfeffff40, misc=0x1040000086, walltime=0x5a23114e, cpuid=0x000306a9, bank=0x00000007 +2 2017-12-02 15:46:44 -0500 error: corrected filtering (some unreported errors in same region) Generic CACHE Level-2 Generic Error, mcg mcgstatus=0, mci Error_overflow Uncorrected_error Processor_context_corrupt, mcgcap=0x00000c09, status=0xee2000000003110a, addr=0xfeffff00, misc=0x1040000086, walltime=0x5a23114e, cpuid=0x000306a9, bank=0x00000008 diff --git a/src/mainboard/dell/inspiron_660s/mainboard.c b/src/mainboard/dell/inspiron_660s/mainboard.c new file mode 100644 index 0000000..dfcf1a4 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/mainboard.c @@ -0,0 +1,15 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/inspiron_660s/romstage.c b/src/mainboard/dell/inspiron_660s/romstage.c new file mode 100644 index 0000000..8b13789 --- /dev/null +++ b/src/mainboard/dell/inspiron_660s/romstage.c @@ -0,0 +1 @@ + -- To view, visit https://review.coreboot.org/22682 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8dabb1e1d14e60957e8c8800b0c30921d6bb5d8e Gerrit-Change-Number: 22682 Gerrit-PatchSet: 1 Gerrit-Owner: Jean Lucas <jean(a)4ray.co>

1 0

Change in coreboot[master]: soc/intel/skylake: fix eMMC visibility under Windows
by build bot (Jenkins) (Code Review) 02 Dec '17

02 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22681 ) Change subject: soc/intel/skylake: fix eMMC visibility under Windows ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64019/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18868/ : SUCCESS -- To view, visit https://review.coreboot.org/22681 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3217e5d35fdb2f890ee51670dfab6c86476e2ca2 Gerrit-Change-Number: 22681 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Dec 2017 19:45:20 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: fix eMMC visibility under Windows
by Matt DeVillier (Code Review) 02 Dec '17

02 Dec '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/22681 Change subject: soc/intel/skylake: fix eMMC visibility under Windows ...................................................................... soc/intel/skylake: fix eMMC visibility under Windows For the internal eMMC to be used by Windows for installation, an ACPI device for the card/drive is required, with _RMV indicating that the device is non-removable. Add the required device/method to allow Windows to "see" the internal eMMC. TEST: boot google/chell with Tianocore payload and install Windows 10 to the internal eMMC drive. Change-Id: I3217e5d35fdb2f890ee51670dfab6c86476e2ca2 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/skylake/acpi/scs.asl 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/22681/1 diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 235a57e..00a6f65 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -101,6 +101,15 @@ Or (PMCR, 0x0003, PMCR) Store (PMCR, ^TEMP) } + + Device (CARD) + { + Name (_ADR, 0x00000008) // Slot 0, Function 8 + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + } } #if !IS_ENABLED(CONFIG_EXCLUDE_NATIVE_SD_INTERFACE) -- To view, visit https://review.coreboot.org/22681 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3217e5d35fdb2f890ee51670dfab6c86476e2ca2 Gerrit-Change-Number: 22681 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/intel/apollolake: Make use of Intel common Graphics block
by build bot (Jenkins) (Code Review) 02 Dec '17

02 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22616 ) Change subject: soc/intel/apollolake: Make use of Intel common Graphics block ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64017/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18866/ : SUCCESS -- To view, visit https://review.coreboot.org/22616 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Gerrit-Change-Number: 22616 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Dec 2017 14:07:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Make use of Intel common Graphics block
by build bot (Jenkins) (Code Review) 02 Dec '17

02 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22617 ) Change subject: soc/intel/cannonlake: Make use of Intel common Graphics block ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64018/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18867/ : SUCCESS -- To view, visit https://review.coreboot.org/22617 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d Gerrit-Change-Number: 22617 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Dec 2017 14:05:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common Graphics block
by build bot (Jenkins) (Code Review) 02 Dec '17

02 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22615 ) Change subject: soc/intel/skylake: Make use of Intel common Graphics block ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64016/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/18865/ : SUCCESS -- To view, visit https://review.coreboot.org/22615 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Gerrit-Change-Number: 22615 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Dec 2017 14:00:13 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017