Hello Hannah Williams,
I'd like you to do a code review. Please visit
https://review.coreboot.org/22639
to review the following change.
Change subject: acpi/cnvi.asl: Add _PRW for CNVi
......................................................................
acpi/cnvi.asl: Add _PRW for CNVi
Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
A src/soc/intel/apollolake/acpi/cnvi.asl
M src/soc/intel/apollolake/acpi/southbridge.asl
M src/soc/intel/apollolake/include/soc/gpe.h
3 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22639/1
diff --git a/src/soc/intel/apollolake/acpi/cnvi.asl b/src/soc/intel/apollolake/acpi/cnvi.asl
new file mode 100644
index 0000000..5d3616c
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/cnvi.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* CNVi Controller 0:C.0 */
+Device (CNVI) {
+ Name(_ADR, 0x000C0000)
+
+ Name (_S3D, 3) /* D3 supported in S3 */
+ Name (_S0W, 3) /* D3 can wake device in S0 */
+ Name (_S3W, 3) /* D3 can wake system from S3 */
+
+ Name (_PRW, Package() { GPE0A_CNVI_PME_STS, 3 })
+
+ Method (_STA, 0)
+ {
+ Return (0xF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 97a25a2..5b8f9b7 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -56,4 +56,10 @@
/* SGX */
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
#include <soc/intel/common/acpi/sgx.asl>
+
+/* CNVi */
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include "cnvi.asl"
+#endif
+
#endif
diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h
index 7dfb6f5..eb6e31f 100644
--- a/src/soc/intel/apollolake/include/soc/gpe.h
+++ b/src/soc/intel/apollolake/include/soc/gpe.h
@@ -33,6 +33,7 @@
#define GPE0A_GPIO_TIER1_SCI_STS 15
#define GPE0A_SMB_WAK_STS 16
#define GPE0A_SATA_PME_STS 17
+#define GPE0A_CNVI_PME_STS 18
/* Group DW0 is reserved in Apollolake */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3
Gerrit-Change-Number: 22639
Gerrit-PatchSet: 1
Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com>
John E. Kabat Jr. has uploaded this change for review. ( https://review.coreboot.org/22638
Change subject: mainboard/google/kahlee: Enable elog in Kconfig
......................................................................
mainboard/google/kahlee: Enable elog in Kconfig
- Change kahlee/Kconfig to enable elog and save the boot count in cmos.
BUG=b:65485690
TEST=Build & boot kahlee.
Change-Id: I5fe396c8f532b319481bc073f7541bcd743b92b9
Signed-off-by: John E. Kabat Jr <john.kabat(a)scarletltd.com>
---
M src/mainboard/google/kahlee/Kconfig
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/22638/1
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 6c9bfcc..7966930 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -29,6 +29,8 @@
select MAINBOARD_HAS_LPC_TPM
select SERIRQ_CONTINUOUS_MODE
select STONEYRIDGE_UART
+ select ELOG_GSMI
+ select ELOG_BOOT_COUNT
if BOARD_GOOGLE_BASEBOARD_KAHLEE
@@ -97,4 +99,12 @@
int
default 1
+config ELOG_BOOT_COUNT_CMOS_OFFSET
+ depends on ELOG && ELOG_BOOT_COUNT && !USE_OPTION_TABLE
+ int "Offset in CMOS to store the boot count"
+ default 144
+ help
+ This value must be greater than 16 bytes so as not to interfere
+ with the standard RTC region. Requires 8 bytes.
+
endif # BOARD_GOOGLE_KAHLEE || BOARD_GOOGLE_GRUNT
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5fe396c8f532b319481bc073f7541bcd743b92b9
Gerrit-Change-Number: 22638
Gerrit-PatchSet: 1
Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com>
John E. Kabat Jr. has posted comments on this change. ( https://review.coreboot.org/22636 )
Change subject: mainboard/google/kahlee: Enable elog in Kconfig
......................................................................
Patch Set 2:
> Uploaded patch set 2.
> Uploaded patch set 2.
IO took a wild guess and maybe my config was different. I re-added boot_device_spi_flash to see if that changed anything.
boot_device
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6
Gerrit-Change-Number: 22636
Gerrit-PatchSet: 2
Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com>
Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 30 Nov 2017 02:35:40 +0000
Gerrit-HasComments: No
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/22636
to look at the new patch set (#2).
Change subject: mainboard/google/kahlee: Enable elog in Kconfig
......................................................................
mainboard/google/kahlee: Enable elog in Kconfig
- Change kahlee/Kconfig to enable elog and save the boot count in cmos.
- Change soc/amd/common/Makefile to not include common/spi.c unless S3
is enabled.
- Change soc/amd/stoneyridge/Kconfig to set BOOT_DEVICE_SUPPORTS_WRITES
BUG=b:65485690
TEST=Build & boot kahlee.
WIP - More testing to follow with boot to ChromeOS.
Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6
Signed-off-by: John E. Kabat Jr <john.kabat(a)scarletltd.com>
---
M src/mainboard/google/kahlee/Kconfig
M src/soc/amd/common/Makefile.inc
M src/soc/amd/stoneyridge/Kconfig
3 files changed, 17 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/22636/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6
Gerrit-Change-Number: 22636
Gerrit-PatchSet: 2
Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com>
Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
John E. Kabat Jr. has posted comments on this change. ( https://review.coreboot.org/22636 )
Change subject: mainboard/google/kahlee: Enable elog in Kconfig
......................................................................
Patch Set 1:
> Build Unstable
>
> https://qa.coreboot.org/job/coreboot-gerrit/63911/ : UNSTABLE
>
> https://qa.coreboot.org/job/coreboot-checkpatch/18774/ : SUCCESS
I don't have a clue as to what caused this. Does anyone else have an idea?
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6
Gerrit-Change-Number: 22636
Gerrit-PatchSet: 1
Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com>
Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 30 Nov 2017 02:32:21 +0000
Gerrit-HasComments: No