coreboot-gerrit November 2017

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Change in coreboot[master]: amd/stoneyridge/include/soc/northbridge.h: Cleanup
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22635 ) Change subject: amd/stoneyridge/include/soc/northbridge.h: Cleanup ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18770/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63906/ : SUCCESS -- To view, visit https://review.coreboot.org/22635 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I882bf1cc9d9e6b587b5dc3d27cea1626f4dcc51a Gerrit-Change-Number: 22635 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 20:52:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge/include/soc/northbridge.h: Cleanup
by Richard Spiegel (Code Review) 29 Nov '17

29 Nov '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22635 Change subject: amd/stoneyridge/include/soc/northbridge.h: Cleanup ...................................................................... amd/stoneyridge/include/soc/northbridge.h: Cleanup There are instances where the pound "#" is separated from the word "define", it should be all together "#define". There are instances where bits are being declared as (1 << x), should be replaced by macro BIT(x). BUG=b:62239898 Change-Id: I882bf1cc9d9e6b587b5dc3d27cea1626f4dcc51a Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/northbridge.h 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/22635/1 diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 0cf9428..e3cd212 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -23,16 +23,16 @@ /* D18F0 - HT Configuration Registers */ #define D18F0_NODE_ID 0x60 #define D18F0_CPU_CNT 0x62 /* BKDG defines as a field in DWORD 0x60 */ -# define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ +#define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ /* D18F1 - Address Map Registers */ /* MMIO base and limit */ #define D18F1_MMIO_BASE0_LO 0x80 -# define MMIO_WE (1 << 1) -# define MMIO_RE (1 << 0) +#define MMIO_WE BIT(1) +#define MMIO_RE BIT(0) #define D18F1_MMIO_LIMIT0_LO 0x84 -# define MMIO_NP (1 << 7) +#define MMIO_NP BIT(7) #define D18F1_MMIO_BASELIM0_HI 0x180 #define D18F1_MMIO_BASE8_LO 0x1a0 #define D18F1_MMIO_LIMIT8_LO 0x1a4 @@ -48,17 +48,17 @@ - 8 * sizeof(uint32_t))) /* I/O base and limit */ #define D18F1_IO_BASE0 0xc0 -# define IO_WE (1 << 1) -# define IO_RE (1 << 0) +#define IO_WE BIT(1) +#define IO_RE BIT(0) #define D18F1_IO_LIMIT0 0xc4 #define NB_IO_BASE(reg) ((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0) #define NB_IO_LIMIT(reg) (NB_IO_BASE(reg) + sizeof(uint32_t)) #define D18F1_DRAM_HOLE 0xf0 -# define DRAM_HOIST_VALID (1 << 1) -# define DRAM_HOLE_VALID (1 << 0) +#define DRAM_HOIST_VALID BIT(1) +#define DRAM_HOLE_VALID BIT(0) #define D18F1_VGAEN 0xf4 -# define VGA_ADDR_ENABLE (1 << 0) +#define VGA_ADDR_ENABLE BIT(0) enum { /* SMM handler area. */ -- To view, visit https://review.coreboot.org/22635 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I882bf1cc9d9e6b587b5dc3d27cea1626f4dcc51a Gerrit-Change-Number: 22635 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Fix guarded code in ACPI ASL
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22634 ) Change subject: soc/amd/stoneyridge: Fix guarded code in ACPI ASL ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18769/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63905/ : SUCCESS -- To view, visit https://review.coreboot.org/22634 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I71c6acb235df9aa8642dca4c85d2bf604e244bf4 Gerrit-Change-Number: 22634 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)scarletltd.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 19:53:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Fix guarded code in ACPI ASL
by John E. Kabat Jr. (Code Review) 29 Nov '17

29 Nov '17

John E. Kabat Jr. has uploaded this change for review. ( https://review.coreboot.org/22634 Change subject: soc/amd/stoneyridge: Fix guarded code in ACPI ASL ...................................................................... soc/amd/stoneyridge: Fix guarded code in ACPI ASL Remove #if statements in sb_pci0_fch as Stoneyridge does not support IMC. Change sleepstates.asl to remove #if and change to: If (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) Change-Id: I71c6acb235df9aa8642dca4c85d2bf604e244bf4 Signed-off-by: John E. Kabat Jr <john.kabat(a)scarletltd.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/sleepstates.asl 2 files changed, 5 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/22634/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 216b57c..4aba2f9 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -155,13 +155,6 @@ /* Determine the OS we're running on */ OSFL() -#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) - /* TODO: It is unstable. */ - #include "acpi/AmdImc.asl" -#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) - ITZE() /* enable IMC Fan Control*/ -#endif -#endif } /* End Method(_SB._INI) */ Method(OSFL, 0){ diff --git a/src/soc/amd/stoneyridge/acpi/sleepstates.asl b/src/soc/amd/stoneyridge/acpi/sleepstates.asl index 2f36738..9bcf15f 100644 --- a/src/soc/amd/stoneyridge/acpi/sleepstates.asl +++ b/src/soc/amd/stoneyridge/acpi/sleepstates.asl @@ -15,11 +15,11 @@ */ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -Name (SSFG, 0x0D) -#else -Name (SSFG, 0x09) -#endif +Name(SSFG, 0x09) +if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + Store(0x0D, SSFG) +} + /* Supported sleep states: */ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ -- To view, visit https://review.coreboot.org/22634 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I71c6acb235df9aa8642dca4c85d2bf604e244bf4 Gerrit-Change-Number: 22634 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com>

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Change in coreboot[master]: southbridge/amd/pi/hudson/imc.c: fix out of bounds read
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22619 ) Change subject: southbridge/amd/pi/hudson/imc.c: fix out of bounds read ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18768/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63904/ : SUCCESS -- To view, visit https://review.coreboot.org/22619 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic16edc607358b9a688151735e6fcb3393d3bce80 Gerrit-Change-Number: 22619 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 19:33:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge/lpc.c: Use new wide IO functions
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22574 ) Change subject: amd/stoneyridge/lpc.c: Use new wide IO functions ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18767/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63903/ : SUCCESS -- To view, visit https://review.coreboot.org/22574 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8533e8ff766df8a8261298559aace7666487826d Gerrit-Change-Number: 22574 Gerrit-PatchSet: 4 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 19:31:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Delete early_setup.c
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22569 ) Change subject: amd/stoneyridge: Delete early_setup.c ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18766/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63902/ : SUCCESS -- To view, visit https://review.coreboot.org/22569 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3 Gerrit-Change-Number: 22569 Gerrit-PatchSet: 4 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 19:15:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: kahlee/ec.c: Use new wide IO function
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22591 ) Change subject: kahlee/ec.c: Use new wide IO function ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18765/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63901/ : SUCCESS -- To view, visit https://review.coreboot.org/22591 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74 Gerrit-Change-Number: 22591 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 18:01:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Create new wide IO functions
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22590 ) Change subject: amd/stoneyridge: Create new wide IO functions ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18764/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63900/ : SUCCESS -- To view, visit https://review.coreboot.org/22590 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 Gerrit-Change-Number: 22590 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 17:58:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add Intel SRAM common code support
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22607 ) Change subject: soc/intel/common: Add Intel SRAM common code support ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18763/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63899/ : SUCCESS -- To view, visit https://review.coreboot.org/22607 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a Gerrit-Change-Number: 22607 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 17:46:00 +0000 Gerrit-HasComments: No

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coreboot-gerrit November 2017