coreboot-gerrit November 2017

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Change in coreboot[master]: pcengines/apu2: add support for apu4 variant
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22629 ) Change subject: pcengines/apu2: add support for apu4 variant ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/63892/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/18757/ : SUCCESS -- To view, visit https://review.coreboot.org/22629 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia7a9971d25d4ecc215c392be1e46dc1c10129ba7 Gerrit-Change-Number: 22629 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Kamil Wcisło <kamil.wcislo(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 15:44:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: pcengines/apu2: add support for apu4 variant
by Piotr Król (Code Review) 29 Nov '17

29 Nov '17

Piotr Król has uploaded this change for review. ( https://review.coreboot.org/22629 Change subject: pcengines/apu2: add support for apu4 variant ...................................................................... pcengines/apu2: add support for apu4 variant apu4 is new version of PC Engines platform, which contain 4 Ethernet port and 4GB of RAM. In functional way it is very similar to apu3. Change-Id: Ia7a9971d25d4ecc215c392be1e46dc1c10129ba7 Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Kconfig.name M src/mainboard/pcengines/apu2/board_info.txt M src/mainboard/pcengines/apu2/romstage.c A src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb 5 files changed, 109 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/22629/1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 432963e..f9a87dd 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -14,7 +14,8 @@ # GNU General Public License for more details. # -if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU5 +if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ + BOARD_PCENGINES_APU5 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -41,6 +42,7 @@ string default "apu2" if BOARD_PCENGINES_APU2 default "apu3" if BOARD_PCENGINES_APU3 + default "apu4" if BOARD_PCENGINES_APU4 default "apu5" if BOARD_PCENGINES_APU5 config DEVICETREE @@ -51,6 +53,7 @@ string default "apu2" if BOARD_PCENGINES_APU2 default "apu3" if BOARD_PCENGINES_APU3 + default "apu4" if BOARD_PCENGINES_APU4 default "apu5" if BOARD_PCENGINES_APU5 config MAX_CPUS @@ -76,7 +79,7 @@ choice prompt "J19 pins 1-10" default APU2_PINMUX_OFF_C if BOARD_PCENGINES_APU2 || \ - BOARD_PCENGINES_APU3 + BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 default APU2_PINMUX_UART_C if BOARD_PCENGINES_APU5 config APU2_PINMUX_OFF_C @@ -84,7 +87,8 @@ config APU2_PINMUX_GPIO0 bool "GPIO" - depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 + depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ + BOARD_PCENGINES_APU4 config APU2_PINMUX_UART_C bool "UART 0x3e8" @@ -94,7 +98,7 @@ choice prompt "J19 pins 11-20" default APU2_PINMUX_OFF_D if BOARD_PCENGINES_APU2 || \ - BOARD_PCENGINES_APU3 + BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 default APU2_PINMUX_UART_D if BOARD_PCENGINES_APU5 config APU2_PINMUX_OFF_D @@ -102,7 +106,8 @@ config APU2_PINMUX_GPIO1 bool "GPIO" - depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 + depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ + BOARD_PCENGINES_APU4 config APU2_PINMUX_UART_D bool "UART 0x2e8" diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name index 68e6d6e..45ec16f 100644 --- a/src/mainboard/pcengines/apu2/Kconfig.name +++ b/src/mainboard/pcengines/apu2/Kconfig.name @@ -4,5 +4,8 @@ config BOARD_PCENGINES_APU3 bool "APU3" +config BOARD_PCENGINES_APU4 + bool "APU4" + config BOARD_PCENGINES_APU5 bool "APU5" diff --git a/src/mainboard/pcengines/apu2/board_info.txt b/src/mainboard/pcengines/apu2/board_info.txt index f7d5172..ec2cc9d 100644 --- a/src/mainboard/pcengines/apu2/board_info.txt +++ b/src/mainboard/pcengines/apu2/board_info.txt @@ -1,4 +1,4 @@ -Board name: apu2 apu3 apu5 +Board name: apu2 apu3 apu4 apu5 Board URL: http://www.pcengines.ch/apu2c2.htm Category: half ROM package: SOIC-8 diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 1433518..6339d94 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -117,7 +117,8 @@ // Configure output disabled, value low, pull up/down disabled // if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) || - IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)) { + IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) || + IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) { configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting); } @@ -129,7 +130,8 @@ // Configure output enabled, value low, pull up/down disabled // setting = 0x1 << GPIO_OUTPUT_ENABLE; - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3)) { + if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) || + IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) { configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_33, Function0, GPIO_33, setting); } diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb new file mode 100644 index 0000000..9859255 --- /dev/null +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -0,0 +1,91 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/pi/00730F01/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00730F01 + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + + chip northbridge/amd/pi/00730F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 off end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # LAN1 + device pci 2.2 on end # LAN2 + device pci 2.3 on end # LAN3 + device pci 2.4 on end # LAN4 + device pci 2.5 on end # mPCIe slot 1 + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 + + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB EHCI0 usb[0:3] is connected + device pci 13.0 on end # USB EHCI1 usb[4:7] + device pci 14.0 on end # SM + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 on end + device pnp 2e.107 on end + device pnp 2e.607 off end + device pnp 2e.e off end + end # SIO NCT5104D + end # LPC 0x439d + + device pci 14.7 on end # SD + device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end #chip southbridge/amd/pi/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00730F01/root_complex -- To view, visit https://review.coreboot.org/22629 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia7a9971d25d4ecc215c392be1e46dc1c10129ba7 Gerrit-Change-Number: 22629 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com>

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Change in coreboot[master]: soc/intel/apollolake: Add PNP config
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22488 ) Change subject: soc/intel/apollolake: Add PNP config ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18756/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63891/ : SUCCESS -- To view, visit https://review.coreboot.org/22488 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Gerrit-Change-Number: 22488 Gerrit-PatchSet: 5 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 14:27:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Add PNP config
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22488 ) Change subject: soc/intel/apollolake: Add PNP config ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63889/ : SUCCESS -- To view, visit https://review.coreboot.org/22488 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Gerrit-Change-Number: 22488 Gerrit-PatchSet: 5 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 14:00:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Add PNP config
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22488 ) Change subject: soc/intel/apollolake: Add PNP config ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63890/ : SUCCESS -- To view, visit https://review.coreboot.org/22488 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Gerrit-Change-Number: 22488 Gerrit-PatchSet: 5 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 29 Nov 2017 13:59:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Add PNP config
by Divya Chellappa (Code Review) 29 Nov '17

29 Nov '17

Divya Chellappa has uploaded a new patch set (#5). ( https://review.coreboot.org/22488 ) Change subject: soc/intel/apollolake: Add PNP config ...................................................................... soc/intel/apollolake: Add PNP config 1. Programs PNP values for AUNIT, BUNIT & TUNIT registers as per reference code. 2. A new configuration option pnp_settings is introduced in devicetree.cb to select PNP settings among performance, power, power & performance. TEST = built and booted glkrvp, verfied that the callback gets control, verified warm and cold reboots. Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Signed-off-by: Divya Chellap <divya.chellappa(a)intel.com> --- M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/include/soc/pcr_ids.h A src/soc/intel/apollolake/include/soc/pnpconfig.h A src/soc/intel/apollolake/pnpconfig.c 6 files changed, 857 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/22488/5 -- To view, visit https://review.coreboot.org/22488 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Gerrit-Change-Number: 22488 Gerrit-PatchSet: 5 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common PMC common block
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22565 ) Change subject: soc/intel/skylake: Make use of Intel common PMC common block ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18755/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63888/ : SUCCESS -- To view, visit https://review.coreboot.org/22565 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042bf62407b0acee3d24fbba2de2d482c3fbff9a Gerrit-Change-Number: 22565 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 29 Nov 2017 12:57:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common PMC common block
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22565 ) Change subject: soc/intel/skylake: Make use of Intel common PMC common block ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18754/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63887/ : SUCCESS -- To view, visit https://review.coreboot.org/22565 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042bf62407b0acee3d24fbba2de2d482c3fbff9a Gerrit-Change-Number: 22565 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 29 Nov 2017 12:49:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PMC controller support
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22563 ) Change subject: soc/intel/common/block: Add Intel common PMC controller support ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18753/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63886/ : SUCCESS -- To view, visit https://review.coreboot.org/22563 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Gerrit-Change-Number: 22563 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 29 Nov 2017 12:47:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Set low maximum temperature threshold for Thermal ...
by build bot (Jenkins) (Code Review) 29 Nov '17

29 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22419 ) Change subject: soc/intel/skylake: Set low maximum temperature threshold for Thermal Device ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18752/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63885/ : SUCCESS -- To view, visit https://review.coreboot.org/22419 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610 Gerrit-Change-Number: 22419 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Rushikesh S Kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 29 Nov 2017 11:33:53 +0000 Gerrit-HasComments: No

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coreboot-gerrit November 2017