coreboot-gerrit November 2017

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Change in coreboot[master]: nvramtool: Add dummy cmos-hw-unix accessor implementation for non-x86
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22562 ) Change subject: nvramtool: Add dummy cmos-hw-unix accessor implementation for non-x86 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18574/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63677/ : SUCCESS -- To view, visit https://review.coreboot.org/22562 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I75e4a1a0cbd35ca40f7b108658686839ccf9784a Gerrit-Change-Number: 22562 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 13:39:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Make use of Intel common PMC common block
by Subrata Banik (Code Review) 22 Nov '17

22 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22566 Change subject: soc/intel/cannonlake: Make use of Intel common PMC common block ...................................................................... soc/intel/cannonlake: Make use of Intel common PMC common block TEST=Build and boot cannonlake rvp. Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/pmc.c 1 file changed, 12 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/22566/1 diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index a0d816e..66ec844 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -18,73 +18,21 @@ #include <chip.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <arch/acpi.h> -#include <cpu/cpu.h> -#include <intelblocks/pcr.h> +#include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> -#include <pc80/mc146818rtc.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <cpu/x86/smm.h> -#include <soc/pcr_ids.h> -#include <soc/ramstage.h> -#include <security/vboot/vbnv.h> -#include <security/vboot/vbnv_layout.h> -static void pch_pmc_add_mmio_resources(device_t dev) +/* Fill up PMC resource structure */ +void soc_pch_pmc_get_resources(struct pmc_resource_config *cfg) { - struct resource *res; - - /* Memory-mmapped I/O registers. */ - res = new_resource(dev, PWRMBASE); - res->base = PCH_PWRM_BASE_ADDRESS; - res->size = PCH_PWRM_BASE_SIZE; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; -} - -static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index) -{ - struct resource *res; - res = new_resource(dev, index); - res->base = base; - res->size = size; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void pch_pmc_add_io_resources(device_t dev) -{ - /* PMBASE */ - pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); -} - -static void pch_pmc_read_resources(device_t dev) -{ - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add non-standard MMIO resources. */ - pch_pmc_add_mmio_resources(dev); - - /* Add IO resources. */ - pch_pmc_add_io_resources(dev); -} - -static void pch_set_acpi_mode(void) -{ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); - printk(BIOS_DEBUG, "done.\n"); - } + cfg->pwrmbase_offset = PWRMBASE; + cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS; + cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE; + cfg->abase_offset = ABASE; + cfg->abase_addr = ACPI_BASE_ADDRESS; + cfg->abase_size = ACPI_BASE_SIZE; } static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) @@ -128,37 +76,18 @@ write32(pmcbase + DSX_CFG, reg); } -static void pmc_init(struct device *dev) +void pmc_init(struct device *dev) { - config_t *config = dev->chip_info; + const config_t *config = dev->chip_info; rtc_init(); /* Initialize power management */ pmc_gpe_init(); - pch_set_acpi_mode(); + pmc_set_acpi_mode(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); config_deep_sx(config->deep_sx_config); } - -static struct device_operations device_ops = { - .read_resources = &pch_pmc_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &pmc_init, - .scan_bus = &scan_lpc_bus, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_INTEL_CNL_PMC, - 0 -}; - -static const struct pci_driver pch_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/22566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4 Gerrit-Change-Number: 22566 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common PMC common block
by Subrata Banik (Code Review) 22 Nov '17

22 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22565 Change subject: soc/intel/skylake: Make use of Intel common PMC common block ...................................................................... soc/intel/skylake: Make use of Intel common PMC common block TEST=Build and boot soraka/eve Change-Id: I042bf62407b0acee3d24fbba2de2d482c3fbff9a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/romstage/Makefile.inc D src/soc/intel/skylake/romstage/pmc.c 4 files changed, 36 insertions(+), 134 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/22565/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index da45ec5..0f9a417 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -37,6 +37,7 @@ romstage-y += me.c romstage-y += pch.c romstage-y += pei_data.c +romstage-y += pmc.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += spi.c diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 9c05ff6..9d9d96f 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,25 +18,35 @@ #include <chip.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <arch/acpi.h> -#include <cpu/cpu.h> -#include <intelblocks/pcr.h> +#include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> -#include <pc80/mc146818rtc.h> +#include <intelblocks/rtc.h> #include <reg_script.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/pmc.h> -#include <cpu/x86/smm.h> -#include <soc/pcr_ids.h> -#include <soc/ramstage.h> + +void pmc_set_disb(void) +{ + /* Set the DISB after DRAM init */ + u32 disb_val = 0; + disb_val = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); + disb_val |= DISB; + + /* Don't clear bits that are write-1-to-clear */ + disb_val &= ~(GBL_RST_STS | MS4V); + pci_write_config32(PCH_DEV_PMC, GEN_PMCON_A, disb_val); +} + +/* Fill up PMC resource structure */ +void soc_pch_pmc_get_resources(struct pmc_resource_config *cfg) +{ + cfg->pwrmbase_offset = PWRMBASE; + cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS; + cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE; + cfg->abase_offset = ABASE; + cfg->abase_addr = ACPI_BASE_ADDRESS; + cfg->abase_size = ACPI_BASE_SIZE; +} static const struct reg_script pch_pmc_misc_init_script[] = { /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ @@ -58,68 +68,11 @@ REG_SCRIPT_END }; -static void pch_pmc_add_mmio_resources(device_t dev) -{ - struct resource *res; - - /* Memory-mmapped I/O registers. */ - res = new_resource(dev, PWRMBASE); - res->base = PCH_PWRM_BASE_ADDRESS; - res->size = PCH_PWRM_BASE_SIZE; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; -} - -static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index) -{ - struct resource *res; - res = new_resource(dev, index); - res->base = base; - res->size = size; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void pch_pmc_add_io_resources(device_t dev) -{ - /* PMBASE */ - pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); -} - -static void pch_pmc_read_resources(device_t dev) -{ - /* Get the normal PCI resources of this device. */ - pci_dev_read_resources(dev); - - /* Add non-standard MMIO resources. */ - pch_pmc_add_mmio_resources(dev); - - /* Add IO resources. */ - pch_pmc_add_io_resources(dev); -} - -static void pch_set_acpi_mode(void) -{ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); - printk(BIOS_DEBUG, "done.\n"); - } -} - -static void pch_rtc_init(void) -{ - /* Ensure the date is set including century byte. */ - cmos_check_update_date(); - - cmos_init(rtc_failure()); -} - static void pch_power_options(void) { u16 reg16; const char *state; - /*PMC Controller Device 0x1F, Func 02*/ - device_t dev = PCH_DEV_PMC; + /* Get the chip configuration */ int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; @@ -133,7 +86,7 @@ /*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/ //get_option(&pwr_on, "power_on_after_fail"); pwr_on = MAINBOARD_POWER_ON; - reg16 = pci_read_config16(dev, GEN_PMCON_B); + reg16 = pci_read_config16(PCH_DEV_PMC, GEN_PMCON_B); reg16 &= 0xfffe; switch (pwr_on) { case MAINBOARD_POWER_OFF: @@ -151,7 +104,7 @@ default: state = "undefined"; } - pci_write_config16(dev, GEN_PMCON_B, reg16); + pci_write_config16(PCH_DEV_PMC, GEN_PMCON_B, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up GPE configuration. */ @@ -199,45 +152,24 @@ write32(pmcbase + DSX_CFG, reg); } -static void pmc_init(struct device *dev) +void pmc_init(struct device *dev) { - config_t *config = dev->chip_info; + const config_t *config = dev->chip_info; - pch_rtc_init(); + rtc_init(); /* Initialize power management */ pch_power_options(); /* Note that certain bits may be cleared from running script as * certain bit fields are write 1 to clear. */ - reg_script_run_on_dev(dev, pch_pmc_misc_init_script); - pch_set_acpi_mode(); + reg_script_run_on_dev(PCH_DEV_PMC, pch_pmc_misc_init_script); + pmc_set_acpi_mode(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); config_deep_sx(config->deep_sx_config); /* Clear registers that contain write-1-to-clear bits. */ - reg_script_run_on_dev(dev, pmc_write1_to_clear_script); + reg_script_run_on_dev(PCH_DEV_PMC, pmc_write1_to_clear_script); } - -static struct device_operations device_ops = { - .read_resources = &pch_pmc_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &pmc_init, - .scan_bus = &scan_lpc_bus, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d21, - 0xa121, - 0 -}; - -static const struct pci_driver pch_lpc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 6dbe718..8bfbfea 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,5 +1,4 @@ romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S -romstage-y += pmc.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/pmc.c b/src/soc/intel/skylake/romstage/pmc.c deleted file mode 100644 index e9d06f2..0000000 --- a/src/soc/intel/skylake/romstage/pmc.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/pci_devs.h> -#include <soc/pm.h> - -void pmc_set_disb(void) -{ - /* Set the DISB after DRAM init */ - u32 disb_val = 0; - pci_devfn_t dev = PCH_DEV_PMC; - disb_val = pci_read_config32(dev, GEN_PMCON_A); - disb_val |= DISB; - - /* Don't clear bits that are write-1-to-clear */ - disb_val &= ~(GBL_RST_STS | MS4V); - pci_write_config32(dev, GEN_PMCON_A, disb_val); -} -- To view, visit https://review.coreboot.org/22565 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I042bf62407b0acee3d24fbba2de2d482c3fbff9a Gerrit-Change-Number: 22565 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Make use of Intel common PMC common block
by Subrata Banik (Code Review) 22 Nov '17

22 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22564 Change subject: soc/intel/apollolake: Make use of Intel common PMC common block ...................................................................... soc/intel/apollolake: Make use of Intel common PMC common block TEST=Build and boot reef Change-Id: I968c88ef805fe58751f5359e27cbdf4d3fba3ae9 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/pmc.c 1 file changed, 14 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/22564/1 diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index a4b91e1..36f5c1d 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2017 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -15,74 +15,25 @@ * GNU General Public License for more details. */ +#include "chip.h" +#include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> -#include <console/console.h> -#include <cpu/x86/smm.h> +#include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <soc/iomap.h> -#include <soc/gpio.h> -#include <soc/pci_devs.h> #include <soc/pm.h> #include <timer.h> -#include "chip.h" -/* - * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've observed cases - * where the BAR reads back as 0, but the IO window is open. This also means - * that it will not respond to PCI probing. In the event that probing the BAR - * fails, we still need to create a resource for it. - */ -static void read_resources(device_t dev) +/* Fill up PMC resource structure */ +void soc_pch_pmc_get_resources(struct pmc_resource_config *cfg) { - struct resource *res; - pci_dev_read_resources(dev); - - res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = PMC_BAR0; - res->size = PMC_BAR0_SIZE; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = ACPI_BASE_ADDRESS; - res->size = ACPI_BASE_SIZE; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -/* - * Part 2: - * Resources are assigned, and no other device was given an IO resource to - * overlap with our ACPI BAR. But because the resource is FIXED, - * pci_dev_set_resources() will not store it for us. We need to do that - * explicitly. - */ -static void set_resources(device_t dev) -{ - struct resource *res; - - pci_dev_set_resources(dev); - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - pci_write_config32(dev, res->index, res->base); - dev->command |= PCI_COMMAND_MEMORY; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, " PMC BAR"); - - res = find_resource(dev, PCI_BASE_ADDRESS_4); - pci_write_config32(dev, res->index, res->base); - dev->command |= PCI_COMMAND_IO; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, " ACPI BAR"); -} - -static void pch_set_acpi_mode(void) -{ - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); - printk(BIOS_DEBUG, "Done.\n"); - } + cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0; + cfg->pwrmbase_addr = PMC_BAR0; + cfg->pwrmbase_size = PMC_BAR0_SIZE; + cfg->abase_offset = PCI_BASE_ADDRESS_4; + cfg->abase_addr = ACPI_BASE_ADDRESS; + cfg->abase_size = ACPI_BASE_SIZE; } static int choose_slp_s3_assertion_width(int width_usecs) @@ -138,14 +89,14 @@ write32((void *)gen_pmcon3, reg); } -static void pmc_init(struct device *dev) +void pmc_init(struct device *dev) { const struct soc_intel_apollolake_config *cfg = dev->chip_info; /* Set up GPE configuration */ pmc_gpe_init(); pmc_fixup_power_state(); - pch_set_acpi_mode(); + pmc_set_acpi_mode(); if (cfg != NULL) set_slp_s3_assertion_width(cfg->slp_s3_assertion_width_usecs); @@ -156,22 +107,3 @@ /* Now that things have been logged clear out the PMC state. */ pmc_clear_prsts(); } - -static const struct device_operations device_ops = { - .read_resources = read_resources, - .set_resources = set_resources, - .enable_resources = pci_dev_enable_resources, - .init = &pmc_init, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_INTEL_APL_PMC, - PCI_DEVICE_ID_INTEL_GLK_PMC, - 0, -}; - -static const struct pci_driver pmc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices= pci_device_ids, -}; -- To view, visit https://review.coreboot.org/22564 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I968c88ef805fe58751f5359e27cbdf4d3fba3ae9 Gerrit-Change-Number: 22564 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PMC controller support
by Subrata Banik (Code Review) 22 Nov '17

22 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22563 Change subject: soc/intel/common/block: Add Intel common PMC controller support ...................................................................... soc/intel/common/block: Add Intel common PMC controller support SoC need to select specific macros to compile commom PMC code. Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/common/block/pmc/Makefile.inc A src/soc/intel/common/block/pmc/pmc.c 3 files changed, 178 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/22563/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h new file mode 100644 index 0000000..f693b51 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_PMC_H +#define SOC_INTEL_COMMON_BLOCK_PMC_H + +#include <device/device.h> +#include <stdint.h> + +/* + * SoC overrides + * + * All new SoC must implement below functionality. + */ + +/* Function to initialize PMC controller. + * + * This initialization may differ between different SoC + * + * Input: Device Structure PMC PCI device + */ +void pmc_init(struct device *dev); + +/* PMC controller resource structure */ +struct pmc_resource_config { + uint8_t pwrmbase_offset; + uintptr_t pwrmbase_addr; + size_t pwrmbase_size; + uint8_t abase_offset; + uintptr_t abase_addr; + size_t abase_size; +}; + +/* + * SoC should fill this structure information based on + * PMC controller register information like PWRMBASE, ABASE offset + * BAR and Size + */ +void soc_pch_pmc_get_resources(struct pmc_resource_config *cfg); + +/* API to set ACPI mode */ +void pmc_set_acpi_mode(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc index 40fcba1..2253115 100644 --- a/src/soc/intel/common/block/pmc/Makefile.inc +++ b/src/soc/intel/common/block/pmc/Makefile.inc @@ -1,5 +1,8 @@ -bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c -smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c -verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC),y) +bootblock-y += pmclib.c +romstage-y += pmclib.c +ramstage-y += pmc.c +ramstage-y += pmclib.c +smm-y += pmclib.c +verstage-y += pmclib.c +endif diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c new file mode 100644 index 0000000..a4b2960 --- /dev/null +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/pmc.h> +#include <soc/pci_devs.h> + +/* SoC overrides */ + +/* Fill up PMC resource structure inside SoC directory */ +__attribute__((weak)) void soc_pch_pmc_get_resources( + struct pmc_resource_config *cfg) +{ + /* no-op */ +} + +/* SoC override PMC initialization */ +__attribute__((weak)) void pmc_init(struct device *dev) +{ + /* no-op */ +} + +static void pch_pmc_add_mmio_resources(device_t dev, uint8_t offset, + uintptr_t pwrm_base, size_t pwrm_size) +{ + struct resource *res; + + /* Memory-mapped I/O registers. */ + res = new_resource(dev, offset); + res->base = pwrm_base; + res->size = pwrm_size; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED | IORESOURCE_RESERVE; +} + +static void pch_pmc_add_io_resources(device_t dev, uint8_t offset, + uintptr_t abase, size_t size) +{ + struct resource *res; + + res = new_resource(dev, offset); + res->base = abase; + res->size = size; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void pch_pmc_read_resources(device_t dev) +{ + static struct pmc_resource_config *config; + + soc_pch_pmc_get_resources(config); + + if (!config->pwrmbase_offset) + die("Unable to get PMC controller resource information!"); + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add non-standard MMIO resources. */ + pch_pmc_add_mmio_resources(dev, config->pwrmbase_offset, + config->pwrmbase_addr, config->pwrmbase_size); + + /* Add IO resources. */ + pch_pmc_add_io_resources(dev, config->abase_offset, + config->abase_addr, config->abase_size); +} + +void pmc_set_acpi_mode(void) +{ + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); + printk(BIOS_DEBUG, "done.\n"); + } +} + +static struct device_operations device_ops = { + .read_resources = &pch_pmc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .init = &pmc_init, + .scan_bus = &scan_lpc_bus, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_LP_PMC, + PCI_DEVICE_ID_INTEL_KBP_H_PMC, + PCI_DEVICE_ID_INTEL_APL_PMC, + PCI_DEVICE_ID_INTEL_GLK_PMC, + PCI_DEVICE_ID_INTEL_CNL_PMC, + 0 +}; + +static const struct pci_driver pch_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/22563 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Gerrit-Change-Number: 22563 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: nvramtool: Add dummy cmos-hw-unix accessor implementation for non-x86
by Paul Kocialkowski (Code Review) 22 Nov '17

22 Nov '17

Paul Kocialkowski has uploaded this change for review. ( https://review.coreboot.org/22562 Change subject: nvramtool: Add dummy cmos-hw-unix accessor implementation for non-x86 ...................................................................... nvramtool: Add dummy cmos-hw-unix accessor implementation for non-x86 The default implementation uses inb/outb, that is not available on ARM platforms and others. A dummy implementation allows building nvramtool on these platforms. Change-Id: I75e4a1a0cbd35ca40f7b108658686839ccf9784a Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- M util/nvramtool/accessors/cmos-hw-unix.c 1 file changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/22562/1 diff --git a/util/nvramtool/accessors/cmos-hw-unix.c b/util/nvramtool/accessors/cmos-hw-unix.c index acefdf7..33d6994 100644 --- a/util/nvramtool/accessors/cmos-hw-unix.c +++ b/util/nvramtool/accessors/cmos-hw-unix.c @@ -11,7 +11,7 @@ #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); }) #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); }) #else -#if defined(__GLIBC__) +#if defined(__GLIBC__) && (defined(__i386__) || defined(__x86_64__)) #include <sys/io.h> #endif #if (defined(__MACH__) && defined(__APPLE__)) @@ -76,6 +76,8 @@ static unsigned char cmos_hal_read(unsigned addr); static void cmos_hal_write(unsigned addr, unsigned char value); static void cmos_set_iopl(int level); + +#if defined(__i386__) || defined(__x86_64__) /* no need to initialize anything */ static void cmos_hal_init(__attribute__((unused)) void *data) @@ -160,6 +162,32 @@ #endif } +#else + +/* no need to initialize anything */ +static void cmos_hal_init(__attribute__((unused)) void *data) +{ + return; +} + +static unsigned char cmos_hal_read(__attribute__((unused)) unsigned index) +{ + return; +} + +static void cmos_hal_write(__attribute__((unused)) unsigned index, + __attribute__((unused)) unsigned char value) +{ + return; +} + +static void cmos_set_iopl(__attribute__((unused)) int level) +{ + return; +} + +#endif + cmos_access_t cmos_hal = { .init = cmos_hal_init, .read = cmos_hal_read, -- To view, visit https://review.coreboot.org/22562 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I75e4a1a0cbd35ca40f7b108658686839ccf9784a Gerrit-Change-Number: 22562 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr>

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Change in coreboot[master]: soc/intel/apollolake: Add PNP config
by Divya Chellappa (Code Review) 22 Nov '17

22 Nov '17

Divya Chellappa has uploaded a new patch set (#4). ( https://review.coreboot.org/22488 ) Change subject: soc/intel/apollolake: Add PNP config ...................................................................... soc/intel/apollolake: Add PNP config 1. Programs PNP values for AUNIT, BUNIT & TUNIT registers as per reference code. 2. A new Kconfig option PNP_SETTINGS is introduced to select PNP settings among performance, power, power & performance. TEST = built and booted glkrvp, verfied that the callback gets control, verified warm and cold reboots. Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Signed-off-by: Divya Chellap <divya.chellappa(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc A src/soc/intel/apollolake/include/soc/pnpconfig.h A src/soc/intel/apollolake/pnpconfig.c 4 files changed, 851 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/22488/4 -- To view, visit https://review.coreboot.org/22488 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Gerrit-Change-Number: 22488 Gerrit-PatchSet: 4 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/scarlet: support kd097d04 panel
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22472 ) Change subject: google/scarlet: support kd097d04 panel ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18571/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63673/ : SUCCESS -- To view, visit https://review.coreboot.org/22472 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie8bc0cbb79840f1924a8cc111f2511292203731f Gerrit-Change-Number: 22472 Gerrit-PatchSet: 9 Gerrit-Owner: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sean Paul <seanpaul(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey yang <nickey.yang(a)rock-chips.com> Gerrit-Comment-Date: Wed, 22 Nov 2017 09:02:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/gru: correct backlight gpio
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22529 ) Change subject: google/gru: correct backlight gpio ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18572/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63674/ : SUCCESS -- To view, visit https://review.coreboot.org/22529 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7c5abfd5bbbae015b899f3edc8892ea32bf82463 Gerrit-Change-Number: 22529 Gerrit-PatchSet: 6 Gerrit-Owner: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 08:57:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Rename board_id to memory_sku
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22561 ) Change subject: google/kahlee: Rename board_id to memory_sku ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18570/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63672/ : SUCCESS -- To view, visit https://review.coreboot.org/22561 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I84bacead3daf829c97f595c4c11a243953243c29 Gerrit-Change-Number: 22561 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 07:55:54 +0000 Gerrit-HasComments: No

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