coreboot-gerrit November 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: lib/spd_bin: Only build when CONFIG option is set
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22575 ) Change subject: lib/spd_bin: Only build when CONFIG option is set ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/63688/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/18584/ : SUCCESS -- To view, visit https://review.coreboot.org/22575 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97a4d810199c96912d13737046e6041b74315164 Gerrit-Change-Number: 22575 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Nov 2017 00:43:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge/lpc.c: Use new wide IO functions
by Marc Jones (Code Review) 22 Nov '17

22 Nov '17

Marc Jones has posted comments on this change. ( https://review.coreboot.org/22574 ) Change subject: amd/stoneyridge/lpc.c: Use new wide IO functions ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/22574/1/src/soc/amd/stoneyridge/lpc.c File src/soc/amd/stoneyridge/lpc.c: https://review.coreboot.org/#/c/22574/1/src/soc/amd/stoneyridge/lpc.c@256 PS1, Line 256: function_ret = sb_find_wideio_range(base, end); this should be a better name. In this case wideio_size or something. https://review.coreboot.org/#/c/22574/1/src/soc/amd/stoneyridge/lpc.c@269 PS1, Line 269: function_ret and this should be wideio_range -- To view, visit https://review.coreboot.org/22574 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8533e8ff766df8a8261298559aace7666487826d Gerrit-Change-Number: 22574 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Nov 2017 00:42:57 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c
by Marc Jones (Code Review) 22 Nov '17

22 Nov '17

Marc Jones has posted comments on this change. ( https://review.coreboot.org/22568 ) Change subject: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c ...................................................................... Patch Set 1: This should be two patches. One for the transfer and one for new functions. -- To view, visit https://review.coreboot.org/22568 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Gerrit-Change-Number: 22568 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Nov 2017 00:40:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: lib/spd_bin: Only build when CONFIG option is set
by Marc Jones (Code Review) 22 Nov '17

22 Nov '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22575 Change subject: lib/spd_bin: Only build when CONFIG option is set ...................................................................... lib/spd_bin: Only build when CONFIG option is set Only build spd_bin.c when GENERIC_SPD_BIN is selected. This issue was found by Coverity scan, which fails 10 test when the dependent MAX_DIMMS KCONFIG option is not built. BUG=b:69669995 TEST=Build test. Change-Id: I97a4d810199c96912d13737046e6041b74315164 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/lib/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/22575/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 25537d2..a041b32 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -309,9 +309,10 @@ endif # CONFIG_RAMSTAGE_LIBHWBASE -romstage-y += spd_bin.c ifeq ($(CONFIG_GENERIC_SPD_BIN),y) +romstage-y += spd_bin.c + LIB_SPD_BIN = $(obj)/spd.bin LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) -- To view, visit https://review.coreboot.org/22575 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I97a4d810199c96912d13737046e6041b74315164 Gerrit-Change-Number: 22575 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: amd/stoneyridge: Delete early_setup.c
by Martin Roth (Code Review) 22 Nov '17

22 Nov '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/22569 ) Change subject: amd/stoneyridge: Delete early_setup.c ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/22569/1/src/mainboard/google/kahlee/ec.c File src/mainboard/google/kahlee/ec.c: https://review.coreboot.org/#/c/22569/1/src/mainboard/google/kahlee/ec.c@55 PS1, Line 55: printk(BIOS_DEBUG, "Failed to assign a range\n"); What's the impact of a failure here? Should this maybe be a higher debug level than BIOS_DEBUG? printk(BIOS_WARNING, "ERROR: Failed to assign a range\n"); die("ERROR: Failed to assign a range\n"); -- To view, visit https://review.coreboot.org/22569 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3 Gerrit-Change-Number: 22569 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 23 Nov 2017 00:15:04 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: util/crossgcc: Install a template for the edk2 build system
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22570 ) Change subject: util/crossgcc: Install a template for the edk2 build system ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18582/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63686/ : SUCCESS https://qa.coreboot.org/job/coreboot-toolchain/389/ : SUCCESS -- To view, visit https://review.coreboot.org/22570 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I76b38c928b831ee6f31450aa0ad59b4f906f394d Gerrit-Change-Number: 22570 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 23:11:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge/lpc.c: Use new wide IO functions
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22574 ) Change subject: amd/stoneyridge/lpc.c: Use new wide IO functions ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18583/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63687/ : SUCCESS -- To view, visit https://review.coreboot.org/22574 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8533e8ff766df8a8261298559aace7666487826d Gerrit-Change-Number: 22574 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 22:37:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge/lpc.c: Use new wide IO functions
by Richard Spiegel (Code Review) 22 Nov '17

22 Nov '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22574 Change subject: amd/stoneyridge/lpc.c: Use new wide IO functions ...................................................................... amd/stoneyridge/lpc.c: Use new wide IO functions Use the new wide IO functions from southbridge.c to simplify code in functions set_child_resource and lpc_enable_childrens_resources. BUG=b:64033893 Change-Id: I8533e8ff766df8a8261298559aace7666487826d Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/lpc.c 1 file changed, 24 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/22574/1 diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 3cd9acb..5450469 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -158,39 +158,14 @@ pci_dev_set_resources(dev); } -/* - * Structure to simplify code obtaining the total of used wide IO - * registers and the size assigned to each. Used on set_child_resource - * and lpc_enable_childrens_resources. - */ -struct _wide_IO_enable_bits { - u32 enable[3]; - u8 alt[3]; -} wio_en = { - { - LPC_WIDEIO0_ENABLE, - LPC_WIDEIO1_ENABLE, - LPC_WIDEIO2_ENABLE - }, - { - LPC_ALT_WIDEIO0_ENABLE, - LPC_ALT_WIDEIO1_ENABLE, - LPC_ALT_WIDEIO2_ENABLE - } -}; - static void set_child_resource(device_t child, - int *wio_total_ptr, - u16 *reg_var, u32 *reg, - u32 *reg_x, - u8 *wiosize) + u32 *reg_x) { struct resource *res; u32 base, end; u32 rsize = 0, set = 0, set_x = 0; - int i, wio_total = *wio_total_ptr; - u16 reg_size[3]; + uint8_t function_ret; /* * Be a bit relaxed, tolerate that LPC region might be bigger than @@ -202,17 +177,6 @@ * will verify if required region was previously set and will avoid * setting a new wide IO resource if one is already set. */ - - /* - * For each wideIO get the current size, 16, 512, - * or 0 if it isn't used. - */ - for (i = 0; i < 3; i++) { - if (i < wio_total) /* convert to index */ - reg_size[i] = (*wiosize & wio_en.alt[i]) ? 16 : 512; - else - reg_size[i] = 0; - } for (res = child->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_IO)) @@ -289,18 +253,11 @@ break; default: rsize = 0; - if (wio_total > 0) { - for (i = 0; i < wio_total; i++) { - if ((base >= reg_var[i]) && - ((base + res->size) <= - (reg_var[i] + reg_size[i]))) { - rsize = reg_size[i]; - printk(BIOS_DEBUG, - "Covered by wideIO"); - printk(BIOS_DEBUG, " %d\n", i); - break; - } - } + function_ret = sb_find_wideio_range(base, end); + if (function_ret != WIDE_IO_RANGE_FAILED) { + rsize = sb_wideio_size(function_ret); + printk(BIOS_DEBUG, "Covered by wideIO"); + printk(BIOS_DEBUG, " %d\n", function_ret); } } /* check if region found and matches the enable */ @@ -308,18 +265,23 @@ *reg |= set; *reg_x |= set_x; /* check if we can fit resource in variable range */ - } else if ((wio_total < 3) && (res->size <= 512)) { - reg_var[wio_total] = base; - *reg_x |= wio_en.enable[i]; - if (res->size <= 16) - *wiosize |= wio_en.alt[wio_total]; - wio_total++; - *wio_total_ptr = wio_total; } else { - printk(BIOS_ERR, - "cannot fit LPC decode region:"); - printk(BIOS_ERR, "%s, base = 0x%08x, end = 0x%08x\n", - dev_path(child), base, end); + function_ret = sb_set_wideio_range(base, res->size); + if (function_ret != WIDE_IO_RANGE_FAILED) { + /* preserve wide IO related bits. */ + *reg_x = pci_read_config32(SOC_LPC_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE); + + printk(BIOS_DEBUG, + "Range assigned to wide IO %d\n", + function_ret); + } else { + printk(BIOS_ERR, + "cannot fit LPC decode region:"); + printk(BIOS_ERR, + "%s, base = 0x%08x, end = 0x%08x\n", + dev_path(child), base, end); + } } } } @@ -334,27 +296,10 @@ { struct bus *link; u32 reg, reg_x; - int i, wio_total = 0; - u16 reg_var[3]; - u8 wiosize = pci_read_config8(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* - * Detect the number of used ranges (wide IO), and don't use those - * already taken. - */ - for (i = 0; i < 3; i++) { - if (reg_x & wio_en.enable[i]) - wio_total = i + 1; - } - - reg_var[2] = pci_read_config16(dev, LPC_WIDEIO2_GENERIC_PORT); - reg_var[1] = pci_read_config16(dev, LPC_WIDEIO1_GENERIC_PORT); - reg_var[0] = pci_read_config16(dev, LPC_WIDEIO_GENERIC_PORT); - - /* todo: clean up the code style here */ for (link = dev->link_list; link; link = link->next) { device_t child; for (child = link->children; child; @@ -362,29 +307,13 @@ if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { set_child_resource(child, - &wio_total, - reg_var, &reg, - &reg_x, - &wiosize); + &reg_x); } } } pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x); - /* Set WideIO for as many IOs found (fall through is on purpose) */ - switch (wio_total) { - case 3: - pci_write_config16(dev, LPC_WIDEIO2_GENERIC_PORT, reg_var[2]); - /* fall through */ - case 2: - pci_write_config16(dev, LPC_WIDEIO1_GENERIC_PORT, reg_var[1]); - /* fall through */ - case 1: - pci_write_config16(dev, LPC_WIDEIO_GENERIC_PORT, reg_var[0]); - break; - } - pci_write_config8(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, wiosize); } static void lpc_enable_resources(device_t dev) -- To view, visit https://review.coreboot.org/22574 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8533e8ff766df8a8261298559aace7666487826d Gerrit-Change-Number: 22574 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: amd/stoneyridge: Delete early_setup.c
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22569 ) Change subject: amd/stoneyridge: Delete early_setup.c ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18581/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63685/ : SUCCESS -- To view, visit https://review.coreboot.org/22569 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3 Gerrit-Change-Number: 22569 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 21:44:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/crossgcc: Install a template for the edk2 build system
by Patrick Georgi (Code Review) 22 Nov '17

22 Nov '17

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/22570 Change subject: util/crossgcc: Install a template for the edk2 build system ...................................................................... util/crossgcc: Install a template for the edk2 build system Add a CBSDK tool set template that can be used in edk2 simply by appending $prefix/share/edk2config/tools_def.txt to Conf/tools_def.txt. After that, build -t CBSDK uses the coreboot compilers, providing a more predictable compiler choice. Change-Id: I76b38c928b831ee6f31450aa0ad59b4f906f394d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/crossgcc/buildgcc A util/crossgcc/edk2tools.txt 2 files changed, 190 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/22570/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 2f8a9f4..780d87a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -1236,6 +1236,11 @@ rm -f "$DESTDIR$TARGETDIR/share/$PROGNAME-*" cp "$PROGNAME" "$DESTDIR$TARGETDIR/share/$PROGNAME-$CROSSGCC_VERSION-$CROSSGCC_COMMIT" +# Adding edk2 tools template +mkdir -p "$DESTDIR$TARGETDIR/share/edk2config" +sed -e "s,@@PREFIX@@,$TARGETDIR,g" edk2tools.txt > "$DESTDIR$TARGETDIR/share/edk2config/tools_def.txt" +printf "Copied EDK2 tools template ... ${green}ok${NC}\n" + cleanup printf "\n${green}You can now run $NAME from $TARGETDIR.${NC}\n" diff --git a/util/crossgcc/edk2tools.txt b/util/crossgcc/edk2tools.txt new file mode 100644 index 0000000..8420c14 --- /dev/null +++ b/util/crossgcc/edk2tools.txt @@ -0,0 +1,185 @@ +#################################################################################### +# +# COREBOOT is spun off from the GCC5 template +# +#################################################################################### + +DEFINE COREBOOT_IA32_PREFIX = @@PREFIX@@/i386-elf- +DEFINE COREBOOT_X64_PREFIX = @@PREFIX@@/x86_64-elf- +DEFINE COREBOOT_ARM_PREFIX = @@PREFIX@@/arm-eabi- +DEFINE COREBOOT_AARCH64_PREFIX = @@PREFIX@@/arch64-elf- + +DEFINE COREBOOT_IA32_CC_FLAGS = DEF(GCC5_IA32_CC_FLAGS) +DEFINE COREBOOT_X64_CC_FLAGS = DEF(GCC5_X64_CC_FLAGS) +DEFINE COREBOOT_IA32_X64_DLINK_COMMON = DEF(GCC5_IA32_X64_DLINK_COMMON) +DEFINE COREBOOT_IA32_X64_ASLDLINK_FLAGS = DEF(GCC5_IA32_X64_ASLDLINK_FLAGS) +DEFINE COREBOOT_IA32_X64_DLINK_FLAGS = DEF(GCC5_IA32_X64_DLINK_FLAGS) +DEFINE COREBOOT_IA32_DLINK2_FLAGS = DEF(GCC5_IA32_DLINK2_FLAGS) +DEFINE COREBOOT_X64_DLINK_FLAGS = DEF(GCC5_X64_DLINK_FLAGS) +DEFINE COREBOOT_X64_DLINK2_FLAGS = DEF(GCC5_X64_DLINK2_FLAGS) +DEFINE COREBOOT_ASM_FLAGS = DEF(GCC5_ASM_FLAGS) +DEFINE COREBOOT_ARM_ASM_FLAGS = DEF(GCC5_ARM_ASM_FLAGS) +DEFINE COREBOOT_AARCH64_ASM_FLAGS = DEF(GCC5_AARCH64_ASM_FLAGS) +DEFINE COREBOOT_ARM_CC_FLAGS = DEF(GCC5_ARM_CC_FLAGS) +DEFINE COREBOOT_ARM_CC_XIPFLAGS = DEF(GCC5_ARM_CC_XIPFLAGS) +DEFINE COREBOOT_AARCH64_CC_FLAGS = DEF(GCC5_AARCH64_CC_FLAGS) +DEFINE COREBOOT_AARCH64_CC_XIPFLAGS = DEF(GCC5_AARCH64_CC_XIPFLAGS) +DEFINE COREBOOT_ARM_DLINK_FLAGS = DEF(GCC5_ARM_DLINK_FLAGS) +DEFINE COREBOOT_ARM_DLINK2_FLAGS = DEF(GCC5_ARM_DLINK2_FLAGS) +DEFINE COREBOOT_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) +DEFINE COREBOOT_AARCH64_DLINK2_FLAGS = DEF(GCC5_AARCH64_DLINK2_FLAGS) +DEFINE COREBOOT_ARM_ASLDLINK_FLAGS = DEF(GCC5_ARM_ASLDLINK_FLAGS) +DEFINE COREBOOT_AARCH64_ASLDLINK_FLAGS = DEF(GCC5_AARCH64_ASLDLINK_FLAGS) + +#################################################################################### +# +# GCC 5 - This configuration is used to compile under Linux to produce +# PE/COFF binaries using GCC 5 +# +#################################################################################### +*_COREBOOT_*_*_FAMILY = GCC + +*_COREBOOT_*_MAKE_PATH = make +*_COREBOOT_*_*_DLL = ENV(COREBOOT_DLL) +*_COREBOOT_*_ASL_PATH = DEF(UNIX_IASL_BIN) + +*_COREBOOT_*_PP_FLAGS = DEF(GCC_PP_FLAGS) +*_COREBOOT_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) +*_COREBOOT_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_COREBOOT_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) +*_COREBOOT_*_APP_FLAGS = +*_COREBOOT_*_ASL_FLAGS = DEF(IASL_FLAGS) +*_COREBOOT_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS) + +################## +# COREBOOT IA32 definitions +################## +*_COREBOOT_IA32_OBJCOPY_PATH = DEF(COREBOOT_IA32_PREFIX)objcopy +*_COREBOOT_IA32_CC_PATH = DEF(COREBOOT_IA32_PREFIX)gcc +*_COREBOOT_IA32_SLINK_PATH = DEF(COREBOOT_IA32_PREFIX)gcc-ar +*_COREBOOT_IA32_DLINK_PATH = DEF(COREBOOT_IA32_PREFIX)gcc +*_COREBOOT_IA32_ASLDLINK_PATH = DEF(COREBOOT_IA32_PREFIX)gcc +*_COREBOOT_IA32_ASM_PATH = DEF(COREBOOT_IA32_PREFIX)gcc +*_COREBOOT_IA32_PP_PATH = DEF(COREBOOT_IA32_PREFIX)gcc +*_COREBOOT_IA32_VFRPP_PATH = DEF(COREBOOT_IA32_PREFIX)gcc +*_COREBOOT_IA32_ASLCC_PATH = DEF(COREBOOT_IA32_PREFIX)gcc +*_COREBOOT_IA32_ASLPP_PATH = DEF(COREBOOT_IA32_PREFIX)gcc +*_COREBOOT_IA32_RC_PATH = DEF(COREBOOT_IA32_PREFIX)objcopy + +*_COREBOOT_IA32_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m32 -fno-lto +*_COREBOOT_IA32_ASLDLINK_FLAGS = DEF(COREBOOT_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_i386 +*_COREBOOT_IA32_ASM_FLAGS = DEF(COREBOOT_ASM_FLAGS) -m32 -march=i386 +*_COREBOOT_IA32_DLINK2_FLAGS = DEF(COREBOOT_IA32_DLINK2_FLAGS) +*_COREBOOT_IA32_RC_FLAGS = DEF(GCC_IA32_RC_FLAGS) +*_COREBOOT_IA32_OBJCOPY_FLAGS = +*_COREBOOT_IA32_NASM_FLAGS = -f elf32 + + DEBUG_COREBOOT_IA32_CC_FLAGS = DEF(COREBOOT_IA32_CC_FLAGS) -flto -Os + DEBUG_COREBOOT_IA32_DLINK_FLAGS = DEF(COREBOOT_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 + +RELEASE_COREBOOT_IA32_CC_FLAGS = DEF(COREBOOT_IA32_CC_FLAGS) -flto -Os -Wno-unused-but-set-variable +RELEASE_COREBOOT_IA32_DLINK_FLAGS = DEF(COREBOOT_IA32_X64_DLINK_FLAGS) -flto -Os -Wl,-m,elf_i386,--oformat=elf32-i386 + + NOOPT_COREBOOT_IA32_CC_FLAGS = DEF(COREBOOT_IA32_CC_FLAGS) -O0 + NOOPT_COREBOOT_IA32_DLINK_FLAGS = DEF(COREBOOT_IA32_X64_DLINK_FLAGS) -Wl,-m,elf_i386,--oformat=elf32-i386 -O0 + +################## +# COREBOOT X64 definitions +################## +*_COREBOOT_X64_OBJCOPY_PATH = DEF(COREBOOT_X64_PREFIX)objcopy +*_COREBOOT_X64_CC_PATH = DEF(COREBOOT_X64_PREFIX)gcc +*_COREBOOT_X64_SLINK_PATH = DEF(COREBOOT_X64_PREFIX)gcc-ar +*_COREBOOT_X64_DLINK_PATH = DEF(COREBOOT_X64_PREFIX)gcc +*_COREBOOT_X64_ASLDLINK_PATH = DEF(COREBOOT_X64_PREFIX)gcc +*_COREBOOT_X64_ASM_PATH = DEF(COREBOOT_X64_PREFIX)gcc +*_COREBOOT_X64_PP_PATH = DEF(COREBOOT_X64_PREFIX)gcc +*_COREBOOT_X64_VFRPP_PATH = DEF(COREBOOT_X64_PREFIX)gcc +*_COREBOOT_X64_ASLCC_PATH = DEF(COREBOOT_X64_PREFIX)gcc +*_COREBOOT_X64_ASLPP_PATH = DEF(COREBOOT_X64_PREFIX)gcc +*_COREBOOT_X64_RC_PATH = DEF(COREBOOT_X64_PREFIX)objcopy + +*_COREBOOT_X64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -m64 -fno-lto +*_COREBOOT_X64_ASLDLINK_FLAGS = DEF(COREBOOT_IA32_X64_ASLDLINK_FLAGS) -Wl,-m,elf_x86_64 +*_COREBOOT_X64_ASM_FLAGS = DEF(COREBOOT_ASM_FLAGS) -m64 +*_COREBOOT_X64_DLINK2_FLAGS = DEF(COREBOOT_X64_DLINK2_FLAGS) +*_COREBOOT_X64_RC_FLAGS = DEF(GCC_X64_RC_FLAGS) +*_COREBOOT_X64_OBJCOPY_FLAGS = +*_COREBOOT_X64_NASM_FLAGS = -f elf64 + + DEBUG_COREBOOT_X64_CC_FLAGS = DEF(COREBOOT_X64_CC_FLAGS) -flto -DUSING_LTO -Os + DEBUG_COREBOOT_X64_DLINK_FLAGS = DEF(COREBOOT_X64_DLINK_FLAGS) -flto -Os + +RELEASE_COREBOOT_X64_CC_FLAGS = DEF(COREBOOT_X64_CC_FLAGS) -flto -DUSING_LTO -Os -Wno-unused-but-set-variable +RELEASE_COREBOOT_X64_DLINK_FLAGS = DEF(COREBOOT_X64_DLINK_FLAGS) -flto -Os + + NOOPT_COREBOOT_X64_CC_FLAGS = DEF(COREBOOT_X64_CC_FLAGS) -O0 + NOOPT_COREBOOT_X64_DLINK_FLAGS = DEF(COREBOOT_X64_DLINK_FLAGS) -O0 + +################## +# COREBOOT ARM definitions +################## +*_COREBOOT_ARM_CC_PATH = ENV(COREBOOT_ARM_PREFIX)gcc +*_COREBOOT_ARM_SLINK_PATH = ENV(COREBOOT_ARM_PREFIX)gcc-ar +*_COREBOOT_ARM_DLINK_PATH = ENV(COREBOOT_ARM_PREFIX)gcc +*_COREBOOT_ARM_ASLDLINK_PATH = ENV(COREBOOT_ARM_PREFIX)gcc +*_COREBOOT_ARM_ASM_PATH = ENV(COREBOOT_ARM_PREFIX)gcc +*_COREBOOT_ARM_PP_PATH = ENV(COREBOOT_ARM_PREFIX)gcc +*_COREBOOT_ARM_VFRPP_PATH = ENV(COREBOOT_ARM_PREFIX)gcc +*_COREBOOT_ARM_ASLCC_PATH = ENV(COREBOOT_ARM_PREFIX)gcc +*_COREBOOT_ARM_ASLPP_PATH = ENV(COREBOOT_ARM_PREFIX)gcc +*_COREBOOT_ARM_RC_PATH = ENV(COREBOOT_ARM_PREFIX)objcopy + +*_COREBOOT_ARM_ARCHCC_FLAGS = -mthumb +*_COREBOOT_ARM_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_COREBOOT_ARM_ASLDLINK_FLAGS = DEF(COREBOOT_ARM_ASLDLINK_FLAGS) +*_COREBOOT_ARM_ASM_FLAGS = DEF(COREBOOT_ARM_ASM_FLAGS) +*_COREBOOT_ARM_DLINK2_FLAGS = DEF(COREBOOT_ARM_DLINK2_FLAGS) +*_COREBOOT_ARM_PLATFORM_FLAGS = -march=armv7-a +*_COREBOOT_ARM_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) +*_COREBOOT_ARM_RC_FLAGS = DEF(GCC_ARM_RC_FLAGS) +*_COREBOOT_ARM_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) +*_COREBOOT_ARM_CC_XIPFLAGS = DEF(COREBOOT_ARM_CC_XIPFLAGS) + + DEBUG_COREBOOT_ARM_CC_FLAGS = DEF(COREBOOT_ARM_CC_FLAGS) -O0 + DEBUG_COREBOOT_ARM_DLINK_FLAGS = DEF(COREBOOT_ARM_DLINK_FLAGS) + +RELEASE_COREBOOT_ARM_CC_FLAGS = DEF(COREBOOT_ARM_CC_FLAGS) -flto -Wno-unused-but-set-variable +RELEASE_COREBOOT_ARM_DLINK_FLAGS = DEF(COREBOOT_ARM_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-arm -Wl,-plugin-opt=-pass-through=-llto-arm + + NOOPT_COREBOOT_ARM_CC_FLAGS = DEF(COREBOOT_ARM_CC_FLAGS) -O0 + NOOPT_COREBOOT_ARM_DLINK_FLAGS = DEF(COREBOOT_ARM_DLINK_FLAGS) -O0 + +################## +# COREBOOT AARCH64 definitions +################## +*_COREBOOT_AARCH64_CC_PATH = ENV(COREBOOT_AARCH64_PREFIX)gcc +*_COREBOOT_AARCH64_SLINK_PATH = ENV(COREBOOT_AARCH64_PREFIX)gcc-ar +*_COREBOOT_AARCH64_DLINK_PATH = ENV(COREBOOT_AARCH64_PREFIX)gcc +*_COREBOOT_AARCH64_ASLDLINK_PATH = ENV(COREBOOT_AARCH64_PREFIX)gcc +*_COREBOOT_AARCH64_ASM_PATH = ENV(COREBOOT_AARCH64_PREFIX)gcc +*_COREBOOT_AARCH64_PP_PATH = ENV(COREBOOT_AARCH64_PREFIX)gcc +*_COREBOOT_AARCH64_VFRPP_PATH = ENV(COREBOOT_AARCH64_PREFIX)gcc +*_COREBOOT_AARCH64_ASLCC_PATH = ENV(COREBOOT_AARCH64_PREFIX)gcc +*_COREBOOT_AARCH64_ASLPP_PATH = ENV(COREBOOT_AARCH64_PREFIX)gcc +*_COREBOOT_AARCH64_RC_PATH = ENV(COREBOOT_AARCH64_PREFIX)objcopy + +*_COREBOOT_AARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_COREBOOT_AARCH64_ASLDLINK_FLAGS = DEF(COREBOOT_AARCH64_ASLDLINK_FLAGS) +*_COREBOOT_AARCH64_ASM_FLAGS = DEF(COREBOOT_AARCH64_ASM_FLAGS) +*_COREBOOT_AARCH64_DLINK2_FLAGS = DEF(COREBOOT_AARCH64_DLINK2_FLAGS) +*_COREBOOT_AARCH64_PLATFORM_FLAGS = +*_COREBOOT_AARCH64_PP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_PP_FLAGS) +*_COREBOOT_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS) +*_COREBOOT_AARCH64_VFRPP_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_VFRPP_FLAGS) +*_COREBOOT_AARCH64_CC_XIPFLAGS = DEF(COREBOOT_AARCH64_CC_XIPFLAGS) + + DEBUG_COREBOOT_AARCH64_CC_FLAGS = DEF(COREBOOT_AARCH64_CC_FLAGS) -O0 -mcmodel=small + DEBUG_COREBOOT_AARCH64_DLINK_FLAGS = DEF(COREBOOT_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 + DEBUG_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 + +RELEASE_COREBOOT_AARCH64_CC_FLAGS = DEF(COREBOOT_AARCH64_CC_FLAGS) -flto -Wno-unused-but-set-variable -mcmodel=tiny -fomit-frame-pointer +RELEASE_COREBOOT_AARCH64_DLINK_FLAGS = DEF(COREBOOT_AARCH64_DLINK_FLAGS) -flto -Os -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wno-lto-type-mismatch + + NOOPT_COREBOOT_AARCH64_CC_FLAGS = DEF(COREBOOT_AARCH64_CC_FLAGS) -O0 -mcmodel=small + NOOPT_COREBOOT_AARCH64_DLINK_FLAGS = DEF(COREBOOT_AARCH64_DLINK_FLAGS) -z common-page-size=0x1000 -O0 + NOOPT_COREBOOT_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0 -- To view, visit https://review.coreboot.org/22570 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I76b38c928b831ee6f31450aa0ad59b4f906f394d Gerrit-Change-Number: 22570 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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coreboot-gerrit November 2017