coreboot-gerrit November 2017

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Change in coreboot[master]: amd/stoneyridge: Delete early_setup.c
by Richard Spiegel (Code Review) 22 Nov '17

22 Nov '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22569 Change subject: amd/stoneyridge: Delete early_setup.c ...................................................................... amd/stoneyridge: Delete early_setup.c Delete early_setup.c, Change kahlee/ec.c to use new southbridge.c function sb_set_wideio_range. Remove <#ifdef __PRE_RAM__> from kahlee/ec.c. BUG=b:64033893 Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/ec.c M src/soc/amd/stoneyridge/Makefile.inc D src/soc/amd/stoneyridge/early_setup.c 3 files changed, 6 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/22569/1 diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index 3f309eb..35246c9 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -36,9 +36,9 @@ static void early_ec_init(void) { -#ifdef __PRE_RAM__ uint16_t ec_ioport_base; size_t ec_ioport_size; + uint8_t status; /* * Set up LPC decoding for the ChromeEC I/O port ranges: @@ -50,8 +50,11 @@ printk(BIOS_DEBUG, "LPC Setup google_chromeec_ioport_range: %04x, %08zx\n", ec_ioport_base, ec_ioport_size); - lpc_wideio_512_window(ec_ioport_base); -#endif //_PRE_RAM_ + status = sb_set_wideio_range(ec_ioport_base, ec_ioport_size); + if (status == WIDE_IO_RANGE_FAILED) + printk(BIOS_DEBUG, "Failed to assign a range\n"); + else + printk(BIOS_DEBUG, "Range assigned to wide IO %d\n", status); } void mainboard_ec_init(void) diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index f513a20..a978a75 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -40,14 +40,12 @@ bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c bootblock-y += BiosCallOuts.c bootblock-y += bootblock/bootblock.c -bootblock-y += early_setup.c bootblock-y += pmutil.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c romstage-y += BiosCallOuts.c romstage-y += romstage.c -romstage-y += early_setup.c romstage-y += dimmSpd.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c romstage-y += gpio.c diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c deleted file mode 100644 index 09eb8b6..0000000 --- a/src/soc/amd/stoneyridge/early_setup.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <agesawrapper.h> -#include <assert.h> -#include <stdint.h> -#include <arch/io.h> -#include <arch/acpi.h> -#include <console/console.h> -#include <reset.h> -#include <arch/cpu.h> -#include <cbmem.h> -#include <soc/southbridge.h> -#include <soc/pci_devs.h> -#include <cpu/x86/msr.h> -#include <delay.h> - -static void enable_wideio(uint8_t port, uint16_t size) -{ - uint32_t wideio_enable[] = { - LPC_WIDEIO0_ENABLE, - LPC_WIDEIO1_ENABLE, - LPC_WIDEIO2_ENABLE - }; - uint32_t alt_wideio_enable[] = { - LPC_ALT_WIDEIO0_ENABLE, - LPC_ALT_WIDEIO1_ENABLE, - LPC_ALT_WIDEIO2_ENABLE - }; - pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - uint32_t tmp; - - /* Only allow port 0-2 */ - assert(port <= ARRAY_SIZE(wideio_enable)); - - if (size == 16) { - tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); - tmp |= alt_wideio_enable[port]; - pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); - } else { /* 512 */ - tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); - tmp &= ~alt_wideio_enable[port]; - pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); - } - - /* Enable the range */ - tmp = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - tmp |= wideio_enable[port]; - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, tmp); -} - -/* - * lpc_wideio_window() may be called any point in romstage, but take - * care that AGESA doesn't overwrite the range this function used. - * The function checks if there is an empty range and if all ranges are - * used the function throws an assert. The function doesn't check for a - * duplicate range, for ranges that can be merged into a single - * range, or ranges that overlap. - * - * The developer is expected to ensure that there are no conflicts. - */ -static void lpc_wideio_window(uint16_t base, uint16_t size) -{ - pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - u32 tmp; - - /* Support 512 or 16 bytes per range */ - assert(size == 512 || size == 16); - - /* Find and open Base Register and program it */ - tmp = pci_read_config32(dev, LPC_WIDEIO_GENERIC_PORT); - - if ((tmp & 0xffff) == 0) { /* WIDEIO0 */ - tmp |= base; - pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); - enable_wideio(0, size); - } else if ((tmp & 0xffff0000) == 0) { /* WIDEIO1 */ - tmp |= (base << 16); - pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp); - enable_wideio(1, size); - } else { /* Check WIDEIO2 register */ - tmp = pci_read_config32(dev, LPC_WIDEIO2_GENERIC_PORT); - if ((tmp & 0xffff) == 0) { /* WIDEIO2 */ - tmp |= base; - pci_write_config32(dev, LPC_WIDEIO2_GENERIC_PORT, tmp); - enable_wideio(2, size); - } else { /* All WIDEIO locations used*/ - assert(0); - } - } -} - -void lpc_wideio_512_window(uint16_t base) -{ - assert(IS_ALIGNED(base, 512)); - lpc_wideio_window(base, 512); -} - -void lpc_wideio_16_window(uint16_t base) -{ - assert(IS_ALIGNED(base, 16)); - lpc_wideio_window(base, 16); -} -- To view, visit https://review.coreboot.org/22569 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3 Gerrit-Change-Number: 22569 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: Remove table from amd/stoneyridge/include/amd_pci_int_types.h
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22476 ) Change subject: Remove table from amd/stoneyridge/include/amd_pci_int_types.h ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18580/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63684/ : SUCCESS -- To view, visit https://review.coreboot.org/22476 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I18907c93e1eec341d56cea13bb73a336d8e7b05b Gerrit-Change-Number: 22476 Gerrit-PatchSet: 11 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 21:33:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22568 ) Change subject: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18579/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63683/ : SUCCESS -- To view, visit https://review.coreboot.org/22568 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Gerrit-Change-Number: 22568 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 21:25:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c
by Richard Spiegel (Code Review) 22 Nov '17

22 Nov '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22568 Change subject: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c ...................................................................... amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c In preparation to deleting early_setup,c, transfer all functions except those related to wide IO to southbridge.c. Create new generic wide IO functions in southbridge.c. These new functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c. BUG=b:64033893 Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/early_setup.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 4 files changed, 381 insertions(+), 258 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/22568/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index f2a9d8d..f513a20 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -43,6 +43,7 @@ bootblock-y += early_setup.c bootblock-y += pmutil.c bootblock-y += tsc_freq.c +bootblock-y += southbridge.c romstage-y += BiosCallOuts.c romstage-y += romstage.c @@ -57,6 +58,7 @@ romstage-y += ramtop.c romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c +romstage-y += southbridge.c verstage-y += sb_util.c verstage-y += pmutil.c diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index ec3baa4..09eb8b6 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -27,98 +27,6 @@ #include <cpu/x86/msr.h> #include <delay.h> -void configure_stoneyridge_uart(void) -{ - u8 byte, byte2; - - if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) - return; - - /* Power on the UART and AMBA devices */ - byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 - + CONFIG_UART_FOR_CONSOLE * 2); - byte |= AOAC_PWR_ON_DEV; - write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 - + CONFIG_UART_FOR_CONSOLE * 2, byte); - - byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62); - byte |= AOAC_PWR_ON_DEV; - write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte); - - /* Set the GPIO mux to UART */ - write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); - write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); - write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); - write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); - - /* Wait for the UART and AMBA devices to indicate power and clock OK */ - do { - udelay(100); - byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57 - + CONFIG_UART_FOR_CONSOLE * 2); - byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE); - byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE - + FCH_AOAC_REG63); - byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE); - } while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) && - (byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)))); - -} - -void sb_pci_port80(void) -{ - u8 byte; - pci_devfn_t dev; - - dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - - byte = pci_read_config8(dev, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ - pci_write_config8(dev, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); -} - -void sb_lpc_port80(void) -{ - u8 byte; - pci_devfn_t dev; - - /* Enable LPC controller */ - outb(PM_LPC_GATING, PM_INDEX); - byte = inb(PM_DATA); - byte |= PM_LPC_ENABLE; - outb(PM_LPC_GATING, PM_INDEX); - outb(byte, PM_DATA); - - /* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - byte = pci_read_config8(dev, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */ - pci_write_config8(dev, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); -} - -void sb_lpc_decode(void) -{ - pci_devfn_t dev; - u32 tmp = 0; - - /* Enable I/O decode to LPC bus */ - dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 - | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 - | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 - | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 - | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 - | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 - | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 - | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 - | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 - | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT - | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT - | DECODE_ENABLE_ADLIB_PORT; - - pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); -} - static void enable_wideio(uint8_t port, uint16_t size) { uint32_t wideio_enable[] = { @@ -204,170 +112,4 @@ { assert(IS_ALIGNED(base, 16)); lpc_wideio_window(base, 16); -} - -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - int i; - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", - dword, size, nvram_pos); - - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } - - return nvram_pos; -} - -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - u32 data = *old_dword; - int i; - for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i * 8); - nvram_pos++; - } - *old_dword = data; - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", - *old_dword, size, nvram_pos-size); - return nvram_pos; -} - -void sb_clk_output_48Mhz(void) -{ - u32 ctrl; - - /* - * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so - * 48Mhz will be on ball AP13 (FT3b package) - */ - ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); - - /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ - ctrl &= ~FCH_MISC_REG40_OSCOUT1_EN; - write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); -} - -static uintptr_t sb_spibase(void) -{ - /* Make sure the base address is predictable */ - device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - u32 base, enables; - - base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); - enables = base & 0xf; - base &= ~0x3f; - - if (!base) { - base = SPI_BASE_ADDRESS; - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base - | enables | SPI_ROM_ENABLE); - /* PCI_COMMAND_MEMORY is read-only and enabled. */ - } - return (uintptr_t)base; -} - -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) -{ - uintptr_t base = sb_spibase(); - write16((void *)base + SPI100_SPEED_CONFIG, - (norm << SPI_NORM_SPEED_NEW_SH) | - (fast << SPI_FAST_SPEED_NEW_SH) | - (alt << SPI_ALT_SPEED_NEW_SH) | - (tpm << SPI_TPM_SPEED_NEW_SH)); - write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); -} - -void sb_disable_4dw_burst(void) -{ - uintptr_t base = sb_spibase(); - write16((void *)base + SPI100_HOST_PREF_CONFIG, - read16((void *)base + SPI100_HOST_PREF_CONFIG) - & ~SPI_RD4DW_EN_HOST); -} - -void sb_set_readspeed(u16 norm, u16 fast) -{ - uintptr_t base = sb_spibase(); - write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) - & ~SPI_CNTRL1_SPEED_MASK) - | (norm << SPI_NORM_SPEED_SH) - | (fast << SPI_FAST_SPEED_SH)); -} - -void sb_read_mode(u32 mode) -{ - uintptr_t base = sb_spibase(); - write32((void *)base + SPI_CNTRL0, - (read32((void *)base + SPI_CNTRL0) - & ~SPI_READ_MODE_MASK) | mode); -} - -void sb_tpm_decode_spi(void) -{ - device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* LPC device */ - - u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase - | ROUTE_TPM_2_SPI); -} - -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The southbridge power-on default is to map 512K ROM space. - * - */ -void sb_enable_rom(void) -{ - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - - /* - * Decode variable LPC ROM address ranges 1 and 2. - * Bits 3-4 are not defined in any publicly available datasheet - */ - reg8 = pci_io_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - reg8 |= (1 << 3) | (1 << 4); - pci_io_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg8); - - /* - * LPC ROM address range 1: - * Enable LPC ROM range mirroring start at 0x000e(0000). - */ - pci_io_write_config16(dev, ROM_ADDRESS_RANGE1_START, 0x000e); - - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_io_write_config16(dev, ROM_ADDRESS_RANGE1_END, 0x000f); - - /* - * LPC ROM address range 2: - * - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - */ - pci_io_write_config16(dev, ROM_ADDRESS_RANGE2_START, 0x10000 - - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); - - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_io_write_config16(dev, ROM_ADDRESS_RANGE2_END, 0xffff); -} - -void bootblock_fch_early_init(void) -{ - sb_enable_rom(); - sb_lpc_port80(); - sb_lpc_decode(); } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 238feba..beb9af8 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -259,6 +259,12 @@ #define FCH_MISC_REG40_OSCOUT1_EN BIT(2) +/* Return values for sb_find_wideio_range and sb_set_wideio_range. */ +#define WIDE_IO_RANGE_0 0x00 +#define WIDE_IO_RANGE_1 0x01 +#define WIDE_IO_RANGE_2 0x02 +#define WIDE_IO_RANGE_FAILED 0x80 + static inline int sb_sata_enable(void) { /* True if IDE or AHCI. */ @@ -306,5 +312,8 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); void bootblock_fch_early_init(void); +uint16_t sb_wideio_size(uint8_t index); +uint8_t sb_find_wideio_range(uint16_t start, uint16_t end); +uint8_t sb_set_wideio_range(uint16_t start, uint16_t size); #endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 600b064..43975e2 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -28,7 +28,377 @@ #include <soc/southbridge.h> #include <soc/smi.h> #include <fchec.h> +#include <delay.h> +#include <soc/pci_devs.h> +/* + * Structure to simplify code obtaining the total of used wide IO + * registers and the size assigned to each. + */ +static struct wide_IO_ioport_and_bits { + uint32_t enable[3]; + uint16_t port[3]; + uint8_t alt[3]; +} wio_io_en = { + { + LPC_WIDEIO0_ENABLE, + LPC_WIDEIO1_ENABLE, + LPC_WIDEIO2_ENABLE + }, + { + LPC_WIDEIO_GENERIC_PORT, + LPC_WIDEIO1_GENERIC_PORT, + LPC_WIDEIO2_GENERIC_PORT + }, + { + LPC_ALT_WIDEIO0_ENABLE, + LPC_ALT_WIDEIO1_ENABLE, + LPC_ALT_WIDEIO2_ENABLE + } +}; + +/** + * @brief Find the size of a particular wide IO + * + * @param index = index of desired wide IO + * + * @return size of desired wide IO + */ +uint16_t sb_wideio_size(uint8_t index) +{ + uint32_t enable_register; + uint16_t size = 0; + uint8_t alternate_register; + + if (index < 3) { + enable_register = pci_read_config32(SOC_LPC_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE); + alternate_register = pci_read_config8(SOC_LPC_DEV, + LPC_ALT_WIDEIO_RANGE_ENABLE); + if (enable_register & wio_io_en.enable[index]) + size = (alternate_register & wio_io_en.alt[index]) ? + 16 : 512; + } + return size; +} + +/** + * @brief Identify if any LPC wide IO is covering the IO range + * + * @param start = start of IO range + * @param end = end of IO range + * + * @return Index of wide IO covering the range or error + */ +uint8_t sb_find_wideio_range(uint16_t start, uint16_t end) +{ + uint32_t enable_register; + uint16_t reg_var[3], current_size; + uint16_t end_wideio; + uint8_t i, index = WIDE_IO_RANGE_FAILED; + + enable_register = pci_read_config32(SOC_LPC_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE); + for (i = 0; i < 3; i++) + reg_var[i] = pci_read_config16(SOC_LPC_DEV, wio_io_en.port[i]); + + for (i = 0; i < 3; i++) { + current_size = sb_wideio_size(i); + if (current_size == 0) + continue; + end_wideio = reg_var[i] + current_size; + if ((start >= reg_var[i]) && (end <= end_wideio)) { + index = i; + break; + } + } + return index; +} + +/** + * @brief Program a LPC wide IO to support an IO range + * + * @param start = start of range to be routed through wide IO + * @param size = size of range to be routed through wide IO + * + * @return Index of wide IO register used or error + */ +uint8_t sb_set_wideio_range(uint16_t start, uint16_t size) +{ + uint32_t enable_register; + uint8_t i, alternate_register; + uint8_t status = WIDE_IO_RANGE_FAILED; + + enable_register = pci_read_config32(SOC_LPC_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE); + alternate_register = pci_read_config8(SOC_LPC_DEV, + LPC_ALT_WIDEIO_RANGE_ENABLE); + for (i = 0; i < 3; i++) { + if ((enable_register & wio_io_en.enable[i]) == 0) { + status = i; + pci_write_config16(SOC_LPC_DEV, wio_io_en.port[i], + start); + enable_register |= wio_io_en.enable[i]; + pci_write_config32(SOC_LPC_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE, + enable_register); + if (size <= 16) { + alternate_register |= wio_io_en.alt[i]; + pci_write_config8(SOC_LPC_DEV, + LPC_ALT_WIDEIO_RANGE_ENABLE, + alternate_register); + } + break; + } + } + return status; +} + +void configure_stoneyridge_uart(void) +{ + u8 byte, byte2; + + if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + return; + + /* Power on the UART and AMBA devices */ + byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + + CONFIG_UART_FOR_CONSOLE * 2); + byte |= AOAC_PWR_ON_DEV; + write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + + CONFIG_UART_FOR_CONSOLE * 2, byte); + + byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62); + byte |= AOAC_PWR_ON_DEV; + write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte); + + /* Set the GPIO mux to UART */ + write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); + write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); + write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); + write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); + + /* Wait for the UART and AMBA devices to indicate power and clock OK */ + do { + udelay(100); + byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57 + + CONFIG_UART_FOR_CONSOLE * 2); + byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE); + byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + + FCH_AOAC_REG63); + byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE); + } while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) && + (byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)))); + +} + +void sb_pci_port80(void) +{ + u8 byte; + + byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); + byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ + pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); +} + +void sb_lpc_port80(void) +{ + u8 byte; + + /* Enable LPC controller */ + outb(PM_LPC_GATING, PM_INDEX); + byte = inb(PM_DATA); + byte |= PM_LPC_ENABLE; + outb(PM_LPC_GATING, PM_INDEX); + outb(byte, PM_DATA); + + /* Enable port 80 LPC decode in pci function 3 configuration space. */ + byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); + byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */ + pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); +} + +void sb_lpc_decode(void) +{ + u32 tmp = 0; + + /* Enable I/O decode to LPC bus */ + tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 + | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 + | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 + | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 + | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 + | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 + | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 + | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 + | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT + | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT + | DECODE_ENABLE_ADLIB_PORT; + + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); +} + +void sb_clk_output_48Mhz(void) +{ + u32 ctrl; + + /* + * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so + * 48Mhz will be on ball AP13 (FT3b package) + */ + ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); + + /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ + ctrl &= ~FCH_MISC_REG40_OSCOUT1_EN; + write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); +} + +static uintptr_t sb_spibase(void) +{ + u32 base, enables; + + /* Make sure the base address is predictable */ + base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); + enables = base & 0xf; + base &= ~0x3f; + + if (!base) { + base = SPI_BASE_ADDRESS; + pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, + base | enables | SPI_ROM_ENABLE); + /* PCI_COMMAND_MEMORY is read-only and enabled. */ + } + return (uintptr_t)base; +} + +void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) +{ + uintptr_t base = sb_spibase(); + write16((void *)base + SPI100_SPEED_CONFIG, + (norm << SPI_NORM_SPEED_NEW_SH) | + (fast << SPI_FAST_SPEED_NEW_SH) | + (alt << SPI_ALT_SPEED_NEW_SH) | + (tpm << SPI_TPM_SPEED_NEW_SH)); + write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); +} + +void sb_disable_4dw_burst(void) +{ + uintptr_t base = sb_spibase(); + write16((void *)base + SPI100_HOST_PREF_CONFIG, + read16((void *)base + SPI100_HOST_PREF_CONFIG) + & ~SPI_RD4DW_EN_HOST); +} + +void sb_set_readspeed(u16 norm, u16 fast) +{ + uintptr_t base = sb_spibase(); + write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) + & ~SPI_CNTRL1_SPEED_MASK) + | (norm << SPI_NORM_SPEED_SH) + | (fast << SPI_FAST_SPEED_SH)); +} + +void sb_read_mode(u32 mode) +{ + uintptr_t base = sb_spibase(); + write32((void *)base + SPI_CNTRL0, + (read32((void *)base + SPI_CNTRL0) + & ~SPI_READ_MODE_MASK) | mode); +} + +void sb_tpm_decode_spi(void) +{ + u32 spibase = pci_read_config32(SOC_LPC_DEV, + SPIROM_BASE_ADDRESS_REGISTER); + pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase + | ROUTE_TPM_2_SPI); +} + +/* + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The southbridge power-on default is to map 512K ROM space. + * + */ +void sb_enable_rom(void) +{ + u8 reg8; + + /* + * Decode variable LPC ROM address ranges 1 and 2. + * Bits 3-4 are not defined in any publicly available datasheet + */ + reg8 = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + reg8 |= (1 << 3) | (1 << 4); + pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8); + + /* + * LPC ROM address range 1: + * Enable LPC ROM range mirroring start at 0x000e(0000). + */ + pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e); + + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f); + + /* + * LPC ROM address range 2: + * + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + */ + pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 + - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff); +} + +void bootblock_fch_early_init(void) +{ + sb_enable_rom(); + sb_lpc_port80(); + sb_lpc_decode(); +} + +int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +{ + int i; + printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", + dword, size, nvram_pos); + + for (i = 0; i < size; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); + nvram_pos++; + } + + return nvram_pos; +} + +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +{ + u32 data = *old_dword; + int i; + for (i = 0; i < size; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + data &= ~(0xff << (i * 8)); + data |= inb(BIOSRAM_DATA) << (i * 8); + nvram_pos++; + } + *old_dword = data; + printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", + *old_dword, size, nvram_pos-size); + return nvram_pos; +} int acpi_get_sleep_type(void) { -- To view, visit https://review.coreboot.org/22568 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Gerrit-Change-Number: 22568 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: google/gru: Add support for rainier
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22542 ) Change subject: google/gru: Add support for rainier ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/63682/ : SUCCESS -- To view, visit https://review.coreboot.org/22542 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I596f7ca6bc26312ecaeb261c96cebd46974c2cdf Gerrit-Change-Number: 22542 Gerrit-PatchSet: 4 Gerrit-Owner: Ege Mihmanli <egemih(a)google.com> Gerrit-Reviewer: Ege Mihmanli <egemih(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 17:42:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Make use of Intel common PMC common block
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22566 ) Change subject: soc/intel/cannonlake: Make use of Intel common PMC common block ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18577/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63680/ : SUCCESS -- To view, visit https://review.coreboot.org/22566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4 Gerrit-Change-Number: 22566 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 13:47:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common PMC common block
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22565 ) Change subject: soc/intel/skylake: Make use of Intel common PMC common block ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18578/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63681/ : SUCCESS -- To view, visit https://review.coreboot.org/22565 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042bf62407b0acee3d24fbba2de2d482c3fbff9a Gerrit-Change-Number: 22565 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 13:46:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PMC controller support
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22563 ) Change subject: soc/intel/common/block: Add Intel common PMC controller support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18575/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63678/ : SUCCESS -- To view, visit https://review.coreboot.org/22563 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Gerrit-Change-Number: 22563 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 13:46:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Add PNP config
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22488 ) Change subject: soc/intel/apollolake: Add PNP config ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18573/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63676/ : SUCCESS -- To view, visit https://review.coreboot.org/22488 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200 Gerrit-Change-Number: 22488 Gerrit-PatchSet: 4 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 13:42:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Make use of Intel common PMC common block
by build bot (Jenkins) (Code Review) 22 Nov '17

22 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22564 ) Change subject: soc/intel/apollolake: Make use of Intel common PMC common block ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18576/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63679/ : SUCCESS -- To view, visit https://review.coreboot.org/22564 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I968c88ef805fe58751f5359e27cbdf4d3fba3ae9 Gerrit-Change-Number: 22564 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 22 Nov 2017 13:41:04 +0000 Gerrit-HasComments: No

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