coreboot-gerrit November 2017

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Change in coreboot[master]: lib/spd_bin: Only build when CONFIG option is set
by Marc Jones (Code Review) 24 Nov '17

24 Nov '17

Marc Jones has posted comments on this change. ( https://review.coreboot.org/22575 ) Change subject: lib/spd_bin: Only build when CONFIG option is set ...................................................................... Patch Set 3: Code-Review-2 WIP, some boards are not up to code... -- To view, visit https://review.coreboot.org/22575 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97a4d810199c96912d13737046e6041b74315164 Gerrit-Change-Number: 22575 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Nov 2017 21:32:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge/lpc.c: Use new wide IO functions
by build bot (Jenkins) (Code Review) 24 Nov '17

24 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22574 ) Change subject: amd/stoneyridge/lpc.c: Use new wide IO functions ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18642/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63755/ : SUCCESS -- To view, visit https://review.coreboot.org/22574 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8533e8ff766df8a8261298559aace7666487826d Gerrit-Change-Number: 22574 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Nov 2017 15:52:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Delete early_setup.c
by build bot (Jenkins) (Code Review) 24 Nov '17

24 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22569 ) Change subject: amd/stoneyridge: Delete early_setup.c ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18641/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63754/ : SUCCESS -- To view, visit https://review.coreboot.org/22569 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3 Gerrit-Change-Number: 22569 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Nov 2017 15:38:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: kahlee/ec.c: Use new wide IO function
by build bot (Jenkins) (Code Review) 24 Nov '17

24 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22591 ) Change subject: kahlee/ec.c: Use new wide IO function ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18640/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63753/ : SUCCESS -- To view, visit https://review.coreboot.org/22591 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74 Gerrit-Change-Number: 22591 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Nov 2017 15:07:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: kahlee/ec.c: Use new wide IO function
by Richard Spiegel (Code Review) 24 Nov '17

24 Nov '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22591 Change subject: kahlee/ec.c: Use new wide IO function ...................................................................... kahlee/ec.c: Use new wide IO function In preparation to deleting early_setup,c, change early_ec_init() to use new southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>. BUG=b:64033893 Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/ec.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/22591/1 diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index 3f309eb..bbe989d 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -36,9 +36,9 @@ static void early_ec_init(void) { -#ifdef __PRE_RAM__ uint16_t ec_ioport_base; size_t ec_ioport_size; + uint8_t status; /* * Set up LPC decoding for the ChromeEC I/O port ranges: @@ -50,8 +50,11 @@ printk(BIOS_DEBUG, "LPC Setup google_chromeec_ioport_range: %04x, %08zx\n", ec_ioport_base, ec_ioport_size); - lpc_wideio_512_window(ec_ioport_base); -#endif //_PRE_RAM_ + status = sb_set_wideio_range(ec_ioport_base, ec_ioport_size); + if (status == WIDE_IO_RANGE_FAILED) + printk(BIOS_WARNING, "ERROR: Failed to assign a range\n"); + else + printk(BIOS_DEBUG, "Range assigned to wide IO %d\n", status); } void mainboard_ec_init(void) -- To view, visit https://review.coreboot.org/22591 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74 Gerrit-Change-Number: 22591 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: amd/stoneyridge: Create new wide IO functions
by build bot (Jenkins) (Code Review) 24 Nov '17

24 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22590 ) Change subject: amd/stoneyridge: Create new wide IO functions ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18639/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63752/ : SUCCESS -- To view, visit https://review.coreboot.org/22590 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 Gerrit-Change-Number: 22590 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Nov 2017 14:56:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Create new wide IO functions
by Richard Spiegel (Code Review) 24 Nov '17

24 Nov '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22590 Change subject: amd/stoneyridge: Create new wide IO functions ...................................................................... amd/stoneyridge: Create new wide IO functions Create new generic wide IO functions in southbridge.c. These new functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c. BUG=b:64033893 Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 134 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/22590/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 238feba..beb9af8 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -259,6 +259,12 @@ #define FCH_MISC_REG40_OSCOUT1_EN BIT(2) +/* Return values for sb_find_wideio_range and sb_set_wideio_range. */ +#define WIDE_IO_RANGE_0 0x00 +#define WIDE_IO_RANGE_1 0x01 +#define WIDE_IO_RANGE_2 0x02 +#define WIDE_IO_RANGE_FAILED 0x80 + static inline int sb_sata_enable(void) { /* True if IDE or AHCI. */ @@ -306,5 +312,8 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); void bootblock_fch_early_init(void); +uint16_t sb_wideio_size(uint8_t index); +uint8_t sb_find_wideio_range(uint16_t start, uint16_t end); +uint8_t sb_set_wideio_range(uint16_t start, uint16_t size); #endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index dbf27bc..51e0e96 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -31,6 +31,131 @@ #include <delay.h> #include <soc/pci_devs.h> +/* + * Structure to simplify code obtaining the total of used wide IO + * registers and the size assigned to each. + */ +static struct wide_IO_ioport_and_bits { + uint32_t enable[3]; + uint16_t port[3]; + uint8_t alt[3]; +} wio_io_en = { + { + LPC_WIDEIO0_ENABLE, + LPC_WIDEIO1_ENABLE, + LPC_WIDEIO2_ENABLE + }, + { + LPC_WIDEIO_GENERIC_PORT, + LPC_WIDEIO1_GENERIC_PORT, + LPC_WIDEIO2_GENERIC_PORT + }, + { + LPC_ALT_WIDEIO0_ENABLE, + LPC_ALT_WIDEIO1_ENABLE, + LPC_ALT_WIDEIO2_ENABLE + } +}; + +/** + * @brief Find the size of a particular wide IO + * + * @param index = index of desired wide IO + * + * @return size of desired wide IO + */ +uint16_t sb_wideio_size(uint8_t index) +{ + uint32_t enable_register; + uint16_t size = 0; + uint8_t alternate_register; + + if (index < 3) { + enable_register = pci_read_config32(SOC_LPC_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE); + alternate_register = pci_read_config8(SOC_LPC_DEV, + LPC_ALT_WIDEIO_RANGE_ENABLE); + if (enable_register & wio_io_en.enable[index]) + size = (alternate_register & wio_io_en.alt[index]) ? + 16 : 512; + } + return size; +} + +/** + * @brief Identify if any LPC wide IO is covering the IO range + * + * @param start = start of IO range + * @param end = end of IO range + * + * @return Index of wide IO covering the range or error + */ +uint8_t sb_find_wideio_range(uint16_t start, uint16_t end) +{ + uint32_t enable_register; + int i; + uint16_t reg_var[3], current_size; + uint16_t end_wideio; + uint8_t index = WIDE_IO_RANGE_FAILED; + + enable_register = pci_read_config32(SOC_LPC_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE); + for (i = 0; i < 3; i++) + reg_var[i] = pci_read_config16(SOC_LPC_DEV, wio_io_en.port[i]); + + for (i = 0; i < 3; i++) { + current_size = sb_wideio_size(i); + if (current_size == 0) + continue; + end_wideio = reg_var[i] + current_size; + if ((start >= reg_var[i]) && (end <= end_wideio)) { + index = i; + break; + } + } + return index; +} + +/** + * @brief Program a LPC wide IO to support an IO range + * + * @param start = start of range to be routed through wide IO + * @param size = size of range to be routed through wide IO + * + * @return Index of wide IO register used or error + */ +uint8_t sb_set_wideio_range(uint16_t start, uint16_t size) +{ + int i; + uint32_t enable_register; + uint8_t alternate_register; + uint8_t status = WIDE_IO_RANGE_FAILED; + + enable_register = pci_read_config32(SOC_LPC_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE); + alternate_register = pci_read_config8(SOC_LPC_DEV, + LPC_ALT_WIDEIO_RANGE_ENABLE); + for (i = 0; i < 3; i++) { + if ((enable_register & wio_io_en.enable[i]) == 0) { + status = i; + pci_write_config16(SOC_LPC_DEV, wio_io_en.port[i], + start); + enable_register |= wio_io_en.enable[i]; + pci_write_config32(SOC_LPC_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE, + enable_register); + if (size <= 16) { + alternate_register |= wio_io_en.alt[i]; + pci_write_config8(SOC_LPC_DEV, + LPC_ALT_WIDEIO_RANGE_ENABLE, + alternate_register); + } + break; + } + } + return status; +} + void configure_stoneyridge_uart(void) { u8 byte, byte2; -- To view, visit https://review.coreboot.org/22590 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 Gerrit-Change-Number: 22590 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c
by build bot (Jenkins) (Code Review) 24 Nov '17

24 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22568 ) Change subject: amd/stoneyridge: Transfer functions from early_setup.c to southbridge.c ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18638/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63751/ : SUCCESS -- To view, visit https://review.coreboot.org/22568 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Gerrit-Change-Number: 22568 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Nov 2017 14:48:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Provide API to perform any post MP initialization
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22418 ) Change subject: soc/intel/common: Provide API to perform any post MP initialization ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18636/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63749/ : SUCCESS -- To view, visit https://review.coreboot.org/22418 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I140a922147af81851c30444cb4b96c53ae441d7a Gerrit-Change-Number: 22418 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Rushikesh S Kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 24 Nov 2017 06:49:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Set low maximum temperature threshold for Thermal ...
by build bot (Jenkins) (Code Review) 23 Nov '17

23 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22419 ) Change subject: soc/intel/skylake: Set low maximum temperature threshold for Thermal Device ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18637/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63750/ : SUCCESS -- To view, visit https://review.coreboot.org/22419 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610 Gerrit-Change-Number: 22419 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Rushikesh S Kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 24 Nov 2017 06:44:16 +0000 Gerrit-HasComments: No

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coreboot-gerrit November 2017