coreboot-gerrit November 2017

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common Graphics block
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22615 ) Change subject: soc/intel/skylake: Make use of Intel common Graphics block ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18710/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63844/ : SUCCESS -- To view, visit https://review.coreboot.org/22615 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Gerrit-Change-Number: 22615 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 13:25:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common Graphics controller support
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22614 ) Change subject: soc/intel/common/block: Add Intel common Graphics controller support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18711/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63842/ : SUCCESS -- To view, visit https://review.coreboot.org/22614 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Gerrit-Change-Number: 22614 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 13:21:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Make use of Intel common Graphics block
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22616 ) Change subject: soc/intel/apollolake: Make use of Intel common Graphics block ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18712/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63843/ : SUCCESS -- To view, visit https://review.coreboot.org/22616 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Gerrit-Change-Number: 22616 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 13:21:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Make use of Intel common Graphics block
by Subrata Banik (Code Review) 28 Nov '17

28 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22617 Change subject: soc/intel/cannonlake: Make use of Intel common Graphics block ...................................................................... soc/intel/cannonlake: Make use of Intel common Graphics block TEST=Build and boot cannonlake rvp. Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/graphics.c 2 files changed, 5 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/22617/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f4d524a..b95c843 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_GRAPHICS select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index a177127..cd3df19 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -14,29 +14,21 @@ * GNU General Public License for more details. */ -#include <arch/acpi.h> #include <arch/acpigen.h> #include <console/console.h> #include <fsp/util.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/pci_devs.h> #include <drivers/intel/gma/opregion.h> +#include <intelblocks/graphics.h> uintptr_t fsp_soc_get_igd_bar(void) { - device_t dev = SA_DEV_IGD; - - /* Check if IGD PCI device is disabled */ - if (!dev->enabled) - return 0; - - return find_resource(dev, PCI_BASE_ADDRESS_2)->base; + return graphics_get_memory_base(); } -static unsigned long igd_write_opregion(device_t dev, unsigned long current, - struct acpi_rsdp *rsdp) +uintptr_t graphics_soc_write_acpi_opregion(device_t device, + uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; @@ -50,30 +42,3 @@ return acpi_align_current(current); } - -static const struct device_operations igd_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = pci_dev_init, - .write_acpi_tables = igd_write_opregion, - .enable = DEVICE_NOOP -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, - PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, - PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, - PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, - PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, - PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, - PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, - PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, - 0, -}; - -static const struct pci_driver integrated_graphics_driver __pci_driver = { - .ops = &igd_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/22617 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaa1314ae3fcb4a8a3b55a314e79511f5dcba163d Gerrit-Change-Number: 22617 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Make use of Intel common Graphics block
by Subrata Banik (Code Review) 28 Nov '17

28 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22616 Change subject: soc/intel/apollolake: Make use of Intel common Graphics block ...................................................................... soc/intel/apollolake: Make use of Intel common Graphics block TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/graphics.c 2 files changed, 9 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/22616/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f568799..ada9f53 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -71,6 +71,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY + select SOC_INTEL_COMMON_BLOCK_GRAPHICS select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPC diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 90859d5..d7158cc 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2015-2017 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -15,34 +15,21 @@ * GNU General Public License for more details. */ -#include <arch/acpi.h> #include <arch/acpigen.h> #include <console/console.h> #include <fsp/util.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/pci_devs.h> +#include <intelblocks/graphics.h> #include <soc/intel/common/opregion.h> uintptr_t fsp_soc_get_igd_bar(void) { - device_t dev = SA_DEV_IGD; - - /* Check if IGD PCI device is disabled */ - if (!dev->enabled) - return 0; - - return find_resource(dev, PCI_BASE_ADDRESS_2)->base; + return graphics_get_memory_base(); } -static void igd_set_resources(struct device *dev) -{ - pci_dev_set_resources(dev); -} - -static unsigned long igd_write_opregion(device_t dev, unsigned long current, - struct acpi_rsdp *rsdp) +uintptr_t graphics_soc_write_acpi_opregion(device_t device, + uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; uint16_t reg16; @@ -77,34 +64,11 @@ * Maybe it should move to the finalize handler. */ - pci_write_config32(dev, ASLS, (uintptr_t)opregion); - reg16 = pci_read_config16(dev, SWSCI); + pci_write_config32(device, ASLS, (uintptr_t)opregion); + reg16 = pci_read_config16(device, SWSCI); reg16 &= ~(1 << 0); reg16 |= (1 << 15); - pci_write_config16(dev, SWSCI, reg16); + pci_write_config16(device, SWSCI, reg16); return acpi_align_current(current); } - -static const struct device_operations igd_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = igd_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = pci_dev_init, - .write_acpi_tables = igd_write_opregion, - .enable = DEVICE_NOOP -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_INTEL_APL_IGD_HD_505, - PCI_DEVICE_ID_INTEL_APL_IGD_HD_500, - PCI_DEVICE_ID_INTEL_GLK_IGD, - PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, - 0, -}; - -static const struct pci_driver integrated_graphics_driver __pci_driver = { - .ops = &igd_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/22616 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Gerrit-Change-Number: 22616 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common Graphics block
by Subrata Banik (Code Review) 28 Nov '17

28 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22615 Change subject: soc/intel/skylake: Make use of Intel common Graphics block ...................................................................... soc/intel/skylake: Make use of Intel common Graphics block TEST=Build and boot soraka/eve. Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc A src/soc/intel/skylake/graphics.c D src/soc/intel/skylake/igd.c 4 files changed, 116 insertions(+), 194 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/22615/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index e5cc4f7..8bf9b53 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -60,6 +60,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS + select SOC_INTEL_COMMON_BLOCK_GRAPHICS select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index da45ec5..9f33114 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -52,7 +52,7 @@ ramstage-y += gpio.c ramstage-y += gspi.c ramstage-y += i2c.c -ramstage-y += igd.c +ramstage-y += graphics.c ramstage-y += irq.c ramstage-y += lockdown.c ramstage-y += lpc.c diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c new file mode 100644 index 0000000..d4cb6e7 --- /dev/null +++ b/src/soc/intel/skylake/graphics.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/pci.h> +#include <drivers/intel/gma/i915_reg.h> +#include <intelblocks/graphics.h> +#include <soc/intel/common/opregion.h> +#include <soc/ramstage.h> + +uintptr_t fsp_soc_get_igd_bar(void) +{ + return graphics_get_memory_base(); +} + +void graphics_soc_init(struct device *dev) +{ + u32 ddi_buf_ctl; + + /* + * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. + * This will allow the kernel to use 4-lane eDP links properly + * if the VBIOS or GOP driver does not execute. + */ + ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); + if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { + ddi_buf_ctl |= DDI_A_4_LANES; + graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); + } + + if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE)) + return; + + /* IGD needs to be Bus Master */ + u32 reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); +} + +/* Initialize IGD OpRegion, called from ACPI code */ +static int update_igd_opregion(igd_opregion_t *opregion) +{ + u16 reg16; + + /* Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + /* TODO This may need to happen in S3 resume */ + pci_write_config32(SA_DEV_IGD, ASLS, (u32)opregion); + reg16 = pci_read_config16(SA_DEV_IGD, SWSCI); + reg16 &= ~GSSCIE; + reg16 |= SMISCISEL; + pci_write_config16(SA_DEV_IGD, SWSCI, reg16); + + return 0; +} + +uintptr_t graphics_soc_write_acpi_opregion(device_t device, + uintptr_t current, struct acpi_rsdp *rsdp) +{ + igd_opregion_t *opregion; + + /* If GOP is not used, exit here */ + if (!IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE)) + return current; + + /* If IGD is disabled, exit here */ + if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF) + return current; + + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + + if (init_igd_opregion(opregion) != CB_SUCCESS) + return current; + + update_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + current = acpi_align_current(current); + + printk(BIOS_DEBUG, "current = %lx\n", current); + return current; +} diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c deleted file mode 100644 index 545030f..0000000 --- a/src/soc/intel/skylake/igd.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <arch/io.h> -#include <bootmode.h> -#include <chip.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <drivers/intel/gma/i915_reg.h> -#include <soc/intel/common/opregion.h> -#include <soc/acpi.h> -#include <soc/cpu.h> -#include <soc/pm.h> -#include <soc/ramstage.h> -#include <soc/systemagent.h> -#include <stdlib.h> -#include <string.h> -#include <security/vboot/vbnv.h> - -uintptr_t fsp_soc_get_igd_bar(void) -{ - device_t dev = SA_DEV_IGD; - - /* Check if IGD PCI device is disabled */ - if (!dev->enabled) - return 0; - - return find_resource(dev, PCI_BASE_ADDRESS_2)->base; -} - -u32 map_oprom_vendev(u32 vendev) -{ - return SA_IGD_OPROM_VENDEV; -} - -static struct resource *gtt_res = NULL; - -static unsigned long gtt_read(unsigned long reg) -{ - u32 val; - val = read32((void *)(unsigned int)(gtt_res->base + reg)); - return val; -} - -static void gtt_write(unsigned long reg, unsigned long data) -{ - write32((void *)(unsigned int)(gtt_res->base + reg), data); -} - -static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) -{ - u32 val = gtt_read(reg); - val &= andmask; - val |= ormask; - gtt_write(reg, val); -} - -static void igd_init(struct device *dev) -{ - u32 ddi_buf_ctl; - - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!gtt_res || !gtt_res->base) - return; - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver does not execute. - */ - ddi_buf_ctl = gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= DDI_A_4_LANES; - gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } - - if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE)) - return; - - /* IGD needs to be Bus Master */ - u32 reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} - -/* Initialize IGD OpRegion, called from ACPI code */ -static int update_igd_opregion(igd_opregion_t *opregion) -{ - u16 reg16; - - /* Initialize Mailbox 3 */ - opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; - opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; - opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ - opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; - opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; - opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; - opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; - opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; - opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; - opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; - opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; - opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; - opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; - opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; - opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; - - /* TODO This may need to happen in S3 resume */ - pci_write_config32(SA_DEV_IGD, ASLS, (u32)opregion); - reg16 = pci_read_config16(SA_DEV_IGD, SWSCI); - reg16 &= ~GSSCIE; - reg16 |= SMISCISEL; - pci_write_config16(SA_DEV_IGD, SWSCI, reg16); - - return 0; -} - -static unsigned long write_acpi_igd_opregion(device_t device, - unsigned long current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - /* If GOP is not used, exit here */ - if (!IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE)) - return current; - - /* If IGD is disabled, exit here */ - if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF) - return current; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - update_igd_opregion(opregion); - current += sizeof(igd_opregion_t); - current = acpi_align_current(current); - - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; -} - -static struct device_operations igd_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &igd_init, - .ops_pci = &soc_pci_ops, - .write_acpi_tables = write_acpi_igd_opregion, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, - PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, - PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, - PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, - PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, - PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, - PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, - PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM, - PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM, - PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, - PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, - 0, -}; - -static const struct pci_driver igd_driver __pci_driver = { - .ops = &igd_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/22615 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Gerrit-Change-Number: 22615 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common Graphics controller support
by Subrata Banik (Code Review) 28 Nov '17

28 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22614 Change subject: soc/intel/common/block: Add Intel common Graphics controller support ...................................................................... soc/intel/common/block: Add Intel common Graphics controller support SoC need to select specific macros to compile common graphics code. Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/graphics/Kconfig A src/soc/intel/common/block/graphics/Makefile.inc A src/soc/intel/common/block/graphics/graphics.c A src/soc/intel/common/block/include/intelblocks/graphics.h 4 files changed, 184 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/22614/1 diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig new file mode 100644 index 0000000..4ab9200 --- /dev/null +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_GRAPHICS + bool + help + Intel Processor common Graphics support diff --git a/src/soc/intel/common/block/graphics/Makefile.inc b/src/soc/intel/common/block/graphics/Makefile.inc new file mode 100644 index 0000000..44dfc7e --- /dev/null +++ b/src/soc/intel/common/block/graphics/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c new file mode 100644 index 0000000..f35725c --- /dev/null +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/graphics.h> +#include <soc/pci_devs.h> + +/* SoC Overrides */ +__attribute__((weak)) void graphics_soc_init(struct device *dev) +{ + /* no-op */ +} + +__attribute__((weak)) uintptr_t graphics_soc_write_acpi_opregion( + device_t device, uintptr_t current, + struct acpi_rsdp *rsdp) +{ + return 0; +} + +uintptr_t graphics_get_memory_base(void) +{ + struct device *dev = SA_DEV_IGD; + struct resource *gm_res; + + /* + * GFX PCI config space offset 0x18 know as Graphics + * Memory Range Address (GMADR) + */ + gm_res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (!gm_res || !gm_res->base) + return 0; + + return gm_res->base; +} + +static uintptr_t graphics_get_gtt_base(void) +{ + struct device *dev = SA_DEV_IGD; + struct resource *gtt_res; + + /* + * GFX PCI config space offset 0x10 know as Graphics + * Translation Table Memory Mapped Range Address + * (GTTMMADR) + */ + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!gtt_res || !gtt_res->base) + return 0; + + return gtt_res->base; +} + +uintptr_t graphics_gtt_read(uintptr_t reg) +{ + uint32_t val; + val = read32((void *)(graphics_get_gtt_base() + reg)); + return val; +} + +void graphics_gtt_write(uintptr_t reg, uintptr_t data) +{ + write32((void *)(graphics_get_gtt_base() + reg), data); +} + +void graphics_gtt_rmw(uint32_t reg, uint32_t andmask, uint32_t ormask) +{ + uint32_t val = graphics_gtt_read(reg); + val &= andmask; + val |= ormask; + graphics_gtt_write(reg, val); +} + +static const struct device_operations graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = graphics_soc_init, + .write_acpi_tables = graphics_soc_write_acpi_opregion, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_APL_IGD_HD_505, + PCI_DEVICE_ID_INTEL_APL_IGD_HD_500, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, + PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, + PCI_DEVICE_ID_INTEL_GLK_IGD, + PCI_DEVICE_ID_INTEL_GLK_IGD_EU12, + PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM, + PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM, + PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM, + PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR, + PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM, + PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, + PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, + PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, + PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, + PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, + PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, + 0, +}; + +static const struct pci_driver graphics_driver __pci_driver = { + .ops = &graphics_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h new file mode 100644 index 0000000..69a1f36 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_GRAPHICS_H +#define SOC_INTEL_COMMON_BLOCK_GRAPHICS_H + +/* + * SoC overrides + * + * All new SoC must implement below functionality. + */ + +/* + * Perform Graphics Initialization in ramstage + * Input: + * struct device *dev: device structure + */ +void graphics_soc_init(struct device *dev); + +/* + * Write ASL entry for Graphics opregion + * Input: + * device_t device: device structure + * current: start address of graphics opregion + * rsdp: pointer to RSDT (and XSDT) structure + * + * Output: + * 0 = Error, >0 = End address of graphics opregion + */ +uintptr_t graphics_soc_write_acpi_opregion(device_t device, + uintptr_t current, struct acpi_rsdp *rsdp); + +/* Graphics MMIO register read/write APIs */ +uintptr_t graphics_gtt_read(uintptr_t reg); +void graphics_gtt_write(uintptr_t reg, uintptr_t data); +void graphics_gtt_rmw(uint32_t reg, uint32_t andmask, uint32_t ormask); +uintptr_t graphics_get_memory_base(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */ -- To view, visit https://review.coreboot.org/22614 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Gerrit-Change-Number: 22614 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PMC controller support
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22563 ) Change subject: soc/intel/common/block: Add Intel common PMC controller support ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18707/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63839/ : SUCCESS -- To view, visit https://review.coreboot.org/22563 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e Gerrit-Change-Number: 22563 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 28 Nov 2017 10:30:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Initialize PMC controller
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22566 ) Change subject: soc/intel/cannonlake: Initialize PMC controller ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18709/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63841/ : SUCCESS -- To view, visit https://review.coreboot.org/22566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4 Gerrit-Change-Number: 22566 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 28 Nov 2017 10:29:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common PMC common block
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22565 ) Change subject: soc/intel/skylake: Make use of Intel common PMC common block ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18706/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63838/ : SUCCESS -- To view, visit https://review.coreboot.org/22565 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042bf62407b0acee3d24fbba2de2d482c3fbff9a Gerrit-Change-Number: 22565 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 28 Nov 2017 10:28:21 +0000 Gerrit-HasComments: No

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