coreboot-gerrit November 2017

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Change in coreboot[master]: intel/bd82x6x: Add missing IRQ routes
by Tobias Diedrich (Code Review) 28 Nov '17

28 Nov '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22622 Change subject: intel/bd82x6x: Add missing IRQ routes ...................................................................... intel/bd82x6x: Add missing IRQ routes Add missing routing data for the gigabit ethernet, management engine and secondary SATA controller devices. The ACPI table was also inconsistent between the APIC and PIC routing data. At least the gigabit ethernet routing setup is likely needed for PXE option roms in case they are not MSI capable (untested). Tested using Linux with pci=nomsi. Change-Id: Id14f4e2fb03e0a9149c443487665f6eb04c4d3bd --- M src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl M src/southbridge/intel/bd82x6x/early_rcba.c 2 files changed, 31 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/22622/1 diff --git a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl index 0e6f960..999cd4b 100644 --- a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl +++ b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl @@ -27,7 +27,11 @@ Package() { 0x0001ffff, 0, 0, 18 },/* GFX PCIe INTC -> PIRQC (MSI) */ Package() { 0x0001ffff, 0, 0, 19 },/* GFX PCIe INTD -> PIRQD (MSI) */ /* XHCI 0:14.0 (ivy only) */ - Package() { 0x0014ffff, 0, 0, 19 }, + Package() { 0x0014ffff, 0, 0, 19 },/* D20IP_XHCI XHCI INTA -> PIRQD (MSI) */ + /* Management Enginge */ + Package() { 0x0016ffff, 0, 0, 16 },/* D22IP_MEI1 MEI1 INTA -> PIRQA */ + /* Gigabit Ethernet */ + Package() { 0x0019ffff, 0, 0, 16 },/* D25IP_LIP GBE INTA -> PIRQA */ /* High Definition Audio 0:1b.0 */ Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */ /* PCIe Root Ports 0:1c.x */ @@ -43,7 +47,7 @@ Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */ Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */ Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */ - Package() { 0x001fffff, 3, 0, 18 }, + Package() { 0x001fffff, 3, 0, 18 }, /* D31IP_SIP2 SATA2 INTD -> PIRQC (MSI) */ }) } Else { Return (Package() { @@ -56,6 +60,10 @@ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, /* XHCI 0:14.0 (ivy only) */ Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + /* Management Enginge */ + Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* Gigabit Ethernet */ + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, /* High Definition Audio 0:1b.0 */ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, /* PCIe Root Ports 0:1c.x */ diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index eeecb5f..6929bda 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -23,22 +23,26 @@ southbridge_configure_default_intmap(void) { /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP SLOT1 INTA -> PIRQB - * D28IP_P2IP SLOT2 INTB -> PIRQF - * D28IP_P3IP SLOT3 INTC -> PIRQD - * D28IP_P5IP SLOT5 INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) + * D20IP_XHCIIP XHCI INTA -> PIRQD (MSI) + * D22IP_MEI1IP MEI1 INTA -> PIRQA + * D25IP_LIP GBE INTA -> PIRQA (MSI) + * D26IP_E2P EHCI2 INTA -> PIRQF + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * D28IP_P1IP SLOT1 INTA -> PIRQB + * D28IP_P2IP SLOT2 INTB -> PIRQF + * D28IP_P3IP SLOT3 INTC -> PIRQD + * D28IP_P5IP SLOT5 INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SIP2 SATA2 INTD -> PIRQC (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA * */ - RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (INTD << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); @@ -46,8 +50,10 @@ (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); - RCBA32(D25IP) = (NOINT << D25IP_LIP); - RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D25IP) = (INTA << D25IP_LIP); + RCBA32(D22IP) = (INTA << D22IP_MEI1IP) | (NOINT << D22IP_MEI2IP) | + (NOINT << D22IP_IDERIP) | (NOINT << D22IP_KTIP); + RCBA32(D20IP) = (INTA << D20IP_XHCIIP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); @@ -57,6 +63,7 @@ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D20IR, PIRQD, PIRQA, PIRQB, PIRQC); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; -- To view, visit https://review.coreboot.org/22622 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id14f4e2fb03e0a9149c443487665f6eb04c4d3bd Gerrit-Change-Number: 22622 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: soc/intel/apollolake: Make use of Intel common Graphics block
by Furquan Shaikh (Code Review) 28 Nov '17

28 Nov '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/22616 ) Change subject: soc/intel/apollolake: Make use of Intel common Graphics block ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/22616/1/src/soc/intel/apollolake/graphics.c File src/soc/intel/apollolake/graphics.c: https://review.coreboot.org/#/c/22616/1/src/soc/intel/apollolake/graphics.c… PS1, Line 93: Do you not need an init function which calls into pci_dev_init? https://review.coreboot.org/#/c/22616/1/src/soc/intel/apollolake/graphics.c… PS1, Line 28: return This function doesn't check for dev->enabled any more. Is that intentional? https://review.coreboot.org/#/c/22616/1/src/soc/intel/apollolake/graphics.c… PS1, Line 45: /* TODO Initialize Mailbox 3 */ Does this TODO needs to be resolved? https://review.coreboot.org/#/c/22616/1/src/soc/intel/apollolake/graphics.c… PS1, Line 62: /* : * TODO This needs to happen in S3 resume, too. : * Maybe it should move to the finalize handler. : */ Does this TODO needs to be resolved? -- To view, visit https://review.coreboot.org/22616 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Gerrit-Change-Number: 22616 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:58:37 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Make use of Intel common Graphics block
by Furquan Shaikh (Code Review) 28 Nov '17

28 Nov '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/22615 ) Change subject: soc/intel/skylake: Make use of Intel common Graphics block ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/22615/1/src/soc/intel/skylake/graphics.c File src/soc/intel/skylake/graphics.c: https://review.coreboot.org/#/c/22615/1/src/soc/intel/skylake/graphics.c@17 PS1, Line 17: #include <arch/io.h> Is this required? https://review.coreboot.org/#/c/22615/1/src/soc/intel/skylake/graphics.c@39 PS1, Line 39: graphics_gtt_read Before this change, igd_init checked to ensure that the base was not 0 before doing any other operation. The behavior now is not the same. Do we want to return a success/error for the read/write operations here and bail out early if any of those fail? https://review.coreboot.org/#/c/22615/1/src/soc/intel/skylake/graphics.c@86 PS1, Line 86: return 0; This function always returns 0. Is it really useful to have a return type for the function? -- To view, visit https://review.coreboot.org/22615 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Gerrit-Change-Number: 22615 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:54:21 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: intel/bd82x6x: Fix a small mistake in DIR_ROUTE
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22621 ) Change subject: intel/bd82x6x: Fix a small mistake in DIR_ROUTE ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18733/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63865/ : SUCCESS -- To view, visit https://review.coreboot.org/22621 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e Gerrit-Change-Number: 22621 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:51:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/bd82x6x: Fix a small mistake in DIR_ROUTE
by Tobias Diedrich (Code Review) 28 Nov '17

28 Nov '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22621 Change subject: intel/bd82x6x: Fix a small mistake in DIR_ROUTE ...................................................................... intel/bd82x6x: Fix a small mistake in DIR_ROUTE The register is 16-bits wide. If the DIR_ROUTE call ordering was reversed the previous writes would get overwritten. See page 407ff on the Intel C216 datasheet, which says "Size: 16bits" with "Default: 3210h" for all DnnIR registers. This also makes sense given the register offsets: 3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W [3142h would be D30IR] 3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W 3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W 3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W 314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W 3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W [discontinuity in register addresses here] 315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W [315Eh would be D21IR] 3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- M src/southbridge/intel/bd82x6x/pch.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/22621/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 51f3b94..83d9d8d 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -418,7 +418,7 @@ #define SOFT_RESET_DATA 0x38f8 #define DIR_ROUTE(x,a,b,c,d) \ - RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR)) #define RC 0x3400 /* 32bit */ -- To view, visit https://review.coreboot.org/22621 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e Gerrit-Change-Number: 22621 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: Fizz: Set BJ adapter limit
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22620 ) Change subject: Fizz: Set BJ adapter limit ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18732/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63864/ : SUCCESS -- To view, visit https://review.coreboot.org/22620 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9b70725c7e2b37aab1e874e2969ea83324abfb42 Gerrit-Change-Number: 22620 Gerrit-PatchSet: 2 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:34:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/bd82x6x: Refactor and complete IRQ routing.
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22601 ) Change subject: intel/bd82x6x: Refactor and complete IRQ routing. ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18731/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63863/ : SUCCESS -- To view, visit https://review.coreboot.org/22601 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7229aee3817f1f4979325a2abccbb3b99ad312f6 Gerrit-Change-Number: 22601 Gerrit-PatchSet: 9 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:30:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: provide common LPDDR4 memory init
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22204 ) Change subject: soc/intel/cannonlake: provide common LPDDR4 memory init ...................................................................... Patch Set 18: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/63860/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/18728/ : SUCCESS -- To view, visit https://review.coreboot.org/22204 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Gerrit-Change-Number: 22204 Gerrit-PatchSet: 18 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward #1001775 Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:25:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/zoombini/variants/meowth: add new board
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22401 ) Change subject: mainboard/google/zoombini/variants/meowth: add new board ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/63862/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/18730/ : SUCCESS -- To view, visit https://review.coreboot.org/22401 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie6ed7ebb4a00a87fc93fc694d74c08a716380a54 Gerrit-Change-Number: 22401 Gerrit-PatchSet: 5 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:19:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/zoombini: Provide memory configuration variant API
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22205 ) Change subject: mainboard/google/zoombini: Provide memory configuration variant API ...................................................................... Patch Set 19: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/63861/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/18729/ : SUCCESS -- To view, visit https://review.coreboot.org/22205 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad Gerrit-Change-Number: 22205 Gerrit-PatchSet: 19 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward #1001775 Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:15:34 +0000 Gerrit-HasComments: No

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coreboot-gerrit November 2017