coreboot-gerrit November 2017

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Change in coreboot[master]: soc/intel/common/block: Add Intel common Graphics controller support
by Furquan Shaikh (Code Review) 28 Nov '17

28 Nov '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/22614 ) Change subject: soc/intel/common/block: Add Intel common Graphics controller support ...................................................................... Patch Set 1: (8 comments) https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/graphics… File src/soc/intel/common/block/graphics/graphics.c: https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/graphics… PS1, Line 24: __attribute__((weak)) void graphics_soc_init(struct device *dev) : { : /* no-op */ : } : : __attribute__((weak)) uintptr_t graphics_soc_write_acpi_opregion( : device_t device, uintptr_t current, : struct acpi_rsdp *rsdp) : { : return 0; : } Are these functions really optional? If not I think its better not to provide weak definitions. https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/graphics… PS1, Line 36: uintptr_t graphics_get_memory_base(void) : { : struct device *dev = SA_DEV_IGD; : struct resource *gm_res; : : /* : * GFX PCI config space offset 0x18 know as Graphics : * Memory Range Address (GMADR) : */ : gm_res = find_resource(dev, PCI_BASE_ADDRESS_2); : if (!gm_res || !gm_res->base) : return 0; : : return gm_res->base; : } : : static uintptr_t graphics_get_gtt_base(void) : { : struct device *dev = SA_DEV_IGD; : struct resource *gtt_res; : : /* : * GFX PCI config space offset 0x10 know as Graphics : * Translation Table Memory Mapped Range Address : * (GTTMMADR) : */ : gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); : if (!gtt_res || !gtt_res->base) : return 0; : : return gtt_res->base; You can also add a helper function for this: static uintptr_t graphics_get_bar(unsigned long index) { struct device *dev = SA_DEV_IGD; struct resource *gtt_res; gtt_res = find_resource(dev, index); if (!gtt_res) return 0; return gtt_res->base; } and then use it: uintptr_t graphics_get_memory_base(void) { return graphics_get_bar(PCI_BASE_ADDRESS_2); } .... https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/graphics… PS1, Line 72: graphics_get_gtt_base Shouldn't you check the return value of graphics_get_gtt_base before performing the read. https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/graphics… PS1, Line 71: uint32_t val; : val = read32((void *)(graphics_get_gtt_base() + reg)); : return val; Why not just: return read32(...); https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/graphics… PS1, Line 78: graphics_get_gtt_base Same comment as above. https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/graphics… PS1, Line 90: use tabs instead of spaces like other structures? https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/graphics.h: https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/include/… PS1, Line 40: 0 = Error Shouldn't this return current as the caller is not validating the return value and it is being used for future calls to write_acpi_tables. https://review.coreboot.org/#/c/22614/1/src/soc/intel/common/block/include/… PS1, Line 49: memory_base Do you want to specify gmadr here to make it clear what base is being returned? -- To view, visit https://review.coreboot.org/22614 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idbc73854ce9fc21a8a3e3663a98e01fc94d5a5e4 Gerrit-Change-Number: 22614 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:06:12 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: mainboard/google/zoombini/variants/meowth: add new board
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22401 ) Change subject: mainboard/google/zoombini/variants/meowth: add new board ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/63859/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/18727/ : SUCCESS -- To view, visit https://review.coreboot.org/22401 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie6ed7ebb4a00a87fc93fc694d74c08a716380a54 Gerrit-Change-Number: 22401 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:04:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/zoombini: Provide memory configuration variant API
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22205 ) Change subject: mainboard/google/zoombini: Provide memory configuration variant API ...................................................................... Patch Set 18: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/63858/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/18726/ : SUCCESS -- To view, visit https://review.coreboot.org/22205 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad Gerrit-Change-Number: 22205 Gerrit-PatchSet: 18 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward #1001775 Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:04:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: provide common LPDDR4 memory init
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22204 ) Change subject: soc/intel/cannonlake: provide common LPDDR4 memory init ...................................................................... Patch Set 17: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/63857/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/18725/ : SUCCESS -- To view, visit https://review.coreboot.org/22204 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Gerrit-Change-Number: 22204 Gerrit-PatchSet: 17 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward #1001775 Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 20:04:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Fizz: Set BJ adapter limit
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22620 ) Change subject: Fizz: Set BJ adapter limit ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/63856/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/18724/ : SUCCESS -- To view, visit https://review.coreboot.org/22620 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9b70725c7e2b37aab1e874e2969ea83324abfb42 Gerrit-Change-Number: 22620 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 19:58:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Fizz: Set BJ adapter limit
by Daisuke Nojiri (Code Review) 28 Nov '17

28 Nov '17

Daisuke Nojiri has posted comments on this change. ( https://review.coreboot.org/22620 ) Change subject: Fizz: Set BJ adapter limit ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/22620/1/src/mainboard/google/fizz/mainboard… File src/mainboard/google/fizz/mainboard.c: https://review.coreboot.org/#/c/22620/1/src/mainboard/google/fizz/mainboard… PS1, Line 57: bj_adapters bj_adapters and bj_adapter_table are incomplete. We're currently gathering info. -- To view, visit https://review.coreboot.org/22620 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9b70725c7e2b37aab1e874e2969ea83324abfb42 Gerrit-Change-Number: 22620 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 19:33:23 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: Fizz: Set BJ adapter limit
by Daisuke Nojiri (Code Review) 28 Nov '17

28 Nov '17

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/22620 Change subject: Fizz: Set BJ adapter limit ...................................................................... Fizz: Set BJ adapter limit This patch makes coreboot set the max current and voltage for a barrel jack adapter. BUG=b:64442692 BRANCH=none TEST=Boot Fizz. Use chgsup console command to verify the max current and voltage are set as expected. Change-Id: I9b70725c7e2b37aab1e874e2969ea83324abfb42 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h M src/mainboard/google/fizz/mainboard.c 4 files changed, 135 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/22620/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 3d053b6..9bdf702 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -638,6 +638,26 @@ return 0; } +int google_chromeec_override_dedicated_charger_limit(u16 current_lim, + u16 voltage_lim) +{ + struct ec_params_dedicated_charger_limit p = { + .current_lim = current_lim, + .voltage_lim = voltage_lim, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, + .cmd_version = 0, + .cmd_data_in = &p, + .cmd_size_in = sizeof(p), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + return google_chromeec_command(&cmd); +} + int google_chromeec_set_usb_pd_role(u8 port, enum usb_pd_control_role role) { struct ec_params_usb_pd_control req = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 25a90d7..59f48d8 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -91,6 +91,16 @@ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, u32 *max_watts); +/* + * Set max current and voltage of a dedicated charger. + * + * @param current_lim Max current in mA + * @param voltage_lim Max voltage in mV + * @return non-zero for error, otherwise 0. + */ +int google_chromeec_override_dedicated_charger_limit(u16 current_lim, + u16 voltage_lim); + /* internal structure to send a command to the EC and wait for response. */ struct chromeec_command { uint16_t cmd_code; /* command code in, status out */ diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index c4e4e31..17ac51e 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -3533,6 +3533,16 @@ #define EC_POWER_LIMIT_NONE 0xffff +/* + * Set maximum voltage & current of a dedicated charge port + */ +#define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3 + +struct __ec_align2 ec_params_dedicated_charger_limit { + uint16_t current_lim; /* in mA */ + uint16_t voltage_lim; /* in mV */ +}; + /*****************************************************************************/ /* Hibernate/Deep Sleep Commands */ diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index ae37675..319b1ed 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -35,8 +35,71 @@ */ #define GET_TYPEC_PL2(w) (9 * (w) / 10) +/* Dev, Asus, HP, Acer, CfM */ +#define OEM_ID_COUNT 5 +/* Celeron-1, Celeron-2, i3, i5-2, i5-4, i7-2, i7-4 */ +#define SKU_ID_COUNT 7 + +/* List of BJ adapters shipped with Fizz or its variants */ +enum bj_adapter { + BJ_UNKNOWN, + BJ_PPP012C_S, + BJ_ADP_65HB_HCE, + BJ_PA_1650_30, + BJ_PA_1900_92, + BJ_COUNT, +}; + +/* BJ adapter specs */ +static const struct { + uint16_t current_lim; /* in mA */ + uint16_t voltage_lim; /* in mV */ +} bj_adapters[] = { + [BJ_PPP012C_S] = {4620, 19500}, + [BJ_ADP_65HB_HCE] = {3330, 19500}, + [BJ_PA_1650_30] = {3420, 19000}, + [BJ_PA_1900_92] = {4740, 19000}, +}; + +/* + * The table showing which device is shipped with which BJ adapter. + * + * | SKU0 SKU1 ... + * OEM0 | AdapterX AdapterZ ... + * OEM1 | AdapterY ... + * ... | + */ +static const enum bj_adapter bj_adapter_table[OEM_ID_COUNT][SKU_ID_COUNT] = { + {BJ_PPP012C_S, BJ_ADP_65HB_HCE, BJ_PA_1650_30, BJ_PA_1900_92, + BJ_PA_1900_92, BJ_PA_1900_92, BJ_UNKNOWN}, + {BJ_PPP012C_S, BJ_ADP_65HB_HCE, BJ_PA_1650_30, BJ_PA_1900_92, + BJ_PA_1900_92, BJ_PA_1900_92, BJ_UNKNOWN}, + {BJ_PPP012C_S, BJ_ADP_65HB_HCE, BJ_PA_1650_30, BJ_PA_1900_92, + BJ_PA_1900_92, BJ_PA_1900_92, BJ_UNKNOWN}, + {BJ_PPP012C_S, BJ_ADP_65HB_HCE, BJ_PA_1650_30, BJ_PA_1900_92, + BJ_PA_1900_92, BJ_PA_1900_92, BJ_UNKNOWN}, + {BJ_PPP012C_S, BJ_ADP_65HB_HCE, BJ_PA_1650_30, BJ_PA_1900_92, + BJ_PA_1900_92, BJ_PA_1900_92, BJ_UNKNOWN}, +}; + static const char *oem_id = "GOOGLE"; static const char *oem_table_id = "FIZZ"; + + +static uint8_t board_sku_id(void) +{ + static int sku_id = -1; + const gpio_t sku_id_gpios[] = { + GPIO_SKU_ID0, + GPIO_SKU_ID1, + GPIO_SKU_ID2, + GPIO_SKU_ID3, + }; + if (sku_id < 0) + sku_id = gpio_base2_value(sku_id_gpios, + ARRAY_SIZE(sku_id_gpios)); + return sku_id; +} /* * mainboard_get_pl2 @@ -48,25 +111,16 @@ */ static u32 mainboard_get_pl2(void) { - const gpio_t sku_id_gpios[] = { - GPIO_SKU_ID0, - GPIO_SKU_ID1, - GPIO_SKU_ID2, - GPIO_SKU_ID3, - }; enum usb_chg_type type; u32 watts; int rv = google_chromeec_get_usb_pd_power_info(&type, &watts); - int sku_id; /* If we can't get charger info or not PD charger, assume barrel jack */ if (rv != 0 || type != USB_CHG_TYPE_PD) { /* using the barrel jack, get PL2 based on sku id */ watts = FIZZ_PL2_OTHERS; - sku_id = gpio_base2_value(sku_id_gpios, - ARRAY_SIZE(sku_id_gpios)); - if (sku_id == FIZZ_SKU_ID_I7_U42) + if (board_sku_id() == FIZZ_SKU_ID_I7_U42) watts = FIZZ_PL2_I7_U42; } else watts = GET_TYPEC_PL2(watts); @@ -105,6 +159,35 @@ return end_addr; } +/* + * Set max current and voltage for a barrel jack adapter based on {OEM, SKU}. + * If this fails, the limit will remain unchanged = default values, which make + * the system run under safe but under-rated power. + * If a BJ adapter isn't plugged, this is a no-op. + */ +static void set_bj_adapter_limit(void) +{ + uint8_t oem = board_oem_id(); + uint8_t sku = board_sku_id(); + enum bj_adapter bj; + + if (oem >= OEM_ID_COUNT || sku >= SKU_ID_COUNT) { + printk(BIOS_ERR, "Unrecognized OEM or SKU: %d/%d\n", oem, sku); + return; + } + + bj = bj_adapter_table[oem][sku]; + if (bj <= BJ_UNKNOWN || BJ_COUNT <= bj) { + printk(BIOS_ERR, "Invalid BJ adapter ID: %d\n", bj); + return; + } + printk(BIOS_INFO, "Setting BJ limit: %dmA/%dmV\n", + bj_adapters[bj].current_lim, bj_adapters[bj].voltage_lim); + google_chromeec_override_dedicated_charger_limit( + bj_adapters[bj].current_lim, + bj_adapters[bj].voltage_lim); +} + static void mainboard_enable(device_t dev) { device_t tpm; @@ -113,6 +196,8 @@ conf->tdp_pl2_override = mainboard_get_pl2(); + set_bj_adapter_limit(); + dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -- To view, visit https://review.coreboot.org/22620 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9b70725c7e2b37aab1e874e2969ea83324abfb42 Gerrit-Change-Number: 22620 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org>

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Change in coreboot[master]: src/soc/intel/cannonlake: Add gpio groups
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22572 ) Change subject: src/soc/intel/cannonlake: Add gpio groups ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18723/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63855/ : SUCCESS -- To view, visit https://review.coreboot.org/22572 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I00be5e9bf25f1723a3d9e177588135d63ab89662 Gerrit-Change-Number: 22572 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 19:07:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block/gpio: Change group offset calculation
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22571 ) Change subject: soc/intel/common/block/gpio: Change group offset calculation ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18721/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63853/ : SUCCESS -- To view, visit https://review.coreboot.org/22571 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580 Gerrit-Change-Number: 22571 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 19:05:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add GPIO community 3 definition
by build bot (Jenkins) (Code Review) 28 Nov '17

28 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22482 ) Change subject: soc/intel/cannonlake: Add GPIO community 3 definition ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18722/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63854/ : SUCCESS -- To view, visit https://review.coreboot.org/22482 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56 Gerrit-Change-Number: 22482 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Nov 2017 19:05:49 +0000 Gerrit-HasComments: No

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coreboot-gerrit November 2017