coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

1 participants
1340 discussions

Patch set updated for coreboot: soc/intel/quark: Support multiple version of FSP
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16807 -gerrit commit 317d281eea52584f270741e6246dbbc5bf04994f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 18:03:13 2016 -0700 soc/intel/quark: Support multiple version of FSP Add support for multiple versions of FSP. BRANCH=none BUG=None TEST=Build FSP 1.1 (SEC/PEI core, with all FSP debug off) and run on Galileo Gen2 Change-Id: Ie7e7f0f883c4d3bfcb18fa25571e505cdde00b2d Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 3950d43..33b3cf8 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -178,7 +178,7 @@ config ADD_FSP_RAW_BIN config FSP_FILE string "Intel FSP binary path and filename" - default "3rdparty/blobs/soc/intel/quark/fsp.bin" + default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP.fd" depends on PLATFORM_USES_FSP1_1 depends on ADD_FSP_RAW_BIN help @@ -218,12 +218,12 @@ config RELOCATE_FSP_INTO_DRAM config FSP_M_FILE string depends on PLATFORM_USES_FSP2_0 - default "3rdparty/blobs/soc/intel/quark/FSP_M.fd" + default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd" config FSP_S_FILE string depends on PLATFORM_USES_FSP2_0 - default "3rdparty/blobs/soc/intel/quark/FSP_S.fd" + default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd" ##### # RMU binary

1 0

Patch set updated for coreboot: mainboard/intel/galileo: Make FSP 2.0 the default
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16810 -gerrit commit 4e4c8ba14ad62ee7130a44c997f30873b295ff41 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 17:28:00 2016 -0700 mainboard/intel/galileo: Make FSP 2.0 the default Switch from FSP 1.1 to FSP 2.0 as the default build. BRANCH=none BUG=None TEST=Build and run on Galileo Gen2 Change-Id: Icbb3a36cdde68baf4d68fbfc371f8847c56e1162 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 0c1fe5b..e941448 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -46,7 +46,7 @@ config GALILEO_GEN2 choice prompt "FSP version" - default FSP_VERSION_1_1 + default FSP_VERSION_2_0 config FSP_VERSION_1_1 bool "FSP 1.1"

1 0

Patch set updated for coreboot: soc/intel/quark: Fix FSP 2.0 build
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16808 -gerrit commit 690322729dc3589e430ad0ebee0513133312ebc6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 17:16:44 2016 -0700 soc/intel/quark: Fix FSP 2.0 build Fix the build issues with FSP 2.0: * Remove struct from the various data structures. * Properly display the serial port UPDs. * Change chipset_handle_reset parameter type BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug off) and run on Galileo Gen2 Change-Id: Icae578855006f18e7e5aa18d2fd196d300d0c658 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/soc/intel/quark/fsp2_0.c | 2 +- src/soc/intel/quark/reset.c | 2 +- src/soc/intel/quark/romstage/debug.c | 20 +++++++++++++------- src/soc/intel/quark/romstage/fsp2_0.c | 6 +++--- 4 files changed, 18 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c index deb9334..2487cde 100644 --- a/src/soc/intel/quark/fsp2_0.c +++ b/src/soc/intel/quark/fsp2_0.c @@ -16,7 +16,7 @@ #include <fsp/util.h> #include <soc/ramstage.h> -void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { } diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c index e3d3fac..b5b86f3 100644 --- a/src/soc/intel/quark/reset.c +++ b/src/soc/intel/quark/reset.c @@ -17,7 +17,7 @@ #include <fsp/util.h> #include <reset.h> -void chipset_handle_reset(enum fsp_status status) +void chipset_handle_reset(uint32_t status) { /* Do a hard reset if Quark FSP ever requests a reset */ printk(BIOS_ERR, "Unknown reset type %x\n", status); diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c index c08150e..1029ead 100644 --- a/src/soc/intel/quark/romstage/debug.c +++ b/src/soc/intel/quark/romstage/debug.c @@ -16,11 +16,11 @@ #include <console/console.h> #include <fsp/util.h> -void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, - const struct FSPM_UPD *fspm_new_upd) +void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) { - const struct FSP_M_CONFIG *new; - const struct FSP_M_CONFIG *old; + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; old = &fspm_old_upd->FspmConfig; new = &fspm_new_upd->FspmConfig; @@ -62,9 +62,15 @@ void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, old->RmuBaseAddress, new->RmuBaseAddress); fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), old->RmuLength, new->RmuLength); - fsp_display_upd_value("SerialPortBaseAddress", - sizeof(old->SerialPortBaseAddress), - old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SerialPortPollForChar", + sizeof(old->SerialPortPollForChar), + old->SerialPortPollForChar, new->SerialPortPollForChar); + fsp_display_upd_value("SerialPortReadChar", + sizeof(old->SerialPortReadChar), + old->SerialPortReadChar, new->SerialPortReadChar); + fsp_display_upd_value("SerialPortWriteChar", + sizeof(old->SerialPortWriteChar), + old->SerialPortWriteChar, new->SerialPortWriteChar); fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), old->SmmTsegSize, new->SmmTsegSize); fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 51fcde7..d90bd38 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -87,14 +87,14 @@ int fill_power_state(void) return ps->prev_sleep_state; } -void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd) { - struct FSPM_ARCH_UPD *aupd; + FSPM_ARCH_UPD *aupd; const struct device *dev; const struct soc_intel_quark_config *config; char *rmu_file; size_t rmu_file_len; - struct FSP_M_CONFIG *upd; + FSP_M_CONFIG *upd; /* Clear SMI and wake events */ clear_smi_and_wake_events();

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Fix debug display support
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16809 -gerrit commit 75a0f140200a19e15ef1d146ea36e61e3d81ceeb Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 17:15:00 2016 -0700 drivers/intel/fsp2_0: Fix debug display support Fix errors in debug display support. BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug on) and run on Galileo Gen2 Change-Id: I2ece056d66dc8568a7b7206970f20368ec5bf147 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/drivers/intel/fsp2_0/graphics.c | 4 ++-- src/drivers/intel/fsp2_0/hand_off_block.c | 11 ----------- src/drivers/intel/fsp2_0/hob_display.c | 7 ++++++- src/drivers/intel/fsp2_0/include/fsp/util.h | 12 +++++++++++- src/drivers/intel/fsp2_0/upd_display.c | 10 +++++----- 5 files changed, 24 insertions(+), 20 deletions(-) diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index caf7bfa..97fffdc 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -20,7 +20,7 @@ enum pixel_format { pixel_bitmask = 2, /* defined by <rgb>_mask values */ }; -const uint8_t fsp_graphics_info_guid[16] = { +static const uint8_t fsp_graphics_info_guid[16] = { 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 }; @@ -137,4 +137,4 @@ void lb_framebuffer(struct lb_header *header) __attribute__((weak)) uintptr_t fsp_soc_get_igd_bar(void) { return 0; -} \ No newline at end of file +} diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 17adf46..a8b9878 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -22,17 +22,6 @@ #define HOB_HEADER_LEN 8 -enum resource_type { - EFI_RESOURCE_SYSTEM_MEMORY = 0, - EFI_RESOURCE_MEMORY_MAPPED_IO = 1, - EFI_RESOURCE_IO = 2, - EFI_RESOURCE_FIRMWARE_DEVICE = 3, - EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4, - EFI_RESOURCE_MEMORY_RESERVED = 5, - EFI_RESOURCE_IO_RESERVED = 6, - EFI_RESOURCE_MAX_MEMORY_TYPE = 7, -}; - /* GUIDs in little-endian, so they can be used with memcmp() */ const uint8_t fsp_bootloader_tolum_guid[16] = { 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index 39a9d17..c56075b 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -51,6 +51,11 @@ static const uint8_t empty_guid[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +static const uint8_t fsp_graphics_info_guid[16] = { + 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 +}; + static const uint8_t fsp_info_header_guid[16] = { 0xbe, 0x40, 0x27, 0x91, 0x84, 0x22, 0x34, 0x47, 0xb9, 0x71, 0x84, 0xb0, 0x27, 0x35, 0x3f, 0x0c @@ -78,7 +83,7 @@ static const struct guid_name_map guid_names[] = { { fsp_info_header_guid, "FSP_INFO_HEADER_GUID" }, { fsp_reserved_memory_guid, "FSP_RESERVED_MEMORY" }, { fsp_nv_storage_guid, "FSP_NV_STORAGE" }, - { graphics_info_guid, "GRAPHICS INFO" }, + { fsp_graphics_info_guid, "GRAPHICS INFO" }, { smbios_memory_info_guid, "FSP_SMBIOS_MEMORY_INFO_GUID" }, { tseg_guid, "TSEG" }, }; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index acb41e0..04f8c00 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -37,6 +37,17 @@ struct hob_resource { uint64_t length; } __attribute__((packed)); +enum resource_type { + EFI_RESOURCE_SYSTEM_MEMORY = 0, + EFI_RESOURCE_MEMORY_MAPPED_IO = 1, + EFI_RESOURCE_IO = 2, + EFI_RESOURCE_FIRMWARE_DEVICE = 3, + EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4, + EFI_RESOURCE_MEMORY_RESERVED = 5, + EFI_RESOURCE_IO_RESERVED = 6, + EFI_RESOURCE_MAX_MEMORY_TYPE = 7, +}; + enum hob_type { HOB_TYPE_HANDOFF = 0x0001, HOB_TYPE_MEMORY_ALLOCATION = 0x0002, @@ -53,7 +64,6 @@ enum hob_type { }; extern const uint8_t fsp_bootloader_tolum_guid[16]; -extern const uint8_t fsp_graphics_info_guid[16]; extern const uint8_t fsp_nv_storage_guid[16]; extern const uint8_t fsp_reserved_memory_guid[16]; diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index a588358..1ef657d 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -19,15 +19,15 @@ void fsp_display_upd_value(const char *name, size_t size, uint64_t old, { size *= 2; if (old == new) { - printk(BIOS_SPEW, " 0x%0*llx: %s\n", size, new, name); + printk(BIOS_SPEW, " 0x%0*llx: %s\n", (int)size, new, name); } else { - printk(BIOS_SPEW, " 0x%0*llx --> 0x%0*llx: %s\n", size, old, - size, new, name); + printk(BIOS_SPEW, " 0x%0*llx --> 0x%0*llx: %s\n", (int)size, old, + (int)size, new, name); } } -static void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old, - const struct FSPM_ARCH_UPD *new) +static void fspm_display_arch_params(const FSPM_ARCH_UPD *old, + const FSPM_ARCH_UPD *new) { /* Display the architectural parameters for MemoryInit */ printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n",

1 0

New patch to review for coreboot: mainboard/gigabyte/ga-b75m-d3h: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16819 -gerrit commit b5d7a0b7cacc247e72febd75920fac6217ed769c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 20:21:28 2016 +0200 mainboard/gigabyte/ga-b75m-d3h: Use tabs for indents Change-Id: I038e5cea654d1760ddb2c403c651d8f75e021251 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 60 +++++++++++++------------- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 42 +++++++++--------- 2 files changed, 51 insertions(+), 51 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c index 584fec0..7b1c506 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -37,36 +37,36 @@ static void mainboard_init(device_t dev) RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x38c0) = 0x00000007; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; } // mainboard_enable is executed as first thing after diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index dd889d1..06fee7e 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -150,10 +150,10 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -161,27 +161,27 @@ void pch_enable_lpc(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 5, 0 }, - { 1, 5, 0 }, - { 1, 5, 1 }, - { 1, 5, 1 }, - { 1, 5, 2 }, - { 1, 5, 2 }, - { 1, 5, 3 }, - { 1, 5, 3 }, - { 1, 5, 4 }, - { 1, 5, 4 }, - { 1, 5, 6 }, - { 1, 5, 5 }, - { 1, 5, 5 }, - { 1, 5, 6 }, + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, }; void mainboard_get_spd(spd_raw_data *spd) { - read_spd (&spd[0], 0x50); - read_spd (&spd[1], 0x51); - read_spd (&spd[2], 0x52); - read_spd (&spd[3], 0x53); + read_spd (&spd[0], 0x50); + read_spd (&spd[1], 0x51); + read_spd (&spd[2], 0x52); + read_spd (&spd[3], 0x53); } #if 0

1 0

New patch to review for coreboot: mainboard/samsung/stumpy: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16818 -gerrit commit 9dd0ce3741fdbcdfc8d71e92984835ad97a50fe5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 20:09:46 2016 +0200 mainboard/samsung/stumpy: Use tabs for indents Change-Id: I1ffee53a04df6874f658feb3d6ce7d5c7b922837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/samsung/stumpy/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 7f7999c..1062b64 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -207,8 +207,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_get_spd(spd_raw_data *spd) { - read_spd(&spd[0], 0x50); - read_spd(&spd[2], 0x52); + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); } const struct southbridge_usb_port mainboard_usb_ports[] = {

1 0

New patch to review for coreboot: mainboard/amd/serengeti_cheetah/romstage.c & mb_sysconf.h: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16817 -gerrit commit 81131b253128507cc89ba94924b86a99377a910e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 19:57:09 2016 +0200 mainboard/amd/serengeti_cheetah/romstage.c & mb_sysconf.h: Use tabs for indents Change-Id: If47f0c072399fe8291bd8e41920d828f649ec49f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/serengeti_cheetah/mb_sysconf.h | 18 ++-- src/mainboard/amd/serengeti_cheetah/romstage.c | 114 +++++++++++------------ 2 files changed, 66 insertions(+), 66 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h index e1c5180..2aeede0 100644 --- a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h @@ -22,18 +22,18 @@ struct mb_sysconf_t { unsigned char bus_8111_0; unsigned char bus_8111_1; - unsigned char bus_8132a[7][3]; + unsigned char bus_8132a[7][3]; - unsigned char bus_8151[7][2]; + unsigned char bus_8151[7][2]; - unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned apicid_8132a[7][2]; + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + unsigned apicid_8132a[7][2]; - unsigned sbdn3; - unsigned sbdn3a[7]; - unsigned sbdn5[7]; + unsigned sbdn3; + unsigned sbdn3a[7]; + unsigned sbdn5[7]; }; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 53adf6c..fff950a 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -38,8 +38,8 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 - outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -47,20 +47,20 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ - i = 2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret != 0) && (i-->0)); - - smbus_write_byte(SMBUS_HUB, 0x03, 0); + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret != 0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); } static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> @@ -83,32 +83,32 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node - RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, - RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, + RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, + RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC2|DIMM0, RC2|DIMM2, 0, 0, - RC2|DIMM1, RC2|DIMM3, 0, 0, - // four node - RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, - RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, + // third node + RC2|DIMM0, RC2|DIMM2, 0, 0, + RC2|DIMM1, RC2|DIMM3, 0, 0, + // four node + RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, + RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif }; struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0; #if CONFIG_SET_FIDVID struct cpuid_result cpuid1; #endif - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -121,35 +121,35 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - setup_mb_resource_map(); + setup_mb_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif #if CONFIG_SET_FIDVID @@ -158,23 +158,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { - { + { /* Read FIDVID_STATUS */ - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); + init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); @@ -185,15 +185,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } #endif allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); @@ -209,20 +209,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 - print_pci_devices(); + print_pci_devices(); #endif #if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); +// dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }

1 0

Patch set updated for coreboot: mainboard/gigabyte/ga-b75m-d3v: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16816 -gerrit commit e260f39f69ea70c845ea383fab7df57c4b7c8bbc Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 19:48:44 2016 +0200 mainboard/gigabyte/ga-b75m-d3v: Use tabs for indents Change-Id: I36011719f79da4a9ab2aaeb92ffb0506b4373143 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c | 60 +++++++++++++------------- src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 42 +++++++++--------- 2 files changed, 51 insertions(+), 51 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c index 584fec0..7b1c506 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c @@ -37,36 +37,36 @@ static void mainboard_init(device_t dev) RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x38c0) = 0x00000007; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; } // mainboard_enable is executed as first thing after diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index fcdac6d..83a53d0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -82,10 +82,10 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -93,27 +93,27 @@ void pch_enable_lpc(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 5, 0 }, - { 1, 5, 0 }, - { 1, 5, 1 }, - { 1, 5, 1 }, - { 1, 5, 2 }, - { 1, 5, 2 }, - { 1, 5, 3 }, - { 1, 5, 3 }, - { 1, 5, 4 }, - { 1, 5, 4 }, - { 1, 5, 6 }, - { 1, 5, 5 }, - { 1, 5, 5 }, - { 1, 5, 6 }, + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, }; void mainboard_get_spd(spd_raw_data *spd) { - read_spd (&spd[0], 0x50); - read_spd (&spd[1], 0x51); - read_spd (&spd[2], 0x52); - read_spd (&spd[3], 0x53); + read_spd (&spd[0], 0x50); + read_spd (&spd[1], 0x51); + read_spd (&spd[2], 0x52); + read_spd (&spd[3], 0x53); } void mainboard_early_init(int s3resume) {

1 0

New patch to review for coreboot: mainboard/gigabyte/ga-b75m-d3v/romstage.c: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16816 -gerrit commit eece372c4c775e5e550bae7393721ebb8eb82300 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 19:48:44 2016 +0200 mainboard/gigabyte/ga-b75m-d3v/romstage.c: Use tabs for indents Change-Id: I36011719f79da4a9ab2aaeb92ffb0506b4373143 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 42 +++++++++++++-------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index fcdac6d..83a53d0 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -82,10 +82,10 @@ void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -93,27 +93,27 @@ void pch_enable_lpc(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 5, 0 }, - { 1, 5, 0 }, - { 1, 5, 1 }, - { 1, 5, 1 }, - { 1, 5, 2 }, - { 1, 5, 2 }, - { 1, 5, 3 }, - { 1, 5, 3 }, - { 1, 5, 4 }, - { 1, 5, 4 }, - { 1, 5, 6 }, - { 1, 5, 5 }, - { 1, 5, 5 }, - { 1, 5, 6 }, + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, }; void mainboard_get_spd(spd_raw_data *spd) { - read_spd (&spd[0], 0x50); - read_spd (&spd[1], 0x51); - read_spd (&spd[2], 0x52); - read_spd (&spd[3], 0x53); + read_spd (&spd[0], 0x50); + read_spd (&spd[1], 0x51); + read_spd (&spd[2], 0x52); + read_spd (&spd[3], 0x53); } void mainboard_early_init(int s3resume) {

1 0

Patch merged into coreboot/master: mainboard/gigabyte/ga_2761gxdk: Use tabs for indents
by gerrit＠coreboot.org 29 Sep '16

29 Sep '16

the following patch was just integrated into master: commit 129c26e5ea076965487213d8404c01632a060d0a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 22:05:31 2016 +0200 mainboard/gigabyte/ga_2761gxdk: Use tabs for indents Change-Id: Ie752fe0a74acd4b79711596e56fc5ebf83884a0d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16779 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16779 for details. -gerrit

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
134
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2016