coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: i945/gma.c: use linux code to calculate divisors
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit 7dfc8a5ebdf6b272de4373da945d756eadcf2786 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Sep 2 22:35:32 2016 +0200 i945/gma.c: use linux code to calculate divisors The code to compute n, m1, m2, p1 divisors is not correct in coreboot and on some targets hits a working mode at lower refresh rate, which is why display is working on some targets. The divisors must be such "refclk * (5 * (m1 + 2) + (m2 + 2))/ (n + 2) / (p1 * p2)" is as close as possible to the target frequency (which is defined by the resolution and refresh rate). This patch also fixes the reference frequency. This patch reuses linux (4.1) code from drivers/gpu/drm/i915/intel_display.c to correctly compute divisors. The result is that some previously not working displays, like many displays found on the Lenovo T60 might work now. Some examples of T60 displays that were known to not work (in payload): Samsung LTN141XA-L01 (14.1" 1024x768) LG-Philips LP150X09 (15.1" 1024x768) IDtech N150U3-L01 (15.1" 1600x1200) IDtech IAQX10N (15.1" 2048x1536) Samsung LTN154X3-L0A (15.4" 1280x800) LG-Philips LP150E06-A5K4 (15.1" 1400x1050) Tested on T60 with 1024x786. Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/16504 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16504 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Try to update BSP microcode from cbfs
by Martin Roth 30 Sep '16

30 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16829 -gerrit commit 5ed88a5f5f0f1c51004b176b6fa99d4650031b09 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 08:59:58 2016 -0600 soc/intel/apollolake: Try to update BSP microcode from cbfs The microcode for the BSP gets loaded early from the fit table, but in case we have newer microcode in cbfs, try to load it again from cbfs. BUG=chrome-os-partner:53013 TEST=Boot and verify that microcode tries to load into the BSP. Change-Id: Ifd6c78d7b0eec333b79e0fe5cb6a81981b078f5d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/apollolake/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 86fe3e1..f3cf050 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -73,6 +73,9 @@ static void pre_mp_init(void) { x86_setup_mtrrs_with_detect(); x86_mtrr_check(); + + /* Make sure BSP is using the microcode from cbfs */ + intel_update_microcode_from_cbfs(); } /* Find CPU topology */

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New patch to review for coreboot: soc/intel/apollolake: Try to update BSP microcode from cbfs
by Martin Roth 30 Sep '16

30 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16829 -gerrit commit 1a32dbd762f07e82e7c6eb1451340f4af88fa277 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 08:59:58 2016 -0600 soc/intel/apollolake: Try to update BSP microcode from cbfs The microcode for the BSP gets loaded early from the fit table, but in case we have newer microcode in cbfs, try to load it again from cbfs. BUG=53013 TEST=Boot and verify that microcode tries to load into the BSP. Change-Id: Ifd6c78d7b0eec333b79e0fe5cb6a81981b078f5d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/apollolake/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 86fe3e1..f3cf050 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -73,6 +73,9 @@ static void pre_mp_init(void) { x86_setup_mtrrs_with_detect(); x86_mtrr_check(); + + /* Make sure BSP is using the microcode from cbfs */ + intel_update_microcode_from_cbfs(); } /* Find CPU topology */

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Patch set updated for coreboot: mainboard/google/reef: unconditionally set MAINBOARD_FAMILY
by Aaron Durbin 30 Sep '16

30 Sep '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16813 -gerrit commit 8ead04de885023d8e6e71e98e71aedeb2bc771dc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 29 09:54:46 2016 -0500 mainboard/google/reef: unconditionally set MAINBOARD_FAMILY For all mainboard variants use the "Google_Reef" family by default which is populated in SMBIOS tables. A variant can provide their own value if needed, but "Google_Reef" can reside as the family without having to add conditions for each variant when MAINBOARD_FAMILY have to be overridden. BUG=chrome-os-partner:56677 Change-Id: Ic214eae1e6473b32f4cb442c09c34355357e1257 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5039725..41be695 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -58,7 +58,7 @@ config MAINBOARD_PART_NUMBER config MAINBOARD_FAMILY string - default "Google_Reef" if BOARD_GOOGLE_REEF + default "Google_Reef" config GBB_HWID string

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Patch set updated for coreboot: mainboard/gigabyte/m57sli/romstage.c: Use tabs for indents
by HAOUAS Elyes 30 Sep '16

30 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16815 -gerrit commit 5e40fe86ccaa238dd673cc773eb81324b9993555 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 19:13:36 2016 +0200 mainboard/gigabyte/m57sli/romstage.c: Use tabs for indents Change-Id: Ib439e5d96543790d17934bd477af62d39a5958b6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/gigabyte/m57sli/romstage.c | 120 +++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index f8d12c6..b12b12c 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -72,20 +72,20 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + uint32_t dword; + uint8_t byte; - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1 << 0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1 << 16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1 << 16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -99,18 +99,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = &sysinfo_car; - int needs_reset = 0; - unsigned bsp_apicid = 0; + struct sys_info *sysinfo = &sysinfo_car; + int needs_reset = 0; + unsigned bsp_apicid = 0; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + } - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); #if 0 @@ -133,71 +133,71 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - setup_mb_resource_map(); + setup_mb_resource_map(); - console_init(); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); // routing table and start other core0 + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + setup_coherent_ht_domain(); // routing table and start other core0 - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif - /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } #endif init_timer(); // Need to use TMICT to synchronize FID/VID - needs_reset |= optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - needs_reset |= mcp55_early_setup_x(); + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= mcp55_early_setup_x(); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } - allow_all_aps_stop(bsp_apicid); + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } + allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - enable_smbus(); + enable_smbus(); - /* all ap stopped? */ + /* all ap stopped? */ - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }

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Patch set updated for coreboot: mainboard/amd/serengeti_cheetah: Use tabs for indents
by HAOUAS Elyes 30 Sep '16

30 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16817 -gerrit commit 136726357b7ffd1d1aee9096cf750eae060ef50b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 19:57:09 2016 +0200 mainboard/amd/serengeti_cheetah: Use tabs for indents rid of "/romstage.c & mb_sysconf.h" Change-Id: If47f0c072399fe8291bd8e41920d828f649ec49f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/serengeti_cheetah/mb_sysconf.h | 18 ++-- src/mainboard/amd/serengeti_cheetah/romstage.c | 114 +++++++++++------------ 2 files changed, 66 insertions(+), 66 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h index e1c5180..2aeede0 100644 --- a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h @@ -22,18 +22,18 @@ struct mb_sysconf_t { unsigned char bus_8111_0; unsigned char bus_8111_1; - unsigned char bus_8132a[7][3]; + unsigned char bus_8132a[7][3]; - unsigned char bus_8151[7][2]; + unsigned char bus_8151[7][2]; - unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned apicid_8132a[7][2]; + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + unsigned apicid_8132a[7][2]; - unsigned sbdn3; - unsigned sbdn3a[7]; - unsigned sbdn5[7]; + unsigned sbdn3; + unsigned sbdn3a[7]; + unsigned sbdn5[7]; }; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 53adf6c..fff950a 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -38,8 +38,8 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 - outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 + outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -47,20 +47,20 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ - i = 2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret != 0) && (i-->0)); - - smbus_write_byte(SMBUS_HUB, 0x03, 0); + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ + i = 2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret != 0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); } static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> @@ -83,32 +83,32 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node - RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, - RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, + RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, + RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC2|DIMM0, RC2|DIMM2, 0, 0, - RC2|DIMM1, RC2|DIMM3, 0, 0, - // four node - RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, - RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, + // third node + RC2|DIMM0, RC2|DIMM2, 0, 0, + RC2|DIMM1, RC2|DIMM3, 0, 0, + // four node + RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, + RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif }; struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0; #if CONFIG_SET_FIDVID struct cpuid_result cpuid1; #endif - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -121,35 +121,35 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - setup_mb_resource_map(); + setup_mb_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif #if CONFIG_SET_FIDVID @@ -158,23 +158,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { - { + { /* Read FIDVID_STATUS */ - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); + init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); @@ -185,15 +185,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } #endif allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); @@ -209,20 +209,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 - print_pci_devices(); + print_pci_devices(); #endif #if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); +// dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }

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Patch merged into coreboot/master: vboot: clear tpm when required
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit 494d398ae43126aec611238a9d30c7b0020cb251 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 28 18:59:39 2016 -0700 vboot: clear tpm when required Function which invoked when TPM clear is requested was left empty, this patch fixes it. BRANCH=gru BUG=chrome-os-partner:57411 TEST=verified on a chromeos device that tpm is in fact cleared when CLEAR_TPM_OWNER_REQUEST is set by userland. Change-Id: I4370792afd512309ecf7f4961ed4d44a04a3e2aa Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://review.coreboot.org/16805 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com> See https://review.coreboot.org/16805 for details. -gerrit

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Patch merged into coreboot/master: Documentation/Intel/Soc: Update Quark FSP build instructions
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit d677d9cedd4cf2e0022314ce79f893f6d797e645 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Sep 29 13:56:28 2016 -0700 Documentation/Intel/Soc: Update Quark FSP build instructions Update the FSP build instructions for Quark: * Discuss multiple types BRANCH=none BUG=None TEST=Build Quark FSP using new instructions Change-Id: Ibc4bfe32d0eb3877d3b988bc185c73be58d44878 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/16826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16826 for details. -gerrit

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Patch merged into coreboot/master: mainboard/intel/galileo: Make FSP 2.0 the default
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit 31f5c130b103b8cb88d6f7a213a38bcfe66ab8f1 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 17:28:00 2016 -0700 mainboard/intel/galileo: Make FSP 2.0 the default Switch from FSP 1.1 to FSP 2.0 as the default build. BRANCH=none BUG=None TEST=Build and run on Galileo Gen2 Change-Id: Icbb3a36cdde68baf4d68fbfc371f8847c56e1162 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/16810 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16810 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp2_0: Fix debug display support
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit 5a9ca4d1ec45c3304716df0f41b0d798aebbc844 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 17:15:00 2016 -0700 drivers/intel/fsp2_0: Fix debug display support Fix errors in debug display support. BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug on) and run on Galileo Gen2 Change-Id: I2ece056d66dc8568a7b7206970f20368ec5bf147 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/16809 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16809 for details. -gerrit

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coreboot-gerrit September 2016