coreboot-gerrit September 2016

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Patch set updated for coreboot: mainboard/jetway/j7f2: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16825 -gerrit commit 2ced7c80861134fc5af8551f0bd7c054429bbb1e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 21:39:27 2016 +0200 mainboard/jetway/j7f2: Use tabs for indents Change-Id: Id97981a05ce4af371c765c6950ed504557b0a584 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/jetway/j7f2/devicetree.cb | 120 ++++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/src/mainboard/jetway/j7f2/devicetree.cb b/src/mainboard/jetway/j7f2/devicetree.cb index 3b99b9c..ce5589f 100644 --- a/src/mainboard/jetway/j7f2/devicetree.cb +++ b/src/mainboard/jetway/j7f2/devicetree.cb @@ -1,62 +1,62 @@ chip northbridge/via/cn700 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci a.0 on end # Firewire - device pci f.0 on end # SATA - device pci f.1 on end # IDE - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 11.0 on # Southbridge LPC - chip superio/fintek/f71805f # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - end - end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet - end - end - device cpu_cluster 0 on # APIC cluster - chip cpu/via/c7 # VIA C7 - device lapic 0 on end # APIC - end - end + device domain 0 on # PCI domain + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + chip southbridge/via/vt8237r # Southbridge + # Enable both IDE channels. + register "ide0_enable" = "1" + register "ide1_enable" = "1" + # Both cables are 40pin. + register "ide0_80pin_cable" = "0" + register "ide1_80pin_cable" = "0" + register "fn_ctrl_lo" = "0x80" + register "fn_ctrl_hi" = "0x1d" + device pci a.0 on end # Firewire + device pci f.0 on end # SATA + device pci f.1 on end # IDE + device pci 10.0 on end # OHCI + device pci 10.1 on end # OHCI + device pci 10.2 on end # OHCI + device pci 10.3 on end # OHCI + device pci 10.4 on end # EHCI + device pci 11.0 on # Southbridge LPC + chip superio/fintek/f71805f # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + end + end + device pci 11.5 on end # AC'97 audio + # device pci 11.6 off end # AC'97 Modem + device pci 12.0 on end # Ethernet + end + end + device cpu_cluster 0 on # APIC cluster + chip cpu/via/c7 # VIA C7 + device lapic 0 on end # APIC + end + end end

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New patch to review for coreboot: mainboard/jetway/j7f2: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16825 -gerrit commit 1d8161b1258cba217329bc4ccae758950ad4f440 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 21:39:27 2016 +0200 mainboard/jetway/j7f2: Use tabs for indents Change-Id: Id97981a05ce4af371c765c6950ed504557b0a584 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/jetway/j7f2/devicetree.cb | 120 ++++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/src/mainboard/jetway/j7f2/devicetree.cb b/src/mainboard/jetway/j7f2/devicetree.cb index 3b99b9c..e428a49 100644 --- a/src/mainboard/jetway/j7f2/devicetree.cb +++ b/src/mainboard/jetway/j7f2/devicetree.cb @@ -1,62 +1,62 @@ chip northbridge/via/cn700 # Northbridge - device domain 0 on # PCI domain - device pci 0.0 on end # AGP Bridge - device pci 0.1 on end # Error Reporting - device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller - device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller - device pci 1.0 on end # PCI Bridge - chip southbridge/via/vt8237r # Southbridge - # Enable both IDE channels. - register "ide0_enable" = "1" - register "ide1_enable" = "1" - # Both cables are 40pin. - register "ide0_80pin_cable" = "0" - register "ide1_80pin_cable" = "0" - register "fn_ctrl_lo" = "0x80" - register "fn_ctrl_hi" = "0x1d" - device pci a.0 on end # Firewire - device pci f.0 on end # SATA - device pci f.1 on end # IDE - device pci 10.0 on end # OHCI - device pci 10.1 on end # OHCI - device pci 10.2 on end # OHCI - device pci 10.3 on end # OHCI - device pci 10.4 on end # EHCI - device pci 11.0 on # Southbridge LPC - chip superio/fintek/f71805f # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - end - end - device pci 11.5 on end # AC'97 audio - # device pci 11.6 off end # AC'97 Modem - device pci 12.0 on end # Ethernet - end - end - device cpu_cluster 0 on # APIC cluster - chip cpu/via/c7 # VIA C7 - device lapic 0 on end # APIC - end - end + device domain 0 on # PCI domain + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + chip southbridge/via/vt8237r # Southbridge + # Enable both IDE channels. + register "ide0_enable" = "1" + register "ide1_enable" = "1" + # Both cables are 40pin. + register "ide0_80pin_cable" = "0" + register "ide1_80pin_cable" = "0" + register "fn_ctrl_lo" = "0x80" + register "fn_ctrl_hi" = "0x1d" + device pci a.0 on end # Firewire + device pci f.0 on end # SATA + device pci f.1 on end # IDE + device pci 10.0 on end # OHCI + device pci 10.1 on end # OHCI + device pci 10.2 on end # OHCI + device pci 10.3 on end # OHCI + device pci 10.4 on end # EHCI + device pci 11.0 on # Southbridge LPC + chip superio/fintek/f71805f # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + end + end + device pci 11.5 on end # AC'97 audio + # device pci 11.6 off end # AC'97 Modem + device pci 12.0 on end # Ethernet + end + end + device cpu_cluster 0 on # APIC cluster + chip cpu/via/c7 # VIA C7 + device lapic 0 on end # APIC + end + end end

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Patch set updated for coreboot: mainboard/*/*/*/usb.asl: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16824 -gerrit commit d5fa9b05cdc2de4e1e2bfb0bfb75c6e454ab3a67 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 21:28:49 2016 +0200 mainboard/*/*/*/usb.asl: Use tabs for indents Change-Id: Id46a0c4ca59dc7224c2eedd674ea3a5486509de1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/advansus/a785e-i/acpi/usb.asl | 4 ++-- src/mainboard/amd/bimini_fam10/acpi/usb.asl | 4 ++-- src/mainboard/amd/dbm690t/acpi/usb.asl | 4 ++-- src/mainboard/amd/mahogany/acpi/usb.asl | 4 ++-- src/mainboard/amd/mahogany_fam10/acpi/usb.asl | 4 ++-- src/mainboard/amd/pistachio/acpi/usb.asl | 4 ++-- src/mainboard/amd/tilapia_fam10/acpi/usb.asl | 4 ++-- src/mainboard/asus/m4a78-em/acpi/usb.asl | 4 ++-- src/mainboard/asus/m4a785-m/acpi/usb.asl | 4 ++-- src/mainboard/asus/m4a785t-m/acpi/usb.asl | 4 ++-- src/mainboard/gigabyte/ma785gm/acpi/usb.asl | 4 ++-- src/mainboard/gigabyte/ma785gmt/acpi/usb.asl | 4 ++-- src/mainboard/gigabyte/ma78gm/acpi/usb.asl | 4 ++-- src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl | 4 ++-- src/mainboard/jetway/pa78vm5/acpi/usb.asl | 4 ++-- src/mainboard/kontron/kt690/acpi/usb.asl | 4 ++-- src/mainboard/lippert/frontrunner-af/acpi/usb.asl | 2 +- src/mainboard/lippert/toucan-af/acpi/usb.asl | 2 +- src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl | 4 ++-- src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl | 4 ++-- src/mainboard/technexion/tim8690/acpi/usb.asl | 4 ++-- 21 files changed, 40 insertions(+), 40 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/acpi/usb.asl b/src/mainboard/advansus/a785e-i/acpi/usb.asl index 86f7825..0f8ca9c 100644 --- a/src/mainboard/advansus/a785e-i/acpi/usb.asl +++ b/src/mainboard/advansus/a785e-i/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/bimini_fam10/acpi/usb.asl b/src/mainboard/amd/bimini_fam10/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/amd/bimini_fam10/acpi/usb.asl +++ b/src/mainboard/amd/bimini_fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/dbm690t/acpi/usb.asl b/src/mainboard/amd/dbm690t/acpi/usb.asl index 7aa29a7..6386906 100644 --- a/src/mainboard/amd/dbm690t/acpi/usb.asl +++ b/src/mainboard/amd/dbm690t/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/mahogany/acpi/usb.asl b/src/mainboard/amd/mahogany/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/amd/mahogany/acpi/usb.asl +++ b/src/mainboard/amd/mahogany/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/mahogany_fam10/acpi/usb.asl b/src/mainboard/amd/mahogany_fam10/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi/usb.asl +++ b/src/mainboard/amd/mahogany_fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/pistachio/acpi/usb.asl b/src/mainboard/amd/pistachio/acpi/usb.asl index 0d9f2a6..a1f87b6 100644 --- a/src/mainboard/amd/pistachio/acpi/usb.asl +++ b/src/mainboard/amd/pistachio/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -123,7 +123,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/tilapia_fam10/acpi/usb.asl b/src/mainboard/amd/tilapia_fam10/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi/usb.asl +++ b/src/mainboard/amd/tilapia_fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/asus/m4a78-em/acpi/usb.asl b/src/mainboard/asus/m4a78-em/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/asus/m4a78-em/acpi/usb.asl +++ b/src/mainboard/asus/m4a78-em/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/asus/m4a785-m/acpi/usb.asl b/src/mainboard/asus/m4a785-m/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/asus/m4a785-m/acpi/usb.asl +++ b/src/mainboard/asus/m4a785-m/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/asus/m4a785t-m/acpi/usb.asl b/src/mainboard/asus/m4a785t-m/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/asus/m4a785t-m/acpi/usb.asl +++ b/src/mainboard/asus/m4a785t-m/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/gigabyte/ma785gm/acpi/usb.asl b/src/mainboard/gigabyte/ma785gm/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi/usb.asl +++ b/src/mainboard/gigabyte/ma785gm/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl b/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl +++ b/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/gigabyte/ma78gm/acpi/usb.asl b/src/mainboard/gigabyte/ma78gm/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi/usb.asl +++ b/src/mainboard/gigabyte/ma78gm/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl +++ b/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/jetway/pa78vm5/acpi/usb.asl b/src/mainboard/jetway/pa78vm5/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/jetway/pa78vm5/acpi/usb.asl +++ b/src/mainboard/jetway/pa78vm5/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/kontron/kt690/acpi/usb.asl b/src/mainboard/kontron/kt690/acpi/usb.asl index 7aa29a7..6386906 100644 --- a/src/mainboard/kontron/kt690/acpi/usb.asl +++ b/src/mainboard/kontron/kt690/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl index 0951451..0f8ca9c 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/lippert/toucan-af/acpi/usb.asl b/src/mainboard/lippert/toucan-af/acpi/usb.asl index 0951451..0f8ca9c 100644 --- a/src/mainboard/lippert/toucan-af/acpi/usb.asl +++ b/src/mainboard/lippert/toucan-af/acpi/usb.asl @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl index de93e8c..54613a8 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl @@ -16,7 +16,7 @@ /* simple name description */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -114,7 +114,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl index bf1a6e9..d4fc433 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl +++ b/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/technexion/tim8690/acpi/usb.asl b/src/mainboard/technexion/tim8690/acpi/usb.asl index 7aa29a7..6386906 100644 --- a/src/mainboard/technexion/tim8690/acpi/usb.asl +++ b/src/mainboard/technexion/tim8690/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC()

1 0

New patch to review for coreboot: mainboard/*/*/*/usb.asl: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16824 -gerrit commit d860fb5f754b82928de82c9c6c56cb49eec2430b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 21:22:46 2016 +0200 mainboard/*/*/*/usb.asl: Use tabs for indents Change-Id: Id46a0c4ca59dc7224c2eedd674ea3a5486509de1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/advansus/a785e-i/acpi/usb.asl | 4 ++-- src/mainboard/amd/bimini_fam10/acpi/usb.asl | 4 ++-- src/mainboard/amd/dbm690t/acpi/usb.asl | 4 ++-- src/mainboard/amd/mahogany/acpi/usb.asl | 4 ++-- src/mainboard/amd/mahogany_fam10/acpi/usb.asl | 4 ++-- src/mainboard/amd/pistachio/acpi/usb.asl | 4 ++-- src/mainboard/amd/tilapia_fam10/acpi/usb.asl | 4 ++-- src/mainboard/asus/m4a78-em/acpi/usb.asl | 4 ++-- src/mainboard/asus/m4a785-m/acpi/usb.asl | 4 ++-- src/mainboard/asus/m4a785t-m/acpi/usb.asl | 4 ++-- src/mainboard/gigabyte/ma785gm/acpi/usb.asl | 4 ++-- src/mainboard/gigabyte/ma785gmt/acpi/usb.asl | 4 ++-- src/mainboard/gigabyte/ma78gm/acpi/usb.asl | 4 ++-- src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl | 4 ++-- src/mainboard/jetway/pa78vm5/acpi/usb.asl | 4 ++-- src/mainboard/kontron/kt690/acpi/usb.asl | 4 ++-- src/mainboard/lippert/frontrunner-af/acpi/usb.asl | 2 +- src/mainboard/lippert/toucan-af/acpi/usb.asl | 2 +- src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl | 4 ++-- src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl | 4 ++-- src/mainboard/technexion/tim8690/acpi/usb.asl | 4 ++-- 21 files changed, 40 insertions(+), 40 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/acpi/usb.asl b/src/mainboard/advansus/a785e-i/acpi/usb.asl index 86f7825..2f051ff 100644 --- a/src/mainboard/advansus/a785e-i/acpi/usb.asl +++ b/src/mainboard/advansus/a785e-i/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/bimini_fam10/acpi/usb.asl b/src/mainboard/amd/bimini_fam10/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/amd/bimini_fam10/acpi/usb.asl +++ b/src/mainboard/amd/bimini_fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/dbm690t/acpi/usb.asl b/src/mainboard/amd/dbm690t/acpi/usb.asl index 7aa29a7..d13f4e7 100644 --- a/src/mainboard/amd/dbm690t/acpi/usb.asl +++ b/src/mainboard/amd/dbm690t/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/mahogany/acpi/usb.asl b/src/mainboard/amd/mahogany/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/amd/mahogany/acpi/usb.asl +++ b/src/mainboard/amd/mahogany/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/mahogany_fam10/acpi/usb.asl b/src/mainboard/amd/mahogany_fam10/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi/usb.asl +++ b/src/mainboard/amd/mahogany_fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/pistachio/acpi/usb.asl b/src/mainboard/amd/pistachio/acpi/usb.asl index 0d9f2a6..7ae1eed 100644 --- a/src/mainboard/amd/pistachio/acpi/usb.asl +++ b/src/mainboard/amd/pistachio/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -123,7 +123,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/amd/tilapia_fam10/acpi/usb.asl b/src/mainboard/amd/tilapia_fam10/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi/usb.asl +++ b/src/mainboard/amd/tilapia_fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/asus/m4a78-em/acpi/usb.asl b/src/mainboard/asus/m4a78-em/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/asus/m4a78-em/acpi/usb.asl +++ b/src/mainboard/asus/m4a78-em/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/asus/m4a785-m/acpi/usb.asl b/src/mainboard/asus/m4a785-m/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/asus/m4a785-m/acpi/usb.asl +++ b/src/mainboard/asus/m4a785-m/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/asus/m4a785t-m/acpi/usb.asl b/src/mainboard/asus/m4a785t-m/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/asus/m4a785t-m/acpi/usb.asl +++ b/src/mainboard/asus/m4a785t-m/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/gigabyte/ma785gm/acpi/usb.asl b/src/mainboard/gigabyte/ma785gm/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi/usb.asl +++ b/src/mainboard/gigabyte/ma785gm/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl b/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl +++ b/src/mainboard/gigabyte/ma785gmt/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/gigabyte/ma78gm/acpi/usb.asl b/src/mainboard/gigabyte/ma78gm/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi/usb.asl +++ b/src/mainboard/gigabyte/ma78gm/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl +++ b/src/mainboard/iei/kino-780am2-fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/jetway/pa78vm5/acpi/usb.asl b/src/mainboard/jetway/pa78vm5/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/jetway/pa78vm5/acpi/usb.asl +++ b/src/mainboard/jetway/pa78vm5/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/kontron/kt690/acpi/usb.asl b/src/mainboard/kontron/kt690/acpi/usb.asl index 7aa29a7..6386906 100644 --- a/src/mainboard/kontron/kt690/acpi/usb.asl +++ b/src/mainboard/kontron/kt690/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl index 0951451..2f051ff 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/lippert/toucan-af/acpi/usb.asl b/src/mainboard/lippert/toucan-af/acpi/usb.asl index 0951451..2f051ff 100644 --- a/src/mainboard/lippert/toucan-af/acpi/usb.asl +++ b/src/mainboard/lippert/toucan-af/acpi/usb.asl @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl index de93e8c..9dc3761 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl @@ -16,7 +16,7 @@ /* simple name description */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -114,7 +114,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl index bf1a6e9..0e06c02 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl +++ b/src/mainboard/supermicro/h8scm_fam10/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/technexion/tim8690/acpi/usb.asl b/src/mainboard/technexion/tim8690/acpi/usb.asl index 7aa29a7..d13f4e7 100644 --- a/src/mainboard/technexion/tim8690/acpi/usb.asl +++ b/src/mainboard/technexion/tim8690/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -121,7 +121,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { +Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC()

1 0

New patch to review for coreboot: mainboard/winent/mb6047: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16823 -gerrit commit 91b774ce8ce2bf5740815dd56a201cf95d8b4938 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 21:07:44 2016 +0200 mainboard/winent/mb6047: Use tabs for indents Change-Id: Iaf5ad440cfc2bbe08ea9f6c545e5e314645c8893 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/winent/mb6047/devicetree.cb | 236 +++++++++++++++--------------- 1 file changed, 118 insertions(+), 118 deletions(-) diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb index 81f5aae..98a9247 100644 --- a/src/mainboard/winent/mb6047/devicetree.cb +++ b/src/mainboard/winent/mb6047/devicetree.cb @@ -1,120 +1,120 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_940 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x10de 0xcb84 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # Consumer IR - device pnp 2e.7 off end # Game port, MIDI, GPIO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic # DIMM 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic # DIMM 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # DIMM 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic # DIMM 0-1-1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # DIMM 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic # DIMM 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic # DIMM 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic # DIMM 1-1-1 - # device i2c 57 on end - # end - end - # device pci 1.1 on # SM 1 - # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 - # device i2c 2d on end - # end - # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 - # device i2c 2e on end - # end - # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN - # device i2c 2a on end - # end - # chip drivers/generic/generic # Winbond HWM 0x92 - # device i2c 49 on end - # end - # chip drivers/generic/generic # Winbond HWM 0x94 - # device i2c 4a on end - # end - # end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI - # device pci 6.0 on end - end - device pci a.0 on end # NIC - device pci b.0 on end # PCI E 3 - device pci c.0 on end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "0" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end - end - device pci 18.0 on end # Link 1 - device pci 18.0 on end # Link 2 == LDT 2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_940 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x10de 0xcb84 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, MIDI, GPIO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic # DIMM 0-0-0 + # device i2c 50 on end + # end + # chip drivers/generic/generic # DIMM 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # DIMM 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic # DIMM 0-1-1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # DIMM 1-0-0 + # device i2c 54 on end + # end + # chip drivers/generic/generic # DIMM 1-0-1 + # device i2c 55 on end + # end + # chip drivers/generic/generic # DIMM 1-1-0 + # device i2c 56 on end + # end + # chip drivers/generic/generic # DIMM 1-1-1 + # device i2c 57 on end + # end + end + # device pci 1.1 on # SM 1 + # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + # device i2c 2d on end + # end + # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + # device i2c 2e on end + # end + # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + # device i2c 2a on end + # end + # chip drivers/generic/generic # Winbond HWM 0x92 + # device i2c 49 on end + # end + # chip drivers/generic/generic # Winbond HWM 0x94 + # device i2c 4a on end + # end + # end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # device pci 6.0 on end + end + device pci a.0 on end # NIC + device pci b.0 on end # PCI E 3 + device pci c.0 on end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "0" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on end # Link 2 == LDT 2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end end

1 0

New patch to review for coreboot: mainboard/kontron/ktqm77: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16822 -gerrit commit 2bed159f2c7b209758b2efe1f5beb500a053e379 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 21:00:13 2016 +0200 mainboard/kontron/ktqm77: Use tabs for indents Change-Id: I3040dc9a2534a77087805ee61c4f91d1bdb4d509 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/kontron/ktqm77/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 1536467..d2d7acf 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -148,7 +148,7 @@ static int int15_handler(void) X86_EAX |= 0x015f; res = 1; break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break;

1 0

New patch to review for coreboot: mainboard/digitallogic/msm800sev: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16821 -gerrit commit b7e07beaa2bb0d76fc1c141c2d05761a9070ecb8 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 20:52:26 2016 +0200 mainboard/digitallogic/msm800sev: Use tabs for indents Change-Id: I39ad6606869f059b2ef0c45d6741b844b3791655 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/digitallogic/msm800sev/devicetree.cb | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index db511e5..b03d4c5 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -1,8 +1,8 @@ chip northbridge/amd/lx - device domain 0 on - device pci 1.0 on end + device domain 0 on + device pci 1.0 on end device pci 1.1 on end - chip southbridge/amd/cs5536 + chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK @@ -25,7 +25,7 @@ chip northbridge/amd/lx register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge + device pci f.0 on # ISA Bridge chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 @@ -69,10 +69,10 @@ chip northbridge/amd/lx end device pci f.1 on end # Flash controller device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI + device pci f.3 on end # Audio + device pci f.4 on end # OHCI device pci f.5 on end # EHCI - end + end end # APIC cluster is late CPU init.

1 0

Patch set updated for coreboot: mainboard/kontron/986lcd-m: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16820 -gerrit commit c1d176cba89e6db52c0f9569ff14784d51a74ad8 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 20:29:54 2016 +0200 mainboard/kontron/986lcd-m: Use tabs for indents Change-Id: Ibeb0da2f75b4aec32f5238e5634bc1f1d8220b84 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/kontron/986lcd-m/devicetree.cb | 98 ++++++++++++++-------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index b9ddf75..6795cdc 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -3,19 +3,19 @@ chip northbridge/intel/i945 register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end - device domain 0 on - device pci 00.0 on end # host bridge + device domain 0 on + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller - chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" register "pirqc_routing" = "0x0b" @@ -31,45 +31,45 @@ chip northbridge/intel/i945 # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x1" - register "sata_ahci" = "0x0" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x1" + register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/winbond/w83627thg + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627thg device pnp 2e.0 off # Floppy end device pnp 2e.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 5 end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end + end device pnp 2e.5 on # Keyboard+Mouse io 0x60 = 0x60 io 0x62 = 0x64 @@ -96,21 +96,21 @@ chip northbridge/intel/i945 irq 0x70 = 0 end - end - chip superio/winbond/w83627thg - device pnp 4e.0 off # Floppy + end + chip superio/winbond/w83627thg + device pnp 4e.0 off # Floppy end device pnp 4e.1 off # Parport end - device pnp 4e.2 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 6 - end - device pnp 4e.3 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 6 + device pnp 4e.2 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 6 + end + device pnp 4e.3 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 6 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end + end device pnp 4e.5 off # Keyboard end device pnp 4e.7 off # GPIO1, GAME, MIDI @@ -123,13 +123,13 @@ chip northbridge/intel/i945 end device pnp 4e.b off # HWM end - end + end - end + end #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus #device pci 1f.4 off end # Realtek ID Codec - end - end + end + end end

1 0

New patch to review for coreboot: mainboard/kontron/986lcd-m: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16820 -gerrit commit 4e10c22145036d7b15d922272c69bd27bdb115be Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 20:29:54 2016 +0200 mainboard/kontron/986lcd-m: Use tabs for indents Change-Id: Ibeb0da2f75b4aec32f5238e5634bc1f1d8220b84 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/kontron/986lcd-m/devicetree.cb | 98 ++++++++++++++-------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index b9ddf75..f2cb35d 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -3,19 +3,19 @@ chip northbridge/intel/i945 register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end - device domain 0 on - device pci 00.0 on end # host bridge + device domain 0 on + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller - chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" register "pirqc_routing" = "0x0b" @@ -31,45 +31,45 @@ chip northbridge/intel/i945 # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x1" - register "sata_ahci" = "0x0" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x1" + register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/winbond/w83627thg + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627thg device pnp 2e.0 off # Floppy end device pnp 2e.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 5 end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end + end device pnp 2e.5 on # Keyboard+Mouse io 0x60 = 0x60 io 0x62 = 0x64 @@ -96,21 +96,21 @@ chip northbridge/intel/i945 irq 0x70 = 0 end - end - chip superio/winbond/w83627thg - device pnp 4e.0 off # Floppy + end + chip superio/winbond/w83627thg + device pnp 4e.0 off # Floppy end device pnp 4e.1 off # Parport end - device pnp 4e.2 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 6 - end - device pnp 4e.3 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 6 + device pnp 4e.2 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 6 + end + device pnp 4e.3 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 6 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end + end device pnp 4e.5 off # Keyboard end device pnp 4e.7 off # GPIO1, GAME, MIDI @@ -123,13 +123,13 @@ chip northbridge/intel/i945 end device pnp 4e.b off # HWM end - end + end - end + end #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus #device pci 1f.4 off end # Realtek ID Codec - end - end + end + end end

1 0

Patch set updated for coreboot: mainboard/intel/quark: Add FSP selection values
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16806 -gerrit commit 5de6e04578080fa099dbce6b44620761c9841328 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 14:10:06 2016 -0700 mainboard/intel/quark: Add FSP selection values Add Kconfig values to select the FSP setup: * FSP version: 1.1 or 2.0 * Implementation: Subroutine or SEC/PEI core based * Build type: DEBUG or RELEASE * Enable all debugging for FSP * Remove USE_FSP1_1 and USE_FSP2_0 Look for include files in vendorcode/intel/fsp/fsp???/quark BRANCH=none BUG=None TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2 Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 108 ++++++++++- src/mainboard/intel/galileo/Makefile.inc | 4 +- src/soc/intel/quark/include/soc/fsp/FspEas.h | 42 ----- src/soc/intel/quark/include/soc/fsp/FspUpd.h | 44 ----- src/soc/intel/quark/include/soc/fsp/FspmUpd.h | 235 ----------------------- src/soc/intel/quark/include/soc/fsp/FspsUpd.h | 52 ------ src/soc/intel/quark/include/soc/fsp/FsptUpd.h | 89 --------- src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h | 48 +++++ src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h | 239 ++++++++++++++++++++++++ src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h | 56 ++++++ src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h | 93 +++++++++ 11 files changed, 537 insertions(+), 473 deletions(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 2acc439..0c1fe5b 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,11 +18,10 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - select CREATE_BOARD_CHECKLIST +# select CREATE_BOARD_CHECKLIST select ENABLE_BUILTIN_HSUART1 select HAVE_ACPI_TABLES select SOC_INTEL_QUARK - select USE_FSP1_1 config MAINBOARD_DIR string @@ -45,16 +44,107 @@ config GALILEO_GEN2 runtime. Select which generation of the Galileo that coreboot should initialize. -config USE_FSP1_1 - bool - default n +choice + prompt "FSP version" + default FSP_VERSION_1_1 + +config FSP_VERSION_1_1 + bool "FSP 1.1" + select CREATE_BOARD_CHECKLIST select PLATFORM_USES_FSP1_1 # select ADD_FSP_RAW_BIN - -config USE_FSP2_0 - bool - default n + help + Use FSP 1_1 binary +config FSP_VERSION_2_0 + bool "FSP 2.0" select PLATFORM_USES_FSP2_0 select POSTCAR_STAGE + help + Use FSP 2.0 binary + +endchoice + +config FSP_VERSION + string + default "fsp1_1" if FSP_VERSION_1_1 + default "fsp2_0" if FSP_VERSION_2_0 + +choice + prompt "FSP binary type" + default FSP_BUILD_TYPE_DEBUG + +config FSP_BUILD_TYPE_DEBUG + bool "Debug" + help + Use the debug version of FSP +config FSP_BUILD_TYPE_RELEASE + bool "Release" + help + Use the release version of FSP + +endchoice + +config FSP_BUILD_TYPE + string + default "DEBUG" if FSP_BUILD_TYPE_DEBUG + default "RELEASE" if FSP_BUILD_TYPE_RELEASE + +choice + prompt "FSP type" + depends on FSP_VERSION_2_0 || FSP_VERSION_1_1 + default FSP_TYPE_1_1_PEI if FSP_VERSION_1_1 + default FSP_TYPE_2_0_PEI if FSP_VERSION_2_0 + +config FSP_TYPE_1_1 + bool "MemInit subroutine" + depends on FSP_VERSION_1_1 + help + FSP 1.1 implemented as subroutines, no EDK-II cores +config FSP_TYPE_1_1_PEI + bool "SEC + PEI Core + MemInit PEIM" + depends on FSP_VERSION_1_1 + help + FSP 1.1 implemented using SEC and PEI core +config FSP_TYPE_2_0 + bool "MemInit subroutine" + depends on FSP_VERSION_2_0 + help + FSP 2.0 implemented as subroutines, no EDK-II cores +config FSP_TYPE_2_0_PEI + bool "SEC + PEI Core + MemInit PEIM" + depends on FSP_VERSION_2_0 + help + FSP 2.0 implemented using SEC and PEI core + +endchoice + +config FSP_TYPE + string + default "Fsp1_1" if FSP_TYPE_1_1 + default "Fsp1_1Pei" if FSP_TYPE_1_1_PEI + default "Fsp2_0" if FSP_TYPE_2_0 + default "Fsp2_0Pei" if FSP_TYPE_2_0_PEI + +config FSP_DEBUG_ALL + bool "Enable all FSP debug support" + depends on FSP_VERSION_2_0 || FSP_VERSION_1_1 + default y +# Enable display and verification for coreboot build tests + select BOOTBLOCK_CONSOLE + select DISPLAY_HOBS + select DISPLAY_MTRRS + select DISPLAY_SMM_MEMORY_MAP + select DISPLAY_UPD_DATA + select DISPLAY_ESRAM_LAYOUT if FSP_VERSION_2_0 + select DISPLAY_FSP_CALLS_AND_STATUS if FSP_VERSION_2_0 + select DISPLAY_FSP_HEADER if FSP_VERSION_2_0 + select POSTCAR_CONSOLE if FSP_VERSION_2_0 + select VERIFY_HOBS if FSP_VERSION_2_0 + select DISPLAY_FSP_ENTRY_POINTS if FSP_VERSION_1_1 + help + Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA + also turn on FSP 2.0 debug support for ESRAM_LAYOUT, + FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS + or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS endif # BOARD_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index efaf007..16b2b4a 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -13,8 +13,8 @@ ## GNU General Public License for more details. ## -ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark +ifeq ($(CONFIG_PLATFORM_USES_FSP2_0)$(CONFIG_PLATFORM_USES_FSP1_1),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/$(CONFIG_FSP_VERSION)/quark endif bootblock-y += gpio.c diff --git a/src/soc/intel/quark/include/soc/fsp/FspEas.h b/src/soc/intel/quark/include/soc/fsp/FspEas.h deleted file mode 100644 index 48d956e..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FspEas.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPEAS_H__ -#define __FSPEAS_H__ - -#include <fsp/upd.h> -#include <soc/fsp/FspmUpd.h> -#include <soc/fsp/FspsUpd.h> -#include <soc/fsp/FsptUpd.h> -#include <fsp/api.h> - -#endif /* _FSPEAS_H_ */ diff --git a/src/soc/intel/quark/include/soc/fsp/FspUpd.h b/src/soc/intel/quark/include/soc/fsp/FspUpd.h deleted file mode 100644 index d3277d9..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FspUpd.h +++ /dev/null @@ -1,44 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ - -#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h deleted file mode 100644 index a7a54a8..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h +++ /dev/null @@ -1,235 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - - -/** Fsp M Configuration -**/ -struct FSP_M_CONFIG { - -/** Offset 0x0040 - RmuBaseAddress - RMU microcode binary base address in SPI flash' -**/ - uint32_t RmuBaseAddress; - -/** Offset 0x0044 - RmuLength - RMU microcode binary length in bytes -**/ - uint32_t RmuLength; - -/** Offset 0x0048 - SerialPortBaseAddress - Debug serial port base address set by BIOS. Zero disables debug serial output. -**/ - uint32_t Reserved_48; - -/** Offset 0x004C - tRAS - ACT to PRE command period in picoseconds. -**/ - uint32_t tRAS; - -/** Offset 0x0050 - tWTR - Delay from start of internal write transaction to internal read command in picoseconds. -**/ - uint32_t tWTR; - -/** Offset 0x0054 - tRRD - ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. -**/ - uint32_t tRRD; - -/** Offset 0x0058 - tFAW - Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. -**/ - uint32_t tFAW; - -/** Offset 0x005C - Flags - Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN - BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" - topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices - on writes. -**/ - uint32_t Flags; - -/** Offset 0x0060 - DramWidth - 0=x8, 1=x16, others=RESERVED. -**/ - uint8_t DramWidth; - -/** Offset 0x0061 - DramSpeed - 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. -**/ - uint8_t DramSpeed; - -/** Offset 0x0062 - DramType - 0=DDR3, 1=DDR3L, others=RESERVED. -**/ - uint8_t DramType; - -/** Offset 0x0063 - RankMask - bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. -**/ - uint8_t RankMask; - -/** Offset 0x0064 - ChanMask - bit[0] CHAN0_EN, others=RESERVED. -**/ - uint8_t ChanMask; - -/** Offset 0x0065 - ChanWidth - 1=x16, others=RESERVED. -**/ - uint8_t ChanWidth; - -/** Offset 0x0066 - AddrMode - 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. -**/ - uint8_t AddrMode; - -/** Offset 0x0067 - SrInt - 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. -**/ - uint8_t SrInt; - -/** Offset 0x0068 - SrTemp - 0=normal, 1=extended, others=RESERVED. -**/ - uint8_t SrTemp; - -/** Offset 0x0069 - DramRonVal - 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. -**/ - uint8_t DramRonVal; - -/** Offset 0x006A - DramRttNomVal - 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. -**/ - uint8_t DramRttNomVal; - -/** Offset 0x006B - DramRttWrVal - 0=off others=RESERVED. -**/ - uint8_t DramRttWrVal; - -/** Offset 0x006C - SocRdOdtVal - 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. -**/ - uint8_t SocRdOdtVal; - -/** Offset 0x006D - SocWrRonVal - 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. -**/ - uint8_t SocWrRonVal; - -/** Offset 0x006E - SocWrSlewRate - 0=2.5V/ns, 1=4V/ns, others=RESERVED. -**/ - uint8_t SocWrSlewRate; - -/** Offset 0x006F - DramDensity - 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. -**/ - uint8_t DramDensity; - -/** Offset 0x0070 - tCL - DRAM CAS Latency in clocks -**/ - uint8_t tCL; - -/** Offset 0x0071 - EccScrubInterval - ECC scrub interval in miliseconds 1..255 (0 works as feature disable -**/ - uint8_t EccScrubInterval; - -/** Offset 0x0072 - EccScrubBlkSize - Number of 32B blocks read for ECC scrub 2..16 -**/ - uint8_t EccScrubBlkSize; - -/** Offset 0x0073 - SmmTsegSize - Size of the SMM region in 1 MiB chunks -**/ - uint8_t SmmTsegSize; - -/** Offset 0x0074 - FspReservedMemoryLength - FSP reserved memory length in bytes -**/ - uint32_t FspReservedMemoryLength; - -/** Offset 0x0078 - MrcDataPtr - Pointer to saved MRC data -**/ - uint32_t MrcDataPtr; - -/** Offset 0x007C - MrcDataLength - Length of saved MRC data -**/ - uint32_t MrcDataLength; - -/** Offset 0x0080 -**/ - uint32_t SerialPortPollForChar; - -/** Offset 0x0084 -**/ - uint32_t SerialPortReadChar; - -/** Offset 0x0088 -**/ - uint32_t SerialPortWriteChar; - -/** Offset 0x008C -**/ - uint16_t UpdTerminator; -} __attribute__((packed)); - -/** Fsp M UPD Configuration -**/ -struct FSPM_UPD { - -/** Offset 0x0000 -**/ - struct FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - struct FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - struct FSP_M_CONFIG FspmConfig; -} __attribute__((packed)); - -#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspsUpd.h b/src/soc/intel/quark/include/soc/fsp/FspsUpd.h deleted file mode 100644 index 6b054e8..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FspsUpd.h +++ /dev/null @@ -1,52 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - - -/** Fsp S UPD Configuration -**/ -struct FSPS_UPD { - -/** Offset 0x0000 -**/ - struct FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - uint16_t UpdTerminator; -} __attribute__((packed)); - -#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FsptUpd.h b/src/soc/intel/quark/include/soc/fsp/FsptUpd.h deleted file mode 100644 index 8b1ded7..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FsptUpd.h +++ /dev/null @@ -1,89 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include <FspUpd.h> - - -/** Fsp T Common UPD -**/ -struct FSPT_COMMON_UPD { - -/** Offset 0x0020 -**/ - uint8_t Revision; - -/** Offset 0x0021 -**/ - uint8_t Reserved[3]; - -/** Offset 0x0024 -**/ - uint32_t MicrocodeRegionBase; - -/** Offset 0x0028 -**/ - uint32_t MicrocodeRegionLength; - -/** Offset 0x002C -**/ - uint32_t CodeRegionBase; - -/** Offset 0x0030 -**/ - uint32_t CodeRegionLength; - -/** Offset 0x0034 -**/ - uint8_t Reserved1[12]; -} __attribute__((packed)); - -/** Fsp T UPD Configuration -**/ -struct FSPT_UPD { - -/** Offset 0x0000 -**/ - struct FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - struct FSPT_COMMON_UPD FsptCommonUpd; - -/** Offset 0x0040 -**/ - uint16_t UpdTerminator; -} __attribute__((packed)); - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h new file mode 100644 index 0000000..cfd1ac0 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(push, 1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h new file mode 100644 index 0000000..28e4d21 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h @@ -0,0 +1,239 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - RmuBaseAddress + RMU microcode binary base address in SPI flash' +**/ + UINT32 RmuBaseAddress; + +/** Offset 0x0044 - RmuLength + RMU microcode binary length in bytes +**/ + UINT32 RmuLength; + +/** Offset 0x0048 - SerialPortBaseAddress + Debug serial port base address set by BIOS. Zero disables debug serial output. +**/ + UINT32 Reserved_48; + +/** Offset 0x004C - tRAS + ACT to PRE command period in picoseconds. +**/ + UINT32 tRAS; + +/** Offset 0x0050 - tWTR + Delay from start of internal write transaction to internal read command in picoseconds. +**/ + UINT32 tWTR; + +/** Offset 0x0054 - tRRD + ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + UINT32 tRRD; + +/** Offset 0x0058 - tFAW + Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + UINT32 tFAW; + +/** Offset 0x005C - Flags + Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN + BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" + topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices + on writes. +**/ + UINT32 Flags; + +/** Offset 0x0060 - DramWidth + 0=x8, 1=x16, others=RESERVED. +**/ + UINT8 DramWidth; + +/** Offset 0x0061 - DramSpeed + 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. +**/ + UINT8 DramSpeed; + +/** Offset 0x0062 - DramType + 0=DDR3, 1=DDR3L, others=RESERVED. +**/ + UINT8 DramType; + +/** Offset 0x0063 - RankMask + bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. +**/ + UINT8 RankMask; + +/** Offset 0x0064 - ChanMask + bit[0] CHAN0_EN, others=RESERVED. +**/ + UINT8 ChanMask; + +/** Offset 0x0065 - ChanWidth + 1=x16, others=RESERVED. +**/ + UINT8 ChanWidth; + +/** Offset 0x0066 - AddrMode + 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. +**/ + UINT8 AddrMode; + +/** Offset 0x0067 - SrInt + 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. +**/ + UINT8 SrInt; + +/** Offset 0x0068 - SrTemp + 0=normal, 1=extended, others=RESERVED. +**/ + UINT8 SrTemp; + +/** Offset 0x0069 - DramRonVal + 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. +**/ + UINT8 DramRonVal; + +/** Offset 0x006A - DramRttNomVal + 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. +**/ + UINT8 DramRttNomVal; + +/** Offset 0x006B - DramRttWrVal + 0=off others=RESERVED. +**/ + UINT8 DramRttWrVal; + +/** Offset 0x006C - SocRdOdtVal + 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. +**/ + UINT8 SocRdOdtVal; + +/** Offset 0x006D - SocWrRonVal + 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. +**/ + UINT8 SocWrRonVal; + +/** Offset 0x006E - SocWrSlewRate + 0=2.5V/ns, 1=4V/ns, others=RESERVED. +**/ + UINT8 SocWrSlewRate; + +/** Offset 0x006F - DramDensity + 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. +**/ + UINT8 DramDensity; + +/** Offset 0x0070 - tCL + DRAM CAS Latency in clocks +**/ + UINT8 tCL; + +/** Offset 0x0071 - EccScrubInterval + ECC scrub interval in miliseconds 1..255 (0 works as feature disable +**/ + UINT8 EccScrubInterval; + +/** Offset 0x0072 - EccScrubBlkSize + Number of 32B blocks read for ECC scrub 2..16 +**/ + UINT8 EccScrubBlkSize; + +/** Offset 0x0073 - SmmTsegSize + Size of the SMM region in 1 MiB chunks +**/ + UINT8 SmmTsegSize; + +/** Offset 0x0074 - FspReservedMemoryLength + FSP reserved memory length in bytes +**/ + UINT32 FspReservedMemoryLength; + +/** Offset 0x0078 - MrcDataPtr + Pointer to saved MRC data +**/ + UINT32 MrcDataPtr; + +/** Offset 0x007C - MrcDataLength + Length of saved MRC data +**/ + UINT32 MrcDataLength; + +/** Offset 0x0080 +**/ + UINT32 SerialPortPollForChar; + +/** Offset 0x0084 +**/ + UINT32 SerialPortReadChar; + +/** Offset 0x0088 +**/ + UINT32 SerialPortWriteChar; + +/** Offset 0x008C +**/ + UINT16 UpdTerminator; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; +} FSPM_UPD; + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h new file mode 100644 index 0000000..a613000 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h @@ -0,0 +1,56 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h new file mode 100644 index 0000000..02a1e09 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h @@ -0,0 +1,93 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp T Common UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT8 Revision; + +/** Offset 0x0021 +**/ + UINT8 Reserved[3]; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0028 +**/ + UINT32 MicrocodeRegionLength; + +/** Offset 0x002C +**/ + UINT32 CodeRegionBase; + +/** Offset 0x0030 +**/ + UINT32 CodeRegionLength; + +/** Offset 0x0034 +**/ + UINT8 Reserved1[12]; +} FSPT_COMMON_UPD; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_COMMON_UPD FsptCommonUpd; + +/** Offset 0x0040 +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack(pop) + +#endif

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coreboot-gerrit September 2016