coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mainboard/gigabyte/m57sli/romstage.c: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16815 -gerrit commit e0627eea64157f6cd6d2a6a75b1d3e7f007c9984 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 19:13:36 2016 +0200 mainboard/gigabyte/m57sli/romstage.c: Use tabs for indents Change-Id: Ib439e5d96543790d17934bd477af62d39a5958b6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/gigabyte/m57sli/romstage.c | 120 +++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index f8d12c6..e7f3ee5 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -72,20 +72,20 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + uint32_t dword; + uint8_t byte; - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1 << 0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1 << 16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1 << 16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -99,18 +99,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = &sysinfo_car; - int needs_reset = 0; - unsigned bsp_apicid = 0; + struct sys_info *sysinfo = &sysinfo_car; + int needs_reset = 0; + unsigned bsp_apicid = 0; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + } - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); #if 0 @@ -133,71 +133,71 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - setup_mb_resource_map(); + setup_mb_resource_map(); - console_init(); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); // routing table and start other core0 + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + setup_coherent_ht_domain(); // routing table and start other core0 - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif - /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } #endif init_timer(); // Need to use TMICT to synchronize FID/VID - needs_reset |= optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - needs_reset |= mcp55_early_setup_x(); + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= mcp55_early_setup_x(); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } - allow_all_aps_stop(bsp_apicid); + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } + allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - enable_smbus(); + enable_smbus(); - /* all ap stopped? */ + /* all ap stopped? */ - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }

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New patch to review for coreboot: mainboard/google/stout/romstage.c: Use tabs for indents
by HAOUAS Elyes 29 Sep '16

29 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16814 -gerrit commit a45ec6d7d16a651a8346c8cf8fa997867983a866 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Sep 29 18:57:56 2016 +0200 mainboard/google/stout/romstage.c: Use tabs for indents Change-Id: I2402648b8c0b9dcc730ce7f099e1e4ccef3b79fc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/google/stout/romstage.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 7264323..e486451 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -218,19 +218,19 @@ void mainboard_config_superio(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled usb oc pin length */ - {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ - {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ - {0, 0, 0}, /* P2: Empty */ - {1, 0, -1}, /* P3: Camera (no OC) */ - {1, 0, -1}, /* P4: WLAN (no OC) */ - {1, 0, -1}, /* P5: WWAN (no OC) */ - {0, 0, 0}, /* P6: Empty */ - {0, 0, 0}, /* P7: Empty */ - {0, 0, 0}, /* P8: Empty */ - {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ - {0, 0, 0}, /* P10: Empty */ - {0, 0, 0}, /* P11: Empty */ - {0, 0, 0}, /* P12: Empty */ - {1, 0, -1}, /* P13: Bluetooth (no OC) */ + /* enabled usb oc pin length */ + {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, /* P2: Empty */ + {1, 0, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, /* P6: Empty */ + {0, 0, 0}, /* P7: Empty */ + {0, 0, 0}, /* P8: Empty */ + {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, /* P10: Empty */ + {0, 0, 0}, /* P11: Empty */ + {0, 0, 0}, /* P12: Empty */ + {1, 0, -1}, /* P13: Bluetooth (no OC) */ };

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New patch to review for coreboot: mainboard/google/reef: unconditionally set MAINBOARD_FAMILY
by Aaron Durbin 29 Sep '16

29 Sep '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16813 -gerrit commit 13163315fe116c3feffd972279abd796543cd36d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 29 09:54:46 2016 -0500 mainboard/google/reef: unconditionally set MAINBOARD_FAMILY For all mainboard variants use the "Google_Reef" family by defailt which is populated in SMBIOS tables. A variant can provide their own value if needed, but "Google_Reef" can reside as the family without having to add conditions for each variant when MAINBOARD_FAMILY have to be overridden. BUG=chrome-os-partner:56677 Change-Id: Ic214eae1e6473b32f4cb442c09c34355357e1257 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5039725..41be695 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -58,7 +58,7 @@ config MAINBOARD_PART_NUMBER config MAINBOARD_FAMILY string - default "Google_Reef" if BOARD_GOOGLE_REEF + default "Google_Reef" config GBB_HWID string

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Patch merged into coreboot/master: mainboard/elmex: Add new board pcm205401
by gerrit＠coreboot.org 29 Sep '16

29 Sep '16

the following patch was just integrated into master: commit 4951677b16568f5299016fd26c51001b28651812 Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Tue Aug 2 08:51:59 2016 +0300 mainboard/elmex: Add new board pcm205401 pcm205401 is CPU board equipped with T40R of AMD. We used SeaBIOS and Windows Embedded Standard 7 to test pcm205401. In comparison to pcm205400, only VGA PCI ID is changed and board identifier strings in SMBIOS / DMI. Change-Id: I6c7e90db84f13ffbf9e629f2b92649895a466155 Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> Reviewed-on: https://review.coreboot.org/15930 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15930 for details. -gerrit

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Patch merged into coreboot/master: mainboard/elmex: Add new board pcm205400
by gerrit＠coreboot.org 29 Sep '16

29 Sep '16

the following patch was just integrated into master: commit c4ddfe45a8067473a63cdf066f50ae2345478548 Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 mainboard/elmex: Add new board pcm205400 pcm205400 is CPU board equipped with T56N of AMD. We used SeaBIOS and Windows Embedded Standard 7 to test pcm205400. I disable the port5, 6, and 7 of the PCI-e in elmex/pcm205400/PlatformGnbPcieComplex.h. I disable the audio capabilities at the 236th line of elmex/pcm205400/platform_cfg.h. Coding style is modified to avoid the error and warning that occur when I commit. Change-Id: I77cb76903fe3c1b500a306426f5399936382695b Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> Reviewed-on: https://review.coreboot.org/15929 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15929 for details. -gerrit

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Patch merged into coreboot/master: src/mainboard: Add vendor ELMEX with a board
by gerrit＠coreboot.org 29 Sep '16

29 Sep '16

the following patch was just integrated into master: commit b31c3d1b921e45d26a2fdade45e82ca3a8af5c74 Author: Yuichi Ito <yui.corebt(a)gmail.com> Date: Thu Jul 28 13:34:18 2016 +0900 src/mainboard: Add vendor ELMEX with a board Add board with amd/persimmon as template. Change-Id: I263b54e0f49b6f1ba730c7f87de41f990ba8fe67 Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com> Reviewed-on: https://review.coreboot.org/15926 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15926 for details. -gerrit

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Patch set updated for coreboot: soc/intel/fsp_broadwell_de/uart: Drop it
by Nico Huber 29 Sep '16

29 Sep '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16786 -gerrit commit db6d0e11c939a400fe78f9fc74637dd012761ceb Author: Nico Huber <nico.h(a)gmx.de> Date: Wed Sep 28 22:15:07 2016 +0200 soc/intel/fsp_broadwell_de/uart: Drop it A copy of our uart8250io driver sneaked in with Broadwell-DE support. The only difference is the lack of initialization (due to FSP handling that). TEST=manually compared resulting object files Change-Id: I09be10b76c76c1306ad2c8db8fb07794dde1b0f2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/drivers/uart/Kconfig | 4 + src/drivers/uart/uart8250io.c | 10 ++- src/soc/intel/fsp_broadwell_de/Kconfig | 10 +-- src/soc/intel/fsp_broadwell_de/Makefile.inc | 6 -- src/soc/intel/fsp_broadwell_de/uart.c | 112 ---------------------------- 5 files changed, 12 insertions(+), 130 deletions(-) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 4faa48d..dafdff1 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -9,6 +9,10 @@ config DRIVERS_UART_8250IO default n if NO_UART_ON_SUPERIO default y if ARCH_X86 +config DRIVERS_UART_8250IO_SKIP_INIT + def_bool n + depends on DRIVERS_UART_8250IO + # Select this for mainboard without SuperIO serial port. config NO_UART_ON_SUPERIO def_bool n diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 89c4476..ac3315a 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -104,10 +104,12 @@ uintptr_t uart_platform_base(int idx) void uart_init(int idx) { - unsigned int div; - div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), - uart_input_clock_divider()); - uart8250_init(uart_platform_base(idx), div); + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250IO_SKIP_INIT)) { + unsigned int div; + div = uart_baudrate_divisor(default_baudrate(), + uart_platform_refclk(), uart_input_clock_divider()); + uart8250_init(uart_platform_base(idx), div); + } } void uart_tx_byte(int idx, unsigned char data) diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 99a2bfd..bedf291 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -61,18 +61,12 @@ config VGA_BIOS config INTEGRATED_UART bool "Integrated UART ports" default y - select HAVE_UART_SPECIAL + select DRIVERS_UART_8250IO + select DRIVERS_UART_8250IO_SKIP_INIT select CONSOLE_SERIAL help Use Broadwell-DE Integrated UART ports @3F8h and 2F8h. -config DRIVERS_UART_8250IO - bool "Serial port on SuperIO (Broadwell-DE's UART ports unselected)" - depends on !INTEGRATED_UART - help - Select to choose SuperIO's serial port for console output. - CANNOT select if intend to use SoC integrated serial ports. - config CONSOLE_CBMEM bool "Send console output to a CBMEM buffer" default n diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 41ae43e..657f70c 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -24,12 +24,6 @@ ramstage-y += acpi.c ramstage-y += smbus_common.c ramstage-y += smbus.c -ifeq ($(CONFIG_INTEGRATED_UART),y) -romstage-y += uart.c -ramstage-y += uart.c -smm-$(CONFIG_DEBUG_SMI) += uart.c -endif - CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/ diff --git a/src/soc/intel/fsp_broadwell_de/uart.c b/src/soc/intel/fsp_broadwell_de/uart.c deleted file mode 100644 index d22dd0d..0000000 --- a/src/soc/intel/fsp_broadwell_de/uart.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2015-2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <rules.h> -#include <stdlib.h> -#include <arch/io.h> -#include <console/uart.h> -#include <trace.h> -#include <drivers/uart/uart8250reg.h> - -#ifndef __ROMCC__ -#include <boot/coreboot_tables.h> -#endif - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - * - * Estimated that inb() from UART takes 1 microsecond. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static int uart8250_can_tx_byte(unsigned base_port) -{ - return inb(base_port + UART8250_LSR) & UART8250_LSR_THRE; -} - -static void uart8250_tx_byte(unsigned base_port, unsigned char data) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_tx_byte(base_port)); - outb(data, base_port + UART8250_TBR); -} - -static void uart8250_tx_flush(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while (i-- && !(inb(base_port + UART8250_LSR) & UART8250_LSR_TEMT)); -} - -static int uart8250_can_rx_byte(unsigned base_port) -{ - return inb(base_port + UART8250_LSR) & UART8250_LSR_DR; -} - -static unsigned char uart8250_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_rx_byte(base_port)); - - if (i) - return inb(base_port + UART8250_RBR); - else - return 0x0; -} - -static const unsigned bases[] = { 0x3f8, 0x2f8 }; - -uintptr_t uart_platform_base(int idx) -{ - if (idx < ARRAY_SIZE(bases)) - return bases[idx]; - return 0; -} - -void uart_init(int idx) -{ - // No needed to configure as setting has been done in BDX-DE FSP -} - -void uart_tx_byte(int idx, unsigned char data) -{ - uart8250_tx_byte(uart_platform_base(idx), data); -} - -unsigned char uart_rx_byte(int idx) -{ - return uart8250_rx_byte(uart_platform_base(idx)); -} - -void uart_tx_flush(int idx) -{ - uart8250_tx_flush(uart_platform_base(idx)); -} - -#if ENV_RAMSTAGE -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_IO_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = default_baudrate(); - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); -} -#endif

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Patch set updated for coreboot: mainboard/google/reef: Update DPTF policy temp. values for CPU
by Sumeet R Pawnikar 29 Sep '16

29 Sep '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16766 -gerrit commit 9eb7250d81c07e972aca654f9c9a55e1df65ae67 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Sep 27 11:55:24 2016 +0530 mainboard/google/reef: Update DPTF policy temp. values for CPU This patch increases the CPU specific passive temp. trip point and critical temp. trip point value for DPTF policy. BUG=chrome-os-partner:57903 TEST=Built, booted on reef and verified this passive and critical temp. trip points with heavy workload. Change-Id: I2a38d01a6539c1bd478f8716c4b543ebcd1f2080 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- .../google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl index 8c18687..43e2e93 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 80 #define DPTF_CPU_ACTIVE_AC2 70

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Patch set updated for coreboot: vboot: clear tpm when required
by Vadim Bendebury 29 Sep '16

29 Sep '16

Vadim Bendebury (vbendeb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16805 -gerrit commit a9929da5a4317e8c26642d156cfde080d7c0ae1a Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 28 18:59:39 2016 -0700 vboot: clear tpm when required Function which invoked when TPM clear is requested was left empty, this patch fixes it. BRANCH=gru BUG=chrome-os-partner:57411 TEST=verified on a chromeos device that tpm is in fact cleared when CLEAR_TPM_OWNER_REQUEST is set by userland. Change-Id: I4370792afd512309ecf7f4961ed4d44a04a3e2aa Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/vboot/secdata_tpm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vboot/secdata_tpm.c b/src/vboot/secdata_tpm.c index a51e5d6..76b90ab 100644 --- a/src/vboot/secdata_tpm.c +++ b/src/vboot/secdata_tpm.c @@ -154,6 +154,7 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) uint32_t tpm_clear_and_reenable(void) { VBDEBUG("TPM: Clear and re-enable\n"); + RETURN_ON_FAILURE(tlcl_force_clear()); return TPM_SUCCESS; }

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New patch to review for coreboot: mainboard/intel/galileo: Make FSP 2.0 the default
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16810 -gerrit commit 97d1dac816857db1908359f13b8bdf9e2ced0a76 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 17:28:00 2016 -0700 mainboard/intel/galileo: Make FSP 2.0 the default Switch from FSP 1.1 to FSP 2.0 as the default build. BRANCH=none BUG=None TEST=Build and run on Galileo Gen2 Change-Id: Icbb3a36cdde68baf4d68fbfc371f8847c56e1162 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 0c1fe5b..e941448 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -46,7 +46,7 @@ config GALILEO_GEN2 choice prompt "FSP version" - default FSP_VERSION_1_1 + default FSP_VERSION_2_0 config FSP_VERSION_1_1 bool "FSP 1.1"

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coreboot-gerrit September 2016