coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: drivers/intel/fsp2_0: Fix debug display support
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16809 -gerrit commit 122f6ea1803cdbfcb75d2576459515170ccb9e50 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 17:15:00 2016 -0700 drivers/intel/fsp2_0: Fix debug display support Fix errors in debug display support. BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug on) and run on Galileo Gen2 Change-Id: I2ece056d66dc8568a7b7206970f20368ec5bf147 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/drivers/intel/fsp2_0/graphics.c | 5 ----- src/drivers/intel/fsp2_0/hand_off_block.c | 11 ----------- src/drivers/intel/fsp2_0/hob_display.c | 7 ++++++- src/drivers/intel/fsp2_0/include/fsp/util.h | 11 +++++++++++ src/drivers/intel/fsp2_0/upd_display.c | 10 +++++----- 5 files changed, 22 insertions(+), 22 deletions(-) diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index caf7bfa..bc1deb5 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -20,11 +20,6 @@ enum pixel_format { pixel_bitmask = 2, /* defined by <rgb>_mask values */ }; -const uint8_t fsp_graphics_info_guid[16] = { - 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, - 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 -}; - struct hob_graphics_info { uint64_t framebuffer_base; uint32_t framebuffer_size; diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 17adf46..a8b9878 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -22,17 +22,6 @@ #define HOB_HEADER_LEN 8 -enum resource_type { - EFI_RESOURCE_SYSTEM_MEMORY = 0, - EFI_RESOURCE_MEMORY_MAPPED_IO = 1, - EFI_RESOURCE_IO = 2, - EFI_RESOURCE_FIRMWARE_DEVICE = 3, - EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4, - EFI_RESOURCE_MEMORY_RESERVED = 5, - EFI_RESOURCE_IO_RESERVED = 6, - EFI_RESOURCE_MAX_MEMORY_TYPE = 7, -}; - /* GUIDs in little-endian, so they can be used with memcmp() */ const uint8_t fsp_bootloader_tolum_guid[16] = { 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index 39a9d17..6e6a915 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -51,6 +51,11 @@ static const uint8_t empty_guid[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +const uint8_t fsp_graphics_info_guid[16] = { + 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 +}; + static const uint8_t fsp_info_header_guid[16] = { 0xbe, 0x40, 0x27, 0x91, 0x84, 0x22, 0x34, 0x47, 0xb9, 0x71, 0x84, 0xb0, 0x27, 0x35, 0x3f, 0x0c @@ -78,7 +83,7 @@ static const struct guid_name_map guid_names[] = { { fsp_info_header_guid, "FSP_INFO_HEADER_GUID" }, { fsp_reserved_memory_guid, "FSP_RESERVED_MEMORY" }, { fsp_nv_storage_guid, "FSP_NV_STORAGE" }, - { graphics_info_guid, "GRAPHICS INFO" }, + { fsp_graphics_info_guid, "GRAPHICS INFO" }, { smbios_memory_info_guid, "FSP_SMBIOS_MEMORY_INFO_GUID" }, { tseg_guid, "TSEG" }, }; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index acb41e0..5f08856 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -37,6 +37,17 @@ struct hob_resource { uint64_t length; } __attribute__((packed)); +enum resource_type { + EFI_RESOURCE_SYSTEM_MEMORY = 0, + EFI_RESOURCE_MEMORY_MAPPED_IO = 1, + EFI_RESOURCE_IO = 2, + EFI_RESOURCE_FIRMWARE_DEVICE = 3, + EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4, + EFI_RESOURCE_MEMORY_RESERVED = 5, + EFI_RESOURCE_IO_RESERVED = 6, + EFI_RESOURCE_MAX_MEMORY_TYPE = 7, +}; + enum hob_type { HOB_TYPE_HANDOFF = 0x0001, HOB_TYPE_MEMORY_ALLOCATION = 0x0002, diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index a588358..1ef657d 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -19,15 +19,15 @@ void fsp_display_upd_value(const char *name, size_t size, uint64_t old, { size *= 2; if (old == new) { - printk(BIOS_SPEW, " 0x%0*llx: %s\n", size, new, name); + printk(BIOS_SPEW, " 0x%0*llx: %s\n", (int)size, new, name); } else { - printk(BIOS_SPEW, " 0x%0*llx --> 0x%0*llx: %s\n", size, old, - size, new, name); + printk(BIOS_SPEW, " 0x%0*llx --> 0x%0*llx: %s\n", (int)size, old, + (int)size, new, name); } } -static void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old, - const struct FSPM_ARCH_UPD *new) +static void fspm_display_arch_params(const FSPM_ARCH_UPD *old, + const FSPM_ARCH_UPD *new) { /* Display the architectural parameters for MemoryInit */ printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n",

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New patch to review for coreboot: soc/intel/quark: Fix FSP 2.0 build
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16808 -gerrit commit 0b9dbacbc41bcdf9acad2ebe1341ac6bec31987b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 17:16:44 2016 -0700 soc/intel/quark: Fix FSP 2.0 build Fix the build issues with FSP 2.0: * Remove struct from the various data structures. * Properly display the serial port UPDs. * Change chipset_handle_reset parameter type BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug off) and run on Galileo Gen2 Change-Id: Icae578855006f18e7e5aa18d2fd196d300d0c658 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/soc/intel/quark/fsp2_0.c | 2 +- src/soc/intel/quark/reset.c | 2 +- src/soc/intel/quark/romstage/debug.c | 20 +++++++++++++------- src/soc/intel/quark/romstage/fsp2_0.c | 6 +++--- 4 files changed, 18 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c index deb9334..2487cde 100644 --- a/src/soc/intel/quark/fsp2_0.c +++ b/src/soc/intel/quark/fsp2_0.c @@ -16,7 +16,7 @@ #include <fsp/util.h> #include <soc/ramstage.h> -void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { } diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c index e3d3fac..b5b86f3 100644 --- a/src/soc/intel/quark/reset.c +++ b/src/soc/intel/quark/reset.c @@ -17,7 +17,7 @@ #include <fsp/util.h> #include <reset.h> -void chipset_handle_reset(enum fsp_status status) +void chipset_handle_reset(uint32_t status) { /* Do a hard reset if Quark FSP ever requests a reset */ printk(BIOS_ERR, "Unknown reset type %x\n", status); diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c index c08150e..1029ead 100644 --- a/src/soc/intel/quark/romstage/debug.c +++ b/src/soc/intel/quark/romstage/debug.c @@ -16,11 +16,11 @@ #include <console/console.h> #include <fsp/util.h> -void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, - const struct FSPM_UPD *fspm_new_upd) +void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) { - const struct FSP_M_CONFIG *new; - const struct FSP_M_CONFIG *old; + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; old = &fspm_old_upd->FspmConfig; new = &fspm_new_upd->FspmConfig; @@ -62,9 +62,15 @@ void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, old->RmuBaseAddress, new->RmuBaseAddress); fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), old->RmuLength, new->RmuLength); - fsp_display_upd_value("SerialPortBaseAddress", - sizeof(old->SerialPortBaseAddress), - old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SerialPortPollForChar", + sizeof(old->SerialPortPollForChar), + old->SerialPortPollForChar, new->SerialPortPollForChar); + fsp_display_upd_value("SerialPortReadChar", + sizeof(old->SerialPortReadChar), + old->SerialPortReadChar, new->SerialPortReadChar); + fsp_display_upd_value("SerialPortWriteChar", + sizeof(old->SerialPortWriteChar), + old->SerialPortWriteChar, new->SerialPortWriteChar); fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), old->SmmTsegSize, new->SmmTsegSize); fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 51fcde7..d90bd38 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -87,14 +87,14 @@ int fill_power_state(void) return ps->prev_sleep_state; } -void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd) { - struct FSPM_ARCH_UPD *aupd; + FSPM_ARCH_UPD *aupd; const struct device *dev; const struct soc_intel_quark_config *config; char *rmu_file; size_t rmu_file_len; - struct FSP_M_CONFIG *upd; + FSP_M_CONFIG *upd; /* Clear SMI and wake events */ clear_smi_and_wake_events();

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New patch to review for coreboot: soc/intel/quark: Support multiple version of FSP
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16807 -gerrit commit 509d7f26ccbf91cb67b995eca1326eccaddbc879 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 18:03:13 2016 -0700 soc/intel/quark: Support multiple version of FSP Add support for multiple versions of FSP. BRANCH=none BUG=None TEST=Build FSP 1.1 (SEC/PEI core, with all FSP debug off) and run on Galileo Gen2 Change-Id: Ie7e7f0f883c4d3bfcb18fa25571e505cdde00b2d Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 3950d43..33b3cf8 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -178,7 +178,7 @@ config ADD_FSP_RAW_BIN config FSP_FILE string "Intel FSP binary path and filename" - default "3rdparty/blobs/soc/intel/quark/fsp.bin" + default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP.fd" depends on PLATFORM_USES_FSP1_1 depends on ADD_FSP_RAW_BIN help @@ -218,12 +218,12 @@ config RELOCATE_FSP_INTO_DRAM config FSP_M_FILE string depends on PLATFORM_USES_FSP2_0 - default "3rdparty/blobs/soc/intel/quark/FSP_M.fd" + default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd" config FSP_S_FILE string depends on PLATFORM_USES_FSP2_0 - default "3rdparty/blobs/soc/intel/quark/FSP_S.fd" + default "3rdparty/blobs/soc/intel/quark/$(CONFIG_FSP_TYPE)/$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd" ##### # RMU binary

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New patch to review for coreboot: mainboard/intel/quark: Add FSP selection values
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16806 -gerrit commit d27c5185b6465a16e7f04377bb2649b2e0a46653 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 14:10:06 2016 -0700 mainboard/intel/quark: Add FSP selection values Add Kconfig values to select the FSP setup: * FSP version: 1.1 or 2.0 * Implementation: Subroutine or SEC/PEI core based * Build type: DEBUG or RELEASE * Enable all debugging for FSP * Remove USE_FSP1_1 and USE_FSP2_0 Look for include files in vendorcode/intel/fsp/fsp???/quark BRANCH=none BUG=None TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2 Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 108 ++++++++++- src/mainboard/intel/galileo/Makefile.inc | 4 +- src/soc/intel/quark/include/soc/fsp/FspEas.h | 42 ----- src/soc/intel/quark/include/soc/fsp/FspUpd.h | 44 ----- src/soc/intel/quark/include/soc/fsp/FspmUpd.h | 235 ----------------------- src/soc/intel/quark/include/soc/fsp/FspsUpd.h | 52 ------ src/soc/intel/quark/include/soc/fsp/FsptUpd.h | 89 --------- src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h | 48 +++++ src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h | 239 ++++++++++++++++++++++++ src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h | 56 ++++++ src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h | 93 +++++++++ 11 files changed, 537 insertions(+), 473 deletions(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 2acc439..0c1fe5b 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,11 +18,10 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - select CREATE_BOARD_CHECKLIST +# select CREATE_BOARD_CHECKLIST select ENABLE_BUILTIN_HSUART1 select HAVE_ACPI_TABLES select SOC_INTEL_QUARK - select USE_FSP1_1 config MAINBOARD_DIR string @@ -45,16 +44,107 @@ config GALILEO_GEN2 runtime. Select which generation of the Galileo that coreboot should initialize. -config USE_FSP1_1 - bool - default n +choice + prompt "FSP version" + default FSP_VERSION_1_1 + +config FSP_VERSION_1_1 + bool "FSP 1.1" + select CREATE_BOARD_CHECKLIST select PLATFORM_USES_FSP1_1 # select ADD_FSP_RAW_BIN - -config USE_FSP2_0 - bool - default n + help + Use FSP 1_1 binary +config FSP_VERSION_2_0 + bool "FSP 2.0" select PLATFORM_USES_FSP2_0 select POSTCAR_STAGE + help + Use FSP 2.0 binary + +endchoice + +config FSP_VERSION + string + default "fsp1_1" if FSP_VERSION_1_1 + default "fsp2_0" if FSP_VERSION_2_0 + +choice + prompt "FSP binary type" + default FSP_BUILD_TYPE_DEBUG + +config FSP_BUILD_TYPE_DEBUG + bool "Debug" + help + Use the debug version of FSP +config FSP_BUILD_TYPE_RELEASE + bool "Release" + help + Use the release version of FSP + +endchoice + +config FSP_BUILD_TYPE + string + default "DEBUG" if FSP_BUILD_TYPE_DEBUG + default "RELEASE" if FSP_BUILD_TYPE_RELEASE + +choice + prompt "FSP type" + depends on FSP_VERSION_2_0 || FSP_VERSION_1_1 + default FSP_TYPE_1_1_PEI if FSP_VERSION_1_1 + default FSP_TYPE_2_0_PEI if FSP_VERSION_2_0 + +config FSP_TYPE_1_1 + bool "MemInit subroutine" + depends on FSP_VERSION_1_1 + help + FSP 1.1 implemented as subroutines, no EDK-II cores +config FSP_TYPE_1_1_PEI + bool "SEC + PEI Core + MemInit PEIM" + depends on FSP_VERSION_1_1 + help + FSP 1.1 implemented using SEC and PEI core +config FSP_TYPE_2_0 + bool "MemInit subroutine" + depends on FSP_VERSION_2_0 + help + FSP 2.0 implemented as subroutines, no EDK-II cores +config FSP_TYPE_2_0_PEI + bool "SEC + PEI Core + MemInit PEIM" + depends on FSP_VERSION_2_0 + help + FSP 2.0 implemented using SEC and PEI core + +endchoice + +config FSP_TYPE + string + default "Fsp1_1" if FSP_TYPE_1_1 + default "Fsp1_1Pei" if FSP_TYPE_1_1_PEI + default "Fsp2_0" if FSP_TYPE_2_0 + default "Fsp2_0Pei" if FSP_TYPE_2_0_PEI + +config FSP_DEBUG_ALL + bool "Enable all FSP debug support" + depends on FSP_VERSION_2_0 || FSP_VERSION_1_1 + default y +# Enable display and verification for coreboot build tests + select BOOTBLOCK_CONSOLE + select DISPLAY_HOBS + select DISPLAY_MTRRS + select DISPLAY_SMM_MEMORY_MAP + select DISPLAY_UPD_DATA + select DISPLAY_ESRAM_LAYOUT if FSP_VERSION_2_0 + select DISPLAY_FSP_CALLS_AND_STATUS if FSP_VERSION_2_0 + select DISPLAY_FSP_HEADER if FSP_VERSION_2_0 + select POSTCAR_CONSOLE if FSP_VERSION_2_0 + select VERIFY_HOBS if FSP_VERSION_2_0 + select DISPLAY_FSP_ENTRY_POINTS if FSP_VERSION_1_1 + help + Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA + also turn on FSP 2.0 debug support for ESRAM_LAYOUT, + FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS + or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS endif # BOARD_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index efaf007..16b2b4a 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -13,8 +13,8 @@ ## GNU General Public License for more details. ## -ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark +ifeq ($(CONFIG_PLATFORM_USES_FSP2_0)$(CONFIG_PLATFORM_USES_FSP1_1),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/$(CONFIG_FSP_VERSION)/quark endif bootblock-y += gpio.c diff --git a/src/soc/intel/quark/include/soc/fsp/FspEas.h b/src/soc/intel/quark/include/soc/fsp/FspEas.h deleted file mode 100644 index 48d956e..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FspEas.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPEAS_H__ -#define __FSPEAS_H__ - -#include <fsp/upd.h> -#include <soc/fsp/FspmUpd.h> -#include <soc/fsp/FspsUpd.h> -#include <soc/fsp/FsptUpd.h> -#include <fsp/api.h> - -#endif /* _FSPEAS_H_ */ diff --git a/src/soc/intel/quark/include/soc/fsp/FspUpd.h b/src/soc/intel/quark/include/soc/fsp/FspUpd.h deleted file mode 100644 index d3277d9..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FspUpd.h +++ /dev/null @@ -1,44 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ - -#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h deleted file mode 100644 index a7a54a8..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h +++ /dev/null @@ -1,235 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - - -/** Fsp M Configuration -**/ -struct FSP_M_CONFIG { - -/** Offset 0x0040 - RmuBaseAddress - RMU microcode binary base address in SPI flash' -**/ - uint32_t RmuBaseAddress; - -/** Offset 0x0044 - RmuLength - RMU microcode binary length in bytes -**/ - uint32_t RmuLength; - -/** Offset 0x0048 - SerialPortBaseAddress - Debug serial port base address set by BIOS. Zero disables debug serial output. -**/ - uint32_t Reserved_48; - -/** Offset 0x004C - tRAS - ACT to PRE command period in picoseconds. -**/ - uint32_t tRAS; - -/** Offset 0x0050 - tWTR - Delay from start of internal write transaction to internal read command in picoseconds. -**/ - uint32_t tWTR; - -/** Offset 0x0054 - tRRD - ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. -**/ - uint32_t tRRD; - -/** Offset 0x0058 - tFAW - Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. -**/ - uint32_t tFAW; - -/** Offset 0x005C - Flags - Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN - BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" - topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices - on writes. -**/ - uint32_t Flags; - -/** Offset 0x0060 - DramWidth - 0=x8, 1=x16, others=RESERVED. -**/ - uint8_t DramWidth; - -/** Offset 0x0061 - DramSpeed - 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. -**/ - uint8_t DramSpeed; - -/** Offset 0x0062 - DramType - 0=DDR3, 1=DDR3L, others=RESERVED. -**/ - uint8_t DramType; - -/** Offset 0x0063 - RankMask - bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. -**/ - uint8_t RankMask; - -/** Offset 0x0064 - ChanMask - bit[0] CHAN0_EN, others=RESERVED. -**/ - uint8_t ChanMask; - -/** Offset 0x0065 - ChanWidth - 1=x16, others=RESERVED. -**/ - uint8_t ChanWidth; - -/** Offset 0x0066 - AddrMode - 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. -**/ - uint8_t AddrMode; - -/** Offset 0x0067 - SrInt - 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. -**/ - uint8_t SrInt; - -/** Offset 0x0068 - SrTemp - 0=normal, 1=extended, others=RESERVED. -**/ - uint8_t SrTemp; - -/** Offset 0x0069 - DramRonVal - 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. -**/ - uint8_t DramRonVal; - -/** Offset 0x006A - DramRttNomVal - 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. -**/ - uint8_t DramRttNomVal; - -/** Offset 0x006B - DramRttWrVal - 0=off others=RESERVED. -**/ - uint8_t DramRttWrVal; - -/** Offset 0x006C - SocRdOdtVal - 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. -**/ - uint8_t SocRdOdtVal; - -/** Offset 0x006D - SocWrRonVal - 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. -**/ - uint8_t SocWrRonVal; - -/** Offset 0x006E - SocWrSlewRate - 0=2.5V/ns, 1=4V/ns, others=RESERVED. -**/ - uint8_t SocWrSlewRate; - -/** Offset 0x006F - DramDensity - 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. -**/ - uint8_t DramDensity; - -/** Offset 0x0070 - tCL - DRAM CAS Latency in clocks -**/ - uint8_t tCL; - -/** Offset 0x0071 - EccScrubInterval - ECC scrub interval in miliseconds 1..255 (0 works as feature disable -**/ - uint8_t EccScrubInterval; - -/** Offset 0x0072 - EccScrubBlkSize - Number of 32B blocks read for ECC scrub 2..16 -**/ - uint8_t EccScrubBlkSize; - -/** Offset 0x0073 - SmmTsegSize - Size of the SMM region in 1 MiB chunks -**/ - uint8_t SmmTsegSize; - -/** Offset 0x0074 - FspReservedMemoryLength - FSP reserved memory length in bytes -**/ - uint32_t FspReservedMemoryLength; - -/** Offset 0x0078 - MrcDataPtr - Pointer to saved MRC data -**/ - uint32_t MrcDataPtr; - -/** Offset 0x007C - MrcDataLength - Length of saved MRC data -**/ - uint32_t MrcDataLength; - -/** Offset 0x0080 -**/ - uint32_t SerialPortPollForChar; - -/** Offset 0x0084 -**/ - uint32_t SerialPortReadChar; - -/** Offset 0x0088 -**/ - uint32_t SerialPortWriteChar; - -/** Offset 0x008C -**/ - uint16_t UpdTerminator; -} __attribute__((packed)); - -/** Fsp M UPD Configuration -**/ -struct FSPM_UPD { - -/** Offset 0x0000 -**/ - struct FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - struct FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - struct FSP_M_CONFIG FspmConfig; -} __attribute__((packed)); - -#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspsUpd.h b/src/soc/intel/quark/include/soc/fsp/FspsUpd.h deleted file mode 100644 index 6b054e8..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FspsUpd.h +++ /dev/null @@ -1,52 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - - -/** Fsp S UPD Configuration -**/ -struct FSPS_UPD { - -/** Offset 0x0000 -**/ - struct FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - uint16_t UpdTerminator; -} __attribute__((packed)); - -#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FsptUpd.h b/src/soc/intel/quark/include/soc/fsp/FsptUpd.h deleted file mode 100644 index 8b1ded7..0000000 --- a/src/soc/intel/quark/include/soc/fsp/FsptUpd.h +++ /dev/null @@ -1,89 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include <FspUpd.h> - - -/** Fsp T Common UPD -**/ -struct FSPT_COMMON_UPD { - -/** Offset 0x0020 -**/ - uint8_t Revision; - -/** Offset 0x0021 -**/ - uint8_t Reserved[3]; - -/** Offset 0x0024 -**/ - uint32_t MicrocodeRegionBase; - -/** Offset 0x0028 -**/ - uint32_t MicrocodeRegionLength; - -/** Offset 0x002C -**/ - uint32_t CodeRegionBase; - -/** Offset 0x0030 -**/ - uint32_t CodeRegionLength; - -/** Offset 0x0034 -**/ - uint8_t Reserved1[12]; -} __attribute__((packed)); - -/** Fsp T UPD Configuration -**/ -struct FSPT_UPD { - -/** Offset 0x0000 -**/ - struct FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - struct FSPT_COMMON_UPD FsptCommonUpd; - -/** Offset 0x0040 -**/ - uint16_t UpdTerminator; -} __attribute__((packed)); - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h new file mode 100644 index 0000000..cfd1ac0 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(push, 1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h new file mode 100644 index 0000000..28e4d21 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h @@ -0,0 +1,239 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - RmuBaseAddress + RMU microcode binary base address in SPI flash' +**/ + UINT32 RmuBaseAddress; + +/** Offset 0x0044 - RmuLength + RMU microcode binary length in bytes +**/ + UINT32 RmuLength; + +/** Offset 0x0048 - SerialPortBaseAddress + Debug serial port base address set by BIOS. Zero disables debug serial output. +**/ + UINT32 Reserved_48; + +/** Offset 0x004C - tRAS + ACT to PRE command period in picoseconds. +**/ + UINT32 tRAS; + +/** Offset 0x0050 - tWTR + Delay from start of internal write transaction to internal read command in picoseconds. +**/ + UINT32 tWTR; + +/** Offset 0x0054 - tRRD + ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + UINT32 tRRD; + +/** Offset 0x0058 - tFAW + Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + UINT32 tFAW; + +/** Offset 0x005C - Flags + Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN + BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" + topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices + on writes. +**/ + UINT32 Flags; + +/** Offset 0x0060 - DramWidth + 0=x8, 1=x16, others=RESERVED. +**/ + UINT8 DramWidth; + +/** Offset 0x0061 - DramSpeed + 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. +**/ + UINT8 DramSpeed; + +/** Offset 0x0062 - DramType + 0=DDR3, 1=DDR3L, others=RESERVED. +**/ + UINT8 DramType; + +/** Offset 0x0063 - RankMask + bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. +**/ + UINT8 RankMask; + +/** Offset 0x0064 - ChanMask + bit[0] CHAN0_EN, others=RESERVED. +**/ + UINT8 ChanMask; + +/** Offset 0x0065 - ChanWidth + 1=x16, others=RESERVED. +**/ + UINT8 ChanWidth; + +/** Offset 0x0066 - AddrMode + 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. +**/ + UINT8 AddrMode; + +/** Offset 0x0067 - SrInt + 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. +**/ + UINT8 SrInt; + +/** Offset 0x0068 - SrTemp + 0=normal, 1=extended, others=RESERVED. +**/ + UINT8 SrTemp; + +/** Offset 0x0069 - DramRonVal + 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. +**/ + UINT8 DramRonVal; + +/** Offset 0x006A - DramRttNomVal + 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. +**/ + UINT8 DramRttNomVal; + +/** Offset 0x006B - DramRttWrVal + 0=off others=RESERVED. +**/ + UINT8 DramRttWrVal; + +/** Offset 0x006C - SocRdOdtVal + 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. +**/ + UINT8 SocRdOdtVal; + +/** Offset 0x006D - SocWrRonVal + 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. +**/ + UINT8 SocWrRonVal; + +/** Offset 0x006E - SocWrSlewRate + 0=2.5V/ns, 1=4V/ns, others=RESERVED. +**/ + UINT8 SocWrSlewRate; + +/** Offset 0x006F - DramDensity + 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. +**/ + UINT8 DramDensity; + +/** Offset 0x0070 - tCL + DRAM CAS Latency in clocks +**/ + UINT8 tCL; + +/** Offset 0x0071 - EccScrubInterval + ECC scrub interval in miliseconds 1..255 (0 works as feature disable +**/ + UINT8 EccScrubInterval; + +/** Offset 0x0072 - EccScrubBlkSize + Number of 32B blocks read for ECC scrub 2..16 +**/ + UINT8 EccScrubBlkSize; + +/** Offset 0x0073 - SmmTsegSize + Size of the SMM region in 1 MiB chunks +**/ + UINT8 SmmTsegSize; + +/** Offset 0x0074 - FspReservedMemoryLength + FSP reserved memory length in bytes +**/ + UINT32 FspReservedMemoryLength; + +/** Offset 0x0078 - MrcDataPtr + Pointer to saved MRC data +**/ + UINT32 MrcDataPtr; + +/** Offset 0x007C - MrcDataLength + Length of saved MRC data +**/ + UINT32 MrcDataLength; + +/** Offset 0x0080 +**/ + UINT32 SerialPortPollForChar; + +/** Offset 0x0084 +**/ + UINT32 SerialPortReadChar; + +/** Offset 0x0088 +**/ + UINT32 SerialPortWriteChar; + +/** Offset 0x008C +**/ + UINT16 UpdTerminator; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; +} FSPM_UPD; + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h new file mode 100644 index 0000000..a613000 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h @@ -0,0 +1,56 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h new file mode 100644 index 0000000..02a1e09 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h @@ -0,0 +1,93 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp T Common UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT8 Revision; + +/** Offset 0x0021 +**/ + UINT8 Reserved[3]; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0028 +**/ + UINT32 MicrocodeRegionLength; + +/** Offset 0x002C +**/ + UINT32 CodeRegionBase; + +/** Offset 0x0030 +**/ + UINT32 CodeRegionLength; + +/** Offset 0x0034 +**/ + UINT8 Reserved1[12]; +} FSPT_COMMON_UPD; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_COMMON_UPD FsptCommonUpd; + +/** Offset 0x0040 +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack(pop) + +#endif

1 0

New patch to review for coreboot: clear tpm when required
by Vadim Bendebury 29 Sep '16

29 Sep '16

Vadim Bendebury (vbendeb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16805 -gerrit commit 55ed04c5ca382414d7bbebc6e2ab5ea8ef9440be Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Sep 28 18:59:39 2016 -0700 clear tpm when required Function which invoked when TPM clear is requested was left empty, this patch fixes it. BRANCH=gru BUG=chrome-os-partner:57411 TEST=verified on a chromeos device that tpm is in fact cleared when CLEAR_TPM_OWNER_REQUEST is set by userland. Change-Id: I4370792afd512309ecf7f4961ed4d44a04a3e2aa Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/vboot/secdata_tpm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vboot/secdata_tpm.c b/src/vboot/secdata_tpm.c index a51e5d6..76b90ab 100644 --- a/src/vboot/secdata_tpm.c +++ b/src/vboot/secdata_tpm.c @@ -154,6 +154,7 @@ static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) uint32_t tpm_clear_and_reenable(void) { VBDEBUG("TPM: Clear and re-enable\n"); + RETURN_ON_FAILURE(tlcl_force_clear()); return TPM_SUCCESS; }

1 0

Patch merged into coreboot/master: cbfstool: set init_size for linux payloads.
by gerrit＠coreboot.org 28 Sep '16

28 Sep '16

the following patch was just integrated into master: commit fa74e4705dbb5ecf5ba466fd6a9bc309f7e3e8bf Author: Ronald G. Minnich <rminnich(a)google.com> Date: Wed Sep 28 10:43:12 2016 -0700 cbfstool: set init_size for linux payloads. We were not setting the init_size for linux payloads. A proper value of init_size is required if the kernel is x86_64. This is tested in qemu and fixes the observed problem that 974f221c84b05b1dc2f5ea50dc16d2a9d1e95eda and later would not boot, and would in fact fail in head_64.S. Change-Id: I254c13d16b1e014a6f1d4fd7c39b1cfe005cd9b0 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://review.coreboot.org/16781 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16781 for details. -gerrit

1 0

Patch set updated for coreboot: cbfstool: set init_size for linux payloads.
by Ronald G. Minnich 28 Sep '16

28 Sep '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16781 -gerrit commit afd117d460509cf5776973054374b23ff2d35bdb Author: Ronald G. Minnich <rminnich(a)google.com> Date: Wed Sep 28 10:43:12 2016 -0700 cbfstool: set init_size for linux payloads. We were not setting the init_size for linux payloads. A proper value of init_size is required if the kernel is x86_64. This is tested in qemu and fixes the observed problem that 974f221c84b05b1dc2f5ea50dc16d2a9d1e95eda and later would not boot, and would in fact fail in head_64.S. Change-Id: I254c13d16b1e014a6f1d4fd7c39b1cfe005cd9b0 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> --- util/cbfstool/cbfs-payload-linux.c | 9 +++++++++ util/cbfstool/linux.h | 12 ++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c index 03a41cd..afb0f3a 100644 --- a/util/cbfstool/cbfs-payload-linux.c +++ b/util/cbfstool/cbfs-payload-linux.c @@ -220,14 +220,19 @@ int parse_bzImage_to_payload(const struct buffer *input, if (hdr->setup_sects != 0) { setup_size = (hdr->setup_sects + 1) * 512; + } else { + WARN("hdr->setup_sects is 0, which could cause boot problems.\n"); } /* Setup parameter block. Imitate FILO. */ struct linux_params params; memset(&params, 0, sizeof(struct linux_params)); + params.mount_root_rdonly = hdr->root_flags; params.orig_root_dev = hdr->root_dev; + params.init_size = hdr->init_size; + /* Sensible video defaults. Might be overridden on runtime by coreboot tables. */ params.orig_video_mode = 3; params.orig_video_cols = 80; @@ -262,6 +267,10 @@ int parse_bzImage_to_payload(const struct buffer *input, * so if possible (relocatable kernel) use that to * avoid a trampoline copy. */ kernel_base = ALIGN(16*1024*1024, params.kernel_alignment); + if (hdr->init_size == 0) { + ERROR("init_size 0 for relocatable kernel\n"); + return -1; + } } } diff --git a/util/cbfstool/linux.h b/util/cbfstool/linux.h index b96f447..2fd2d4d 100644 --- a/util/cbfstool/linux.h +++ b/util/cbfstool/linux.h @@ -139,7 +139,13 @@ struct linux_params { u32 alt_mem_k; /* 0x1e0 */ u8 reserved5[4]; /* 0x1e4 */ u8 e820_map_nr; /* 0x1e8 */ - u8 reserved6[9]; /* 0x1e9 */ + u8 reserved6[8]; /* 0x1e9 */ + /* This next variable is to show where + * in this struct the Linux setup_hdr + * is located. It does not get filled in. + * We may someday find it useful to use + * its address. */ + u8 setup_hdr; /* 0x1f1 */ u16 mount_root_rdonly; /* 0x1f2 */ u8 reserved7[4]; /* 0x1f4 */ u16 ramdisk_flags; /* 0x1f8 */ @@ -170,7 +176,9 @@ struct linux_params { u32 initrd_addr_max; /* 0x22c */ u32 kernel_alignment; /* 0x230 */ u8 relocatable_kernel; /* 0x234 */ - u8 reserved13[155]; /* 0x22c */ + u8 reserved13[0x2b]; /* 0x235 */ + u32 init_size; /* 0x260 */ + u8 reserved14[0x6c]; /* 0x264 */ struct e820entry e820_map[E820MAX]; /* 0x2d0 */ u8 reserved16[688]; /* 0x550 */ #define COMMAND_LINE_SIZE 256

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New patch to review for coreboot: soc/intel/fsp_broadwell_de/uart: Drop it
by Nico Huber 28 Sep '16

28 Sep '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16786 -gerrit commit 90978613fd8b6ea8e25d29566c7c1ecccf5ac6fd Author: Nico Huber <nico.h(a)gmx.de> Date: Wed Sep 28 22:15:07 2016 +0200 soc/intel/fsp_broadwell_de/uart: Drop it A copy of our uart8250io driver sneaked in with Broadwell-DE support. The only difference is the lack of initialization (due to FSP handling that). TEST=manually compared resulting object files Change-Id: I09be10b76c76c1306ad2c8db8fb07794dde1b0f2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/drivers/uart/Kconfig | 5 ++ src/drivers/uart/uart8250io.c | 10 ++- src/soc/intel/fsp_broadwell_de/Kconfig | 10 +-- src/soc/intel/fsp_broadwell_de/Makefile.inc | 6 -- src/soc/intel/fsp_broadwell_de/uart.c | 112 ---------------------------- 5 files changed, 13 insertions(+), 130 deletions(-) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 4faa48d..62d3cc4 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -9,6 +9,11 @@ config DRIVERS_UART_8250IO default n if NO_UART_ON_SUPERIO default y if ARCH_X86 +config DRIVERS_UART_8250IO_SKIP_INIT + bool + depends on DRIVERS_UART_8250IO + default n + # Select this for mainboard without SuperIO serial port. config NO_UART_ON_SUPERIO def_bool n diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 89c4476..5b56c84 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -104,10 +104,12 @@ uintptr_t uart_platform_base(int idx) void uart_init(int idx) { - unsigned int div; - div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), - uart_input_clock_divider()); - uart8250_init(uart_platform_base(idx), div); + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250IO_SKIP_INIT)) { + unsigned int div; + div = uart_baudrate_divisor(default_baudrate(), + uart_platform_refclk(), uart_input_clock_divider()); + uart8250_init(uart_platform_base(idx), div); + } } void uart_tx_byte(int idx, unsigned char data) diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 99a2bfd..bedf291 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -61,18 +61,12 @@ config VGA_BIOS config INTEGRATED_UART bool "Integrated UART ports" default y - select HAVE_UART_SPECIAL + select DRIVERS_UART_8250IO + select DRIVERS_UART_8250IO_SKIP_INIT select CONSOLE_SERIAL help Use Broadwell-DE Integrated UART ports @3F8h and 2F8h. -config DRIVERS_UART_8250IO - bool "Serial port on SuperIO (Broadwell-DE's UART ports unselected)" - depends on !INTEGRATED_UART - help - Select to choose SuperIO's serial port for console output. - CANNOT select if intend to use SoC integrated serial ports. - config CONSOLE_CBMEM bool "Send console output to a CBMEM buffer" default n diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 41ae43e..657f70c 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -24,12 +24,6 @@ ramstage-y += acpi.c ramstage-y += smbus_common.c ramstage-y += smbus.c -ifeq ($(CONFIG_INTEGRATED_UART),y) -romstage-y += uart.c -ramstage-y += uart.c -smm-$(CONFIG_DEBUG_SMI) += uart.c -endif - CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/ diff --git a/src/soc/intel/fsp_broadwell_de/uart.c b/src/soc/intel/fsp_broadwell_de/uart.c deleted file mode 100644 index d22dd0d..0000000 --- a/src/soc/intel/fsp_broadwell_de/uart.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * Copyright (C) 2015-2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <rules.h> -#include <stdlib.h> -#include <arch/io.h> -#include <console/uart.h> -#include <trace.h> -#include <drivers/uart/uart8250reg.h> - -#ifndef __ROMCC__ -#include <boot/coreboot_tables.h> -#endif - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - * - * Estimated that inb() from UART takes 1 microsecond. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static int uart8250_can_tx_byte(unsigned base_port) -{ - return inb(base_port + UART8250_LSR) & UART8250_LSR_THRE; -} - -static void uart8250_tx_byte(unsigned base_port, unsigned char data) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_tx_byte(base_port)); - outb(data, base_port + UART8250_TBR); -} - -static void uart8250_tx_flush(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while (i-- && !(inb(base_port + UART8250_LSR) & UART8250_LSR_TEMT)); -} - -static int uart8250_can_rx_byte(unsigned base_port) -{ - return inb(base_port + UART8250_LSR) & UART8250_LSR_DR; -} - -static unsigned char uart8250_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_rx_byte(base_port)); - - if (i) - return inb(base_port + UART8250_RBR); - else - return 0x0; -} - -static const unsigned bases[] = { 0x3f8, 0x2f8 }; - -uintptr_t uart_platform_base(int idx) -{ - if (idx < ARRAY_SIZE(bases)) - return bases[idx]; - return 0; -} - -void uart_init(int idx) -{ - // No needed to configure as setting has been done in BDX-DE FSP -} - -void uart_tx_byte(int idx, unsigned char data) -{ - uart8250_tx_byte(uart_platform_base(idx), data); -} - -unsigned char uart_rx_byte(int idx) -{ - return uart8250_rx_byte(uart_platform_base(idx)); -} - -void uart_tx_flush(int idx) -{ - uart8250_tx_flush(uart_platform_base(idx)); -} - -#if ENV_RAMSTAGE -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_IO_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = default_baudrate(); - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); -} -#endif

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Patch merged into coreboot/master: google/reef: Mark touchpad and touchscreen as probed devices
by gerrit＠coreboot.org 28 Sep '16

28 Sep '16

the following patch was just integrated into master: commit 6d16e1ff87f31ff558cea76741f5675763d4ab44 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 26 10:33:51 2016 -0700 google/reef: Mark touchpad and touchscreen as probed devices Add the 'probed' flag to the touchpad and touchscreen devices so they are probed by the kernel before being loaded, in case they do not exist or are replaced with another vendor. BUG=chrome-os-partner:57686 Change-Id: I0a61964e6874cd99fab0c21fa404a43548fc8ab5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/16743 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16743 for details. -gerrit

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Patch merged into coreboot/master: drivers/i2c/generic: Add config for marking device as probed
by gerrit＠coreboot.org 28 Sep '16

28 Sep '16

the following patch was just integrated into master: commit fbf2c79b489a526e5ab7359ce56be0b4b66c854b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 26 10:31:22 2016 -0700 drivers/i2c/generic: Add config for marking device as probed Add a config option to the generic I2C device driver to indicate to the OS that this device should be probed before being added. This can be used to provide ACPI device instantiations to devices that may not actually exist on the board. For example, if multiple trackpad vendors are supported on the same board they can both be described in ACPI and the OS will probe the address and load the driver only if the device responds to the probe at that address. BUG=chrome-os-partner:57686 Change-Id: I22cffb4b15f25d97dfd37dc58bca315f57bafc59 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/16742 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16742 for details. -gerrit

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coreboot-gerrit September 2016