coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: soc/intel/apollolake: Add pmc_ipc device support
by gerrit＠coreboot.org 28 Sep '16

28 Sep '16

the following patch was just integrated into master: commit 28821dbb2261267462a7e9b0cc1c23b51af2d3ee Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:48:19 2016 -0700 soc/intel/apollolake: Add pmc_ipc device support A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/16649 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16649 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Use fixed resource for SRAM and IPC1
by gerrit＠coreboot.org 28 Sep '16

28 Sep '16

the following patch was just integrated into master: commit 9108680c1c17ec539bbba9525b6d9d62e57d296a Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:15:29 2016 -0700 soc/intel/apollolake: Use fixed resource for SRAM and IPC1 Intel telemetry support will require PMC IPC1 and SRAM devices to be operated in ACPI mode. Then using fixed resources on BAR0, BAR1 and BAR2 (PMC only) for those two devices will help the resource assignment in DSDT stage. BUG=chrome-os-partner:57364 BRANCH=None TEST=Boot up into Chrome OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/16648 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16648 for details. -gerrit

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New patch to review for coreboot: mainboard/asus/kfsn4-dre_k8/romstage.c: Use tabs for indents
by HAOUAS Elyes 28 Sep '16

28 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16785 -gerrit commit e0876f842ea0b9a39e60fc87d196ffc1398b3e42 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 28 21:41:06 2016 +0200 mainboard/asus/kfsn4-dre_k8/romstage.c: Use tabs for indents Change-Id: If6b36ebef49dd2733d272f990bb7c6623d4ab1b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/asus/kfsn4-dre_k8/romstage.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index b547461..03a095d 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -299,11 +299,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "ck804_early_setup_x()\n"); needs_reset |= ck804_early_setup_x(); - /* FIDVID change will issue one LDTSTOP and the HT change will be effective too */ - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } + /* FIDVID change will issue one LDTSTOP and the HT change will be effective too */ + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } post_code(0x3b); @@ -323,8 +323,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block */ if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { - dump_spd_registers(&cpu[0]); - dump_smbus_registers(); + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); } #endif @@ -348,8 +348,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Initialize GPIO */ /* Access SuperIO GPI03 logical device */ uint16_t port = GPIO3_DEV >> 8; - outb(0x87, port); - outb(0x87, port); + outb(0x87, port); + outb(0x87, port); pnp_set_logical_device(GPIO3_DEV); /* Set GP37 (power LED) to output */ pnp_write_config(GPIO3_DEV, 0xf0, 0x7f);

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Patch set updated for coreboot: mainboard/via/epia-m850/romstage.c: Remove unnecessary whitespace
by HAOUAS Elyes 28 Sep '16

28 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16784 -gerrit commit 445c35bf71d98e130bc8753ddcdcca15db64cca3 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 28 21:24:40 2016 +0200 mainboard/via/epia-m850/romstage.c: Remove unnecessary whitespace Change-Id: Ic5359f794c64a9a67ec9e059af337a65073baff4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/via/epia-m850/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index f3f0ec6..450f7d7 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by

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New patch to review for coreboot: mainboard/via/epia-m850/romstage.c: Correct indent
by HAOUAS Elyes 28 Sep '16

28 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16784 -gerrit commit 002ac28e91d33ea0d692a1e60eff5af62235bb1b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 28 21:24:40 2016 +0200 mainboard/via/epia-m850/romstage.c: Correct indent Change-Id: Ic5359f794c64a9a67ec9e059af337a65073baff4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/via/epia-m850/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index f3f0ec6..450f7d7 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by

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New patch to review for coreboot: mainboard/lanner/em8510: Use tabs for indents
by HAOUAS Elyes 28 Sep '16

28 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16783 -gerrit commit 2ca4ffc366e890739a53a346cade0380b65d55f9 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 28 21:10:08 2016 +0200 mainboard/lanner/em8510: Use tabs for indents Change-Id: Ib6191c590144438d7d9d6772d792a83e92d5516a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lanner/em8510/devicetree.cb | 50 +++++++++++++++---------------- src/mainboard/lanner/em8510/romstage.c | 2 +- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/mainboard/lanner/em8510/devicetree.cb b/src/mainboard/lanner/em8510/devicetree.cb index 257d894..0a91cc9 100644 --- a/src/mainboard/lanner/em8510/devicetree.cb +++ b/src/mainboard/lanner/em8510/devicetree.cb @@ -14,38 +14,38 @@ chip northbridge/intel/i855 register "enable_native_ide" = "0" device pci 1f.0 on chip superio/winbond/w83627thg # link 1 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 end end - end + end end end device cpu_cluster 0 on diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 2e5a125..126d942 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -63,7 +63,7 @@ void mainboard_romstage_entry(unsigned long bist) #endif if (!bios_reset_detected()) { - enable_smbus(); + enable_smbus(); #if 1 dump_spd_registers(); dump_smbus_registers();

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New patch to review for coreboot: mainboard/iwill/dk8_htx: Use tabs for indents
by HAOUAS Elyes 28 Sep '16

28 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16782 -gerrit commit 27f58ec4c822307b798193a380c2171fd0c46fc2 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 28 19:56:00 2016 +0200 mainboard/iwill/dk8_htx: Use tabs for indents Change-Id: I303270a45171dda88b7661e3797fd3724e3b055f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/iwill/dk8_htx/acpi_tables.c | 176 +++++++++++++++--------------- src/mainboard/iwill/dk8_htx/mb_sysconf.h | 18 +-- src/mainboard/iwill/dk8_htx/romstage.c | 60 +++++----- 3 files changed, 127 insertions(+), 127 deletions(-) diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index 5b2b2b0..b9e8468 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -26,11 +26,11 @@ unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base = 0x18; - struct mb_sysconf_t *m; + struct mb_sysconf_t *m; get_bus_conf(); - m = sysconf.mb; + m = sysconf.mb; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); @@ -39,75 +39,75 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, IO_APIC_ADDR, 0); - /* Write all 8131 IOAPICs */ - { - device_t dev; - struct resource *res; - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, - res->base, gsi_base ); + /* Write all 8131 IOAPICs */ + { + device_t dev; + struct resource *res; + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, + res->base, gsi_base ); gsi_base+=4; - } - } - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, - res->base, gsi_base ); - gsi_base+=4; - } - } - - int i; - int j = 0; - - for(i = 1; i< sysconf.hc_possible_num; i++) { + } + } + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, + res->base, gsi_base ); + gsi_base+=4; + } + } + + int i; + int j = 0; + + for(i = 1; i< sysconf.hc_possible_num; i++) { unsigned d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 + if(!(sysconf.pci1234[i] & 0x1) ) continue; + // 8131 need to use +4 - switch (sysconf.hcid[i]) { - case 1: + switch (sysconf.hcid[i]) { + case 1: d = 7; break; case 3: d = 4; break; } - switch (sysconf.hcid[i]) { - case 1: + switch (sysconf.hcid[i]) { + case 1: case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base ); - gsi_base+=d; - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base ); - gsi_base+=d; - - } - } - break; - } - - j++; - } - - } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], + res->base, gsi_base ); + gsi_base+=d; + } + } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], + res->base, gsi_base ); + gsi_base+=d; + + } + } + break; + } + + j++; + } + + } current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 ); @@ -117,8 +117,8 @@ unsigned long acpi_fill_madt(unsigned long current) /* 5 mean: 0101 --> Edge-triggered, Active high*/ - /* create all subtables for processors */ - current = acpi_create_madt_lapic_nmis(current, 5, 1); + /* create all subtables for processors */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); /* 1: LINT1 connect to NMI */ @@ -142,36 +142,36 @@ unsigned long mainboard_write_acpi_tables(device_t device, start = ALIGN(start, 16); current = start; - //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table + //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table - for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink + for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink const char *file_name; - if((sysconf.pci1234[i] & 1) != 1 ) continue; - uint8_t c; - if(i < 7) { - c = (uint8_t) ('4' + i - 1); - } - else { - c = (uint8_t) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *)current; - switch(sysconf.hcid[i]) { - case 1: //8132 + if((sysconf.pci1234[i] & 1) != 1 ) continue; + uint8_t c; + if(i < 7) { + c = (uint8_t) ('4' + i - 1); + } + else { + c = (uint8_t) ('A' + i - 1 - 6); + } + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt + current = ALIGN(current, 8); + ssdtx = (acpi_header_t *)current; + switch(sysconf.hcid[i]) { + case 1: //8132 file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; - break; - case 2: //8151 + break; + case 2: //8151 file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; - break; + break; case 3: //8131 file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; - break; - default: + break; + default: //HTX no io apic file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; break; - } + } p = cbfs_boot_map_with_leak( file_name, CBFS_TYPE_RAW, &p_size); @@ -181,11 +181,11 @@ unsigned long mainboard_write_acpi_tables(device_t device, memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); - acpi_add_table(rsdp,ssdtx); - } + update_ssdtx((void *)ssdtx, i); + ssdtx->checksum = 0; + ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); + acpi_add_table(rsdp,ssdtx); + } return current; } diff --git a/src/mainboard/iwill/dk8_htx/mb_sysconf.h b/src/mainboard/iwill/dk8_htx/mb_sysconf.h index ef3dace..4933d48 100644 --- a/src/mainboard/iwill/dk8_htx/mb_sysconf.h +++ b/src/mainboard/iwill/dk8_htx/mb_sysconf.h @@ -9,18 +9,18 @@ struct mb_sysconf_t { unsigned char bus_8111_0; unsigned char bus_8111_1; - unsigned char bus_8132a[7][3]; + unsigned char bus_8132a[7][3]; - unsigned char bus_8151[7][2]; + unsigned char bus_8151[7][2]; - unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned apicid_8132a[7][2]; + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + unsigned apicid_8132a[7][2]; - unsigned sbdn3; - unsigned sbdn3a[7]; - unsigned sbdn5[7]; + unsigned sbdn3; + unsigned sbdn3a[7]; + unsigned sbdn5[7]; }; diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index fa0c11c..c1c141e 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -51,7 +51,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { } static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> @@ -77,10 +77,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0; - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - setup_mb_resource_map(); + setup_mb_resource_map(); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); @@ -99,47 +99,47 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } #endif needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); @@ -151,13 +151,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ - init_timer(); // Need to use TMICT to synchronize FID/VID + /* all ap stopped? */ + init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 - dump_pci_devices(); + dump_pci_devices(); #endif - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }

1 0

New patch to review for coreboot: cbfstool: set init_size for linux payloads.
by Ronald G. Minnich 28 Sep '16

28 Sep '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16781 -gerrit commit 055f7b168956f9717c263da977ecffecc030fa1b Author: Ronald G. Minnich <rminnich(a)google.com> Date: Wed Sep 28 10:43:12 2016 -0700 cbfstool: set init_size for linux payloads. We were not setting the init_size for linux payloads. A proper value of init_size is required if the kernel is x86_64. This is tested in qemu and fixes the observed problem that 974f221c84b05b1dc2f5ea50dc16d2a9d1e95eda and later would not boot, and would in fact fail in head_64.S. Change-Id: I254c13d16b1e014a6f1d4fd7c39b1cfe005cd9b0 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> --- util/cbfstool/cbfs-payload-linux.c | 7 +++++++ util/cbfstool/linux.h | 7 +++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c index 03a41cd..d58d3d7 100644 --- a/util/cbfstool/cbfs-payload-linux.c +++ b/util/cbfstool/cbfs-payload-linux.c @@ -220,14 +220,19 @@ int parse_bzImage_to_payload(const struct buffer *input, if (hdr->setup_sects != 0) { setup_size = (hdr->setup_sects + 1) * 512; + } else { + WARN("hdr->setup_sects is 0, which could cause boot problems.\n"); } /* Setup parameter block. Imitate FILO. */ struct linux_params params; memset(&params, 0, sizeof(struct linux_params)); + params.mount_root_rdonly = hdr->root_flags; params.orig_root_dev = hdr->root_dev; + params.init_size = hdr->init_size; + /* Sensible video defaults. Might be overridden on runtime by coreboot tables. */ params.orig_video_mode = 3; params.orig_video_cols = 80; @@ -262,6 +267,8 @@ int parse_bzImage_to_payload(const struct buffer *input, * so if possible (relocatable kernel) use that to * avoid a trampoline copy. */ kernel_base = ALIGN(16*1024*1024, params.kernel_alignment); + if (hdr->init_size == 0) + ERROR("init_size 0 for relocatable kernel\n"); } } diff --git a/util/cbfstool/linux.h b/util/cbfstool/linux.h index b96f447..d42737d 100644 --- a/util/cbfstool/linux.h +++ b/util/cbfstool/linux.h @@ -139,7 +139,8 @@ struct linux_params { u32 alt_mem_k; /* 0x1e0 */ u8 reserved5[4]; /* 0x1e4 */ u8 e820_map_nr; /* 0x1e8 */ - u8 reserved6[9]; /* 0x1e9 */ + u8 reserved6[8]; /* 0x1e9 */ + u8 setup_hdr; /* 0x1f1 Where Linux finds the setup header */ u16 mount_root_rdonly; /* 0x1f2 */ u8 reserved7[4]; /* 0x1f4 */ u16 ramdisk_flags; /* 0x1f8 */ @@ -170,7 +171,9 @@ struct linux_params { u32 initrd_addr_max; /* 0x22c */ u32 kernel_alignment; /* 0x230 */ u8 relocatable_kernel; /* 0x234 */ - u8 reserved13[155]; /* 0x22c */ + u8 reserved13[0x2b]; /* 0x235 */ + u32 init_size; /* 0x260 */ + u8 reserved14[0x6c]; /* 0x264 */ struct e820entry e820_map[E820MAX]; /* 0x2d0 */ u8 reserved16[688]; /* 0x550 */ #define COMMAND_LINE_SIZE 256

1 0

Patch set updated for coreboot: apple/imac52: add mainboard
by Arthur Heymans 28 Sep '16

28 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16638 -gerrit commit 04740b379abadc62d64f886d6b2fd5412cb83b99 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Sep 18 20:15:45 2016 +0200 apple/imac52: add mainboard Add Imac5,2 based on macbook2,1 port. Change-Id: I34c8313c32920b02a2b964d8718e5b2b6b5a6820 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/imac52/Kconfig | 7 ++++++ src/mainboard/apple/imac52/Kconfig.name | 2 ++ src/mainboard/apple/imac52/board_info.txt | 8 +++++++ src/mainboard/apple/macbook21/Kconfig | 2 +- src/mainboard/apple/macbook21/hda_verb.c | 38 +++++++++++++++++++++++++++++++ src/mainboard/apple/macbook21/romstage.c | 14 +++++++++++- 6 files changed, 69 insertions(+), 2 deletions(-) diff --git a/src/mainboard/apple/imac52/Kconfig b/src/mainboard/apple/imac52/Kconfig new file mode 100644 index 0000000..ba2ff95 --- /dev/null +++ b/src/mainboard/apple/imac52/Kconfig @@ -0,0 +1,7 @@ +if BOARD_APPLE_IMAC52 + +config MAINBOARD_PART_NUMBER + string + default "iMac5,2" + +endif diff --git a/src/mainboard/apple/imac52/Kconfig.name b/src/mainboard/apple/imac52/Kconfig.name new file mode 100644 index 0000000..034222b --- /dev/null +++ b/src/mainboard/apple/imac52/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_IMAC52 + bool "iMac5,2" diff --git a/src/mainboard/apple/imac52/board_info.txt b/src/mainboard/apple/imac52/board_info.txt new file mode 100644 index 0000000..918d394 --- /dev/null +++ b/src/mainboard/apple/imac52/board_info.txt @@ -0,0 +1,8 @@ +Board name: iMac5,2 +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Clone of: apple/macbook21 +Release year: 2007 diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index e653c08..ebf3954 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -1,4 +1,4 @@ -if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 +if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c index c048481..e0fc92e 100644 --- a/src/mainboard/apple/macbook21/hda_verb.c +++ b/src/mainboard/apple/macbook21/hda_verb.c @@ -19,6 +19,7 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */ +#if CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21 0x106b2200, /* Subsystem ID */ 0x0000000B, /* Number of 4 dword sets */ @@ -54,6 +55,43 @@ const u32 cim_verb_data[] = { /* NID 0x1B. */ AZALIA_PIN_CFG(0x0, 0x1B, 0x400000FB), +#else /* CONFIG_BOARD_APPLE_IMAC52 */ + 0x106b0f00, /* Subsystem ID */ + 0x0000000b, /* Number of 4 dword sets */ + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b0f00), + + /* NID 0x0A. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x012be032), + + /* NID 0x0B. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90afe111), + + /* NID 0x0C. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x9017e131), + + /* NID 0x0D. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x4080e10f), + + /* NID 0x0E. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x40f0e00f), + + /* NID 0x0F */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x018be021), + + /* NID 0x10 */ + AZALIA_PIN_CFG(0x0, 0x10, 0x114bf033), + + /* NID 0x11 */ + AZALIA_PIN_CFG(0x0, 0x11, 0x11cbc022), + + /* NID 0x15 */ + AZALIA_PIN_CFG(0x0, 0x15, 0x4080e10f), + + /* NID 0x1B. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x4080e10f), +#endif }; diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 4d49e89..695f1cd 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -62,7 +62,7 @@ void setup_ich7_gpios(void) * 39: PLANARID3 * 48: FWH_TBL# */ - +#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21) outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ @@ -73,6 +73,18 @@ void setup_ich7_gpios(void) outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +#else /* CONFIG_BOARD_APPLE_IMAC52 */ + outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xfcc06bff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00000082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000100c8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +#endif } static void ich7_enable_lpc(void)

1 0

Patch set updated for coreboot: mb/intel: Add Saddle Brook board support
by Boon Tiong Teo 28 Sep '16

28 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16608 -gerrit commit ec036481792441b5c3e525a5e51df7994248f6c8 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Sep 15 11:49:04 2016 +0800 mb/intel: Add Saddle Brook board support Change-Id: I95c752922a74369cb8ae77be6cb886e4597814e4 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/mainboard/intel/saddlebrook/Kconfig | 45 +++++++ src/mainboard/intel/saddlebrook/Kconfig.name | 2 + src/mainboard/intel/saddlebrook/acpi/ec.asl | 14 +++ src/mainboard/intel/saddlebrook/acpi/mainboard.asl | 26 ++++ src/mainboard/intel/saddlebrook/acpi/superio.asl | 14 +++ src/mainboard/intel/saddlebrook/acpi_tables.c | 15 +++ src/mainboard/intel/saddlebrook/board_info.txt | 6 + src/mainboard/intel/saddlebrook/cmos.layout | 135 +++++++++++++++++++++ src/mainboard/intel/saddlebrook/devicetree.cb | 112 +++++++++++++++++ src/mainboard/intel/saddlebrook/dsdt.asl | 49 ++++++++ src/mainboard/intel/saddlebrook/fadt.c | 47 +++++++ src/mainboard/intel/saddlebrook/onboard.h | 19 +++ src/mainboard/intel/saddlebrook/romstage.c | 87 +++++++++++++ 13 files changed, 571 insertions(+) diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig new file mode 100644 index 0000000..691a080 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_SKLSDLBRK + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select MMCONF_SUPPORT + select MONOTONIC_TIMER_MSR + select PCIEXP_L1_SUB_STATE + select SOC_INTEL_SKYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select CONSOLE_SERIAL + select DRIVERS_UART + + +config IRQ_SLOT_COUNT + int + default 18 + +config BOOT_MEDIA_SPI_BUS + int + default 0 + +config MAINBOARD_DIR + string + default "intel/saddlebrook" + +config MAINBOARD_PART_NUMBER + string + default "Skylake Saddle Brook" + +config MAX_CPUS + int + default 8 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +endif diff --git a/src/mainboard/intel/saddlebrook/Kconfig.name b/src/mainboard/intel/saddlebrook/Kconfig.name new file mode 100644 index 0000000..c85fb81 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SKLSDLBRK + bool "Skylake Saddle Brook" diff --git a/src/mainboard/intel/saddlebrook/acpi/ec.asl b/src/mainboard/intel/saddlebrook/acpi/ec.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl new file mode 100644 index 0000000..76e9707 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> +#include <mainboard/intel/saddlebrook/onboard.h> + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} diff --git a/src/mainboard/intel/saddlebrook/acpi/superio.asl b/src/mainboard/intel/saddlebrook/acpi/superio.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/saddlebrook/acpi_tables.c b/src/mainboard/intel/saddlebrook/acpi_tables.c new file mode 100644 index 0000000..ccf9f74 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi_tables.c @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/saddlebrook/board_info.txt b/src/mainboard/intel/saddlebrook/board_info.txt new file mode 100644 index 0000000..5b33adf --- /dev/null +++ b/src/mainboard/intel/saddlebrook/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Saddle Brook Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout new file mode 100644 index 0000000..8467747 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb new file mode 100644 index 0000000..bd2a552 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -0,0 +1,112 @@ +chip soc/intel/skylake + + # SerialIO device modes + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoPci, \ + }" + + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # Enable S0ix + register "s0ix_enable" = "0" + + # Probeless Trace function + register "ProbelessTrace" = "0" + + # I/O Buffer Ownership: + # 0: HD-A Link + # 1 Shared, HD-A Link and I2S Port + # 3: I2S Ports + register "IoBufferOwnership" = "3" + + # Audio related + register "DspEnable" = "0" + + # USB related + register "SsicPortEnable" = "0" + + # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "2" + + # Integrated Sensor + register "IshEnable" = "0" + + # XDCI controller + register "XdciEnable" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT-Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 off end # PCI Express Port 17 + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on end # LPC Interface (eSPI Enable Strap = 0) eSPI Interface (eSPI Enable Strap = 1) + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus Controller + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl new file mode 100644 index 0000000..4134867 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/saddlebrook/fadt.c b/src/mainboard/intel/saddlebrook/fadt.c new file mode 100644 index 0000000..05fea01 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/fadt.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/saddlebrook/onboard.h b/src/mainboard/intel/saddlebrook/onboard.h new file mode 100644 index 0000000..f902542 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/onboard.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#endif diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c new file mode 100644 index 0000000..5671357 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <soc/cpu.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +void car_mainboard_pre_console_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_romstage_entry(struct romstage_params *params) +{ + post_code(0x31); + /* Fill out PEI DATA */ + mainboard_fill_pei_data(params->pei_data); + mainboard_fill_spd_data(params->pei_data); + /* Initliaze memory */ + romstage_common(params); +} + +void mainboard_memory_init_params( + struct romstage_params *params, + MEMORY_INIT_UPD *mupd) +{ + /* Get SPD data passing strucutre and initialize it.*/ + if (params->pei_data->spd_data[0][0][0] != 0) { + mupd->MemorySpdPtr00 = + (UINT32)(params->pei_data->spd_data[0][0]); + mupd->MemorySpdPtr10 = + (UINT32)(params->pei_data->spd_data[1][0]); + } + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", + mupd->MemorySpdPtr00); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", + mupd->MemorySpdPtr01); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", + mupd->MemorySpdPtr10); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", + mupd->MemorySpdPtr11); + + /* + * Configure the DQ/DQS settings if required. In general the settings + * should be set in the FSP flash image and should not need to be + * changed. + */ + memcpy(mupd->DqByteMapCh0, params->pei_data->dq_map[0], + sizeof(params->pei_data->dq_map[0])); + memcpy(mupd->DqByteMapCh1, params->pei_data->dq_map[1], + sizeof(params->pei_data->dq_map[1])); + memcpy(mupd->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], + sizeof(params->pei_data->dqs_map[0])); + memcpy(mupd->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], + sizeof(params->pei_data->dqs_map[1])); + memcpy(mupd->RcompResistor, params->pei_data->RcompResistor, + sizeof(params->pei_data->RcompResistor)); + memcpy(mupd->RcompTarget, params->pei_data->RcompTarget, + sizeof(params->pei_data->RcompTarget)); + + mupd->DqPinsInterleaved = TRUE; +}

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coreboot-gerrit September 2016