coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Gale: Fixing the orange color to match the UX doc
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16767 -gerrit commit 102a6211fe4a0f9ecb7ae33a8f08763364e93f8e Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Thu Sep 22 08:20:16 2016 -0700 Gale: Fixing the orange color to match the UX doc UX Doc = go/gale-hw-ui This color wasn't changed earlier as the change wasn't done in the OS also. However, since we cannot change this later in FW (but OS can change anytime), I am making this change after discussing with the UX team. BUG=b:31501528, b:31633562 TEST=Change the device state to 'recovery mode' to observe the new color. BRANCH=none Change-Id: Ia91f14eb77492095cb41a9de0bb9790e72aa4851 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 36a3d8c6eabbc0b23d0a15d5bddc5ed3bdeebe70 Original-Change-Id: I88768b94cf91804a6005e44b1a168e059698ec4b Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/388206 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Christopher Book <cbook(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> --- src/drivers/i2c/ww_ring/ww_ring_programs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index fb74a1b..0c70e10 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -170,8 +170,8 @@ static const TiLp55231Program blink_wipeout1_program = { static const uint8_t blink_recovery1_text[] = { 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, 0x94, 0x02, 0x9f, 0x80, 0x98, 255, 0x84, 0x62, - 0x9f, 0x81, 0x98, 50, 0x84, 0x62, 0x9f, 0x82, - 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x9f, 0x81, 0x98, 100, 0x84, 0x62, 0x9f, 0x82, + 0x98, 10, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, 0xc0, 0x00, 0xc0, 0x00, 0x00,

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Patch set updated for coreboot: rockchip/rk3399: Actually remove big CPU initialization from bootblock
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16769 -gerrit commit 9a346cdfdf4ebe343765ffa5892c3cd86f547d20 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 23 16:07:42 2016 -0700 rockchip/rk3399: Actually remove big CPU initialization from bootblock CL:377541 was supposed to remove the big CPU cluster initialization from rkclk_init() in the bootblock and move it to a more suitable place in ramstage. Except that next to all the code cleanup I did in that patch, I seem to have forgotten to actually remove that old code. Big thanks to Nico for spotting that in the upstream coreboot review. BRANCH=gru BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I09fe948b4587536802b42329b813177439e0804f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 77f9eaf0446b22adfca79d0adf8a0ecfd93c0040 Original-Change-Id: I13dab208225b7e43ad864f2f3cf51b3c104acd4b Original-Reported-by: Nico Huber <nico.h(a)gmx.de> Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/389236 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/soc/rockchip/rk3399/clock.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index b9de844..2596853 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -411,13 +411,6 @@ void rkclk_init(void) rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg); rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg); - /* - * coreboot boot from little core, but it seem if apll_b use defalut - * 24MHz it will take a long time to enable big core, and will cause - * a watchdog crash, so we should do apll_b initialization here - */ - rkclk_configure_cpu(APLL_600_MHZ, true); - /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);

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Patch set updated for coreboot: google/gru: pass the gpio power supply enable pin to bl31
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16719 -gerrit commit 76242247cb3accc452b4847713137721053359f1 Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Aug 22 17:35:40 2016 -0700 google/gru: pass the gpio power supply enable pin to bl31 we need to disable some regulator when device into suspend, it mean we need to pass some gpio to bl31, and disable these gpios when bl31 run suspend function. BRANCH=None BUG=chrome-os-partner:56423 TEST=enter suspend, measure suspend gpio go to low [pg: also update arm-trusted-firmware to match] Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70 Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/374046 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- 3rdparty/arm-trusted-firmware | 2 +- src/mainboard/google/gru/board.h | 3 +++ src/mainboard/google/gru/mainboard.c | 43 ++++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index e4f51ee..bfd9251 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit e4f51eee91187e980f5e0e436c65f325fc35c94b +Subproject commit bfd925139fdbc2e87979849907b34843aa326994 diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index 382c462..7880cca 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -25,6 +25,9 @@ #define GPIO_POWEROFF GPIO(1, A, 6) #define GPIO_RESET GPIO(0, B, 3) #define GPIO_WP GPIO(1, C, 2) +#define GPIO_P15V_EN GPIO(0, B, 2) +#define GPIO_P30V_EN GPIO(0, B, 4) +#define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 8359ca4..902228b 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -43,6 +43,48 @@ static void configure_emmc(void) rkclk_configure_emmc(); } +static void register_gpio_suspend(void) +{ + /* + * these 3 pin to disable gpio2 ~ gpio4 1.5v, 1.8v, 3.3v power supply + * so need to shut down the power supply from high voltage to + * low voltage, and consider register_bl31() appends to the front off + * the list, we should register 1.5v enable pin to 3.3v enable pin + */ + static struct bl31_gpio_param param_p15_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p15_en.gpio.index = GET_GPIO_NUM(GPIO_P15V_EN); + register_bl31_param(&param_p15_en.h); + + static struct bl31_gpio_param param_p18_audio_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p18_audio_en.gpio.index = GET_GPIO_NUM(GPIO_P18V_AUDIO_PWREN); + register_bl31_param(&param_p18_audio_en.h); + + static struct bl31_gpio_param param_p30_en = { + .h = { + .type = PARAM_SUSPEND_GPIO, + }, + .gpio = { + .polarity = BL31_GPIO_LEVEL_LOW, + }, + }; + param_p30_en.gpio.index = GET_GPIO_NUM(GPIO_P30V_EN); + register_bl31_param(&param_p30_en.h); +} + static void register_reset_to_bl31(void) { static struct bl31_gpio_param param_reset = { @@ -184,6 +226,7 @@ static void mainboard_init(device_t dev) setup_usb(); register_reset_to_bl31(); register_poweroff_to_bl31(); + register_gpio_suspend(); } static void enable_backlight_booster(void)

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Patch set updated for coreboot: soc/qualcomm/ipq40xx: Fix GPIO pull up config.
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16770 -gerrit commit 9d7dbe26e5501453738198375be70ba9969a9d85 Author: Kan Yan <kyan(a)google.com> Date: Thu Sep 22 18:59:18 2016 -0700 soc/qualcomm/ipq40xx: Fix GPIO pull up config. BUG=b:31690391 TEST=Tested with board ID BRANCH=none Change-Id: I9a2b7eec111a79827f72a506942a8ec833ba7e60 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f23e2b6e72491aaafa15774f9bded3e14363abbc Original-Change-Id: I23183db29d7f7dd812e94ab6a1f2f1329c46ac60 Original-Signed-off-by: Kan Yan <kyan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/388778 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj(a)chromium.org> --- src/soc/qualcomm/ipq40xx/include/soc/gpio.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h index 3f9c385..220ea93 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h @@ -48,8 +48,7 @@ /* GPIO TLMM: Pullup/Pulldown */ #define GPIO_NO_PULL 0 #define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 +#define GPIO_PULL_UP 2 /* GPIO TLMM: Drive Strength */ #define GPIO_2MA 0

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Patch set updated for coreboot: google/gru: pass apio number to arm-trust-firmware
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16720 -gerrit commit 5c624474f3ab514a47bb7ae80c65d787159c7f39 Author: Lin Huang <hl(a)rock-chips.com> Date: Tue Aug 30 15:34:42 2016 -0700 google/gru: pass apio number to arm-trust-firmware for save power consumption, some gpio2 ~ gpio4 need to set to input and pull none mode. It depend on these gpio should shut down there power supply, so pass apio number to ATF, to decide which gpio need to config. BRANCH=None BUG=chrome-os-partner:56423 TEST=run suspend_stress_test on kevin board Change-Id: Id57fe8f622ae3f9c2bc7e58be89518b2b846cd37 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9c42082d1ca9a6baa735821382d3e83c1f8dc9ad Original-Change-Id: Iaf441e8e34c5591ffe7c65f6533fcf0b733ff5ac Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/378475 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/mainboard.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 902228b..8b9f595 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -43,6 +43,23 @@ static void configure_emmc(void) rkclk_configure_emmc(); } +static void register_apio_suspend(void) +{ + static struct bl31_apio_param param_apio = { + .h = { + .type = PARAM_SUSPEND_APIO, + }, + .apio = { + .apio1 = 1, + .apio2 = 1, + .apio3 = 1, + .apio4 = 1, + .apio5 = 1, + }, + }; + register_bl31_param(&param_apio.h); +} + static void register_gpio_suspend(void) { /* @@ -227,6 +244,7 @@ static void mainboard_init(device_t dev) register_reset_to_bl31(); register_poweroff_to_bl31(); register_gpio_suspend(); + register_apio_suspend(); } static void enable_backlight_booster(void)

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Patch set updated for coreboot: google/gru: set W2W_DIFFCS_DLY to 5
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16721 -gerrit commit 22a9f0508ad40638705393390cfa93812d943380 Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Sep 21 17:05:43 2016 +0800 google/gru: set W2W_DIFFCS_DLY to 5 It will enable PHY_PER_CS_TRAINING when DDR DDR frequency >= 666. For per cs training, the controller should consider the PHY delay line switch time,there should be more cycles to switch delay line. So need increase W2W_DIFFCS_DLY_ value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387506 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 6 +++--- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index c877158..5330141 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x05050502, /* DENALI_CTL_215_DATA */ 0x02080808, /* DENALI_CTL_216_DATA */ 0x02050202, /* DENALI_CTL_217_DATA */ - 0x02010202, /* DENALI_CTL_218_DATA */ - 0x00010202, /* DENALI_CTL_219_DATA */ + 0x02050202, /* DENALI_CTL_218_DATA */ + 0x00050202, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x02010200, /* DENALI_CTL_221_DATA */ 0x00010201, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index 591924d..4b73cb0 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x08080803, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050203, /* DENALI_CTL_217_DATA */ - 0x02010303, /* DENALI_CTL_218_DATA */ - 0x00010203, /* DENALI_CTL_219_DATA */ + 0x02050303, /* DENALI_CTL_218_DATA */ + 0x00050203, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020400, /* DENALI_CTL_221_DATA */ 0x00020401, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index b738644..3056e55 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x0a0a0a03, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020500, /* DENALI_CTL_221_DATA */ 0x00020501, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 362489b..3947881 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -278,9 +278,9 @@ struct rk3399_sdram_params params = { 0x04040001, /* DENALI_CTL_214_DATA */ 0x0c0c0c04, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ - 0x02010103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_217_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x06030600, /* DENALI_CTL_221_DATA */ 0x00030603, /* DENALI_CTL_222_DATA */

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Patch set updated for coreboot: rockchip/rk3399: dram: improve dram stability when run high frequency
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16722 -gerrit commit 5d06eb0494b95bfa03d40d93fa679b87b1e60b88 Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Sep 21 18:19:24 2016 +0800 rockchip/rk3399: dram: improve dram stability when run high frequency there are two modify in the driver: 1. correctly set speeds base on DDR frequency. Controls the speeds in the predriver circuits to reduce power. SPEED[1:0] 2'b00:less than 800Mbps(400MHz) 2b01 : 800Mbps(400MHz) to 1600Mbps(800MHz) 2b10 : 1600Mbsp(800MHz) to 2400Mbps(1200MHz) 2b11 : 3200Mbps and greater 2. config the number of cycles phy clock pll wait time after locking base on ddr config file. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: Iaf6da59c6c5c290867e0922a2a99de272f4c7bde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 125cf8afac3a682d33896fe74a20ba1d498a3bd2 Original-Change-Id: Iabc17df37a701c4f052540c3c259f209a1db3c59 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387428 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/sdram.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9211895..1021c6b 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -322,6 +322,7 @@ static void phy_io_config(u32 channel, u32 mode_sel = 0; u32 reg_value; u32 drv_value, odt_value; + u32 speed; /* vref setting */ if (sdram_params->dramtype == LPDDR4) { @@ -436,22 +437,33 @@ static void phy_io_config(u32 channel, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + + /* speed setting */ + if (sdram_params->ddr_freq < 400*MHz) + speed = 0x0; + else if (sdram_params->ddr_freq < 800*MHz) + speed = 0x1; + else if (sdram_params->ddr_freq < 1200*MHz) + speed = 0x2; + else + speed = 0x3; + /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x3 << 21, mode_sel << 21); + clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x3 << 9, mode_sel << 9); + clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x3 << 9, mode_sel << 9); + clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); } static void pctl_cfg(u32 channel, @@ -477,9 +489,10 @@ static void pctl_cfg(u32 channel, /* rank count need to set for init */ set_memory_map(channel, sdram_params); - write32(&denali_phy[910], 0x6400); - write32(&denali_phy[911], 0x01221102); - write32(&denali_phy[912], 0x0); + write32(&denali_phy[910], sdram_params->phy_regs.denali_phy[910]); + write32(&denali_phy[911], sdram_params->phy_regs.denali_phy[911]); + write32(&denali_phy[912], sdram_params->phy_regs.denali_phy[912]); + pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);

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Patch set updated for coreboot: soc/intel/apollolake: Use fixed resource for SRAM and IPC1
by Lijian Zhao 27 Sep '16

27 Sep '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16648 -gerrit commit 98bd13e7c421ab22c57621f823a77ab53565384a Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:15:29 2016 -0700 soc/intel/apollolake: Use fixed resource for SRAM and IPC1 Intel telemetry support will require PMC IPC1 and SRAM devices to be operated in ACPI mode. Then using fixed resources on BAR0, BAR1 and BAR2 (PMC only) for those two devices will help the resource assignment in DSDT stage. BUG=chrome-os-partner:57364 BRANCH=None TEST=Boot up into Chrome OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/iomap.h | 6 +++ src/soc/intel/apollolake/include/soc/pci_ids.h | 1 + src/soc/intel/apollolake/pmc.c | 11 +++++ src/soc/intel/apollolake/pmutil.c | 3 +- src/soc/intel/apollolake/sram.c | 68 ++++++++++++++++++++++++++ 6 files changed, 88 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3c45cbe..4f867e1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -71,6 +71,7 @@ ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smi.c +ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 2045434..621b0a6 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -32,6 +32,12 @@ /* Accesses to these BARs are hardcoded in FSP */ #define PMC_BAR0 0xfe042000 #define PMC_BAR1 0xfe044000 +#define PMC_BAR0_SIZE (8 * KiB) + +#define PMC_SRAM_BASE_0 0xfe900000 +#define PMC_SRAM_SIZE_0 (8 * KiB) +#define PMC_SRAM_BASE_1 0xfe902000 +#define PMC_SRAM_SIZE_1 (4 * KiB) /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index cd56fdd..130263b 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -24,6 +24,7 @@ #define PCI_DEVICE_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_PMC 0x5a94 /* 00:0d.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ +#define PCI_DEVICE_ID_APOLLOLAKE_SRAM 0x5aec /* 00:0d.3 */ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */ diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 20c9492..4544e0d 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -39,6 +39,11 @@ static void read_resources(device_t dev) struct resource *res; pci_dev_read_resources(dev); + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = PMC_BAR0; + res->size = PMC_BAR0_SIZE; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = ACPI_PMIO_BASE; res->size = ACPI_PMIO_SIZE; @@ -58,6 +63,12 @@ static void set_resources(device_t dev) pci_dev_set_resources(dev); + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " PMC BAR"); + res = find_resource(dev, PCI_BASE_ADDRESS_4); pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_IO; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 56bb33d..80aaf71 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -34,8 +34,7 @@ static uintptr_t read_pmc_mmio_bar(void) { - uint32_t bar = pci_read_config32(PMC_DEV, PCI_BASE_ADDRESS_0); - return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + return PMC_BAR0; } uintptr_t get_pmc_mmio_bar(void) diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c new file mode 100644 index 0000000..44eb0ee --- /dev/null +++ b/src/soc/intel/apollolake/sram.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/iomap.h> + +static void read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = PMC_SRAM_BASE_0; + res->size = PMC_SRAM_SIZE_0; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, PCI_BASE_ADDRESS_2); + res->base = PMC_SRAM_BASE_1; + res->size = PMC_SRAM_SIZE_1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void set_resources(device_t dev) +{ + struct resource *res; + pci_dev_set_resources(dev); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " SRAM BAR 0"); + + res = find_resource(dev, PCI_BASE_ADDRESS_2); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " SRAM BAR 1"); +} + +static const struct device_operations device_ops = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_SRAM, +};

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New patch to review for coreboot: soc/qualcomm/ipq40xx: Fix GPIO pull up config.
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16770 -gerrit commit fb56b095abcd56a92fe424c14d36641fdc04d00e Author: Kan Yan <kyan(a)google.com> Date: Thu Sep 22 18:59:18 2016 -0700 soc/qualcomm/ipq40xx: Fix GPIO pull up config. BUG=b:31690391 TEST=Tested with board ID BRANCH=none Change-Id: I9a2b7eec111a79827f72a506942a8ec833ba7e60 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f23e2b6e72491aaafa15774f9bded3e14363abbc Original-Change-Id: I23183db29d7f7dd812e94ab6a1f2f1329c46ac60 Original-Signed-off-by: Kan Yan <kyan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/388778 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj(a)chromium.org> --- src/soc/qualcomm/ipq40xx/include/soc/gpio.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h index 3f9c385..220ea93 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/gpio.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/gpio.h @@ -48,8 +48,7 @@ /* GPIO TLMM: Pullup/Pulldown */ #define GPIO_NO_PULL 0 #define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 +#define GPIO_PULL_UP 2 /* GPIO TLMM: Drive Strength */ #define GPIO_2MA 0

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New patch to review for coreboot: rockchip/rk3399: Actually remove big CPU initialization from bootblock
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16769 -gerrit commit d4b839eac35e49346f0375c3217fbe8aff20bc11 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 23 16:07:42 2016 -0700 rockchip/rk3399: Actually remove big CPU initialization from bootblock CL:377541 was supposed to remove the big CPU cluster initialization from rkclk_init() in the bootblock and move it to a more suitable place in ramstage. Except that next to all the code cleanup I did in that patch, I seem to have forgotten to actually remove that old code. Big thanks to Nico for spotting that in the upstream coreboot review. BRANCH=gru BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I09fe948b4587536802b42329b813177439e0804f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 77f9eaf0446b22adfca79d0adf8a0ecfd93c0040 Original-Change-Id: I13dab208225b7e43ad864f2f3cf51b3c104acd4b Original-Reported-by: Nico Huber <nico.h(a)gmx.de> Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/389236 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/soc/rockchip/rk3399/clock.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index b9de844..2596853 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -411,13 +411,6 @@ void rkclk_init(void) rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg); rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg); - /* - * coreboot boot from little core, but it seem if apll_b use defalut - * 24MHz it will take a long time to enable big core, and will cause - * a watchdog crash, so we should do apll_b initialization here - */ - rkclk_configure_cpu(APLL_600_MHZ, true); - /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);

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coreboot-gerrit September 2016