coreboot-gerrit September 2016

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Patch set updated for coreboot: i2c/ww_ring: LED changes for Gale EVT3
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16697 -gerrit commit f5cfbaf438b0b407aa3b29398e9e2dd04d7bdb04 Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Mon Aug 15 16:18:11 2016 -0700 i2c/ww_ring: LED changes for Gale EVT3 Gale EVT3 has only one LED controller (earlier we had 2). Removing the support for the second controller and also the corresponding microcode. The color values used are the same as onHub (Arkham to be specific). BUG=b:30890905 TEST=Move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the differnet colors. BRANCH=None Change-Id: I853035610ea7ea7c8d29c30d2de13c9e2e786b2b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 593905d2d69daa7482318aa5f5c5cd7cf984043e Original-Change-Id: If8f22abd605faac6f6215ef600041740ce15ea0c Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/370821 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> --- src/drivers/i2c/ww_ring/ww_ring_programs.c | 232 ++++++----------------------- src/drivers/i2c/ww_ring/ww_ring_programs.h | 2 +- 2 files changed, 49 insertions(+), 185 deletions(-) diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index a35998c..5b0c8a8 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -46,36 +46,36 @@ * Solid LED display, the arguments of the set_pwm commands set intensity and * color of the display: -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b +row_red: dw 0000000000000001b +row_green: dw 0000000000000010b +row_blue: dw 0000000000000100b .segment program1 mux_map_addr row_red - set_pwm 1 + set_pwm 0 end .segment program2 mux_map_addr row_green - set_pwm 1 + set_pwm 0 end .segment program3 mux_map_addr row_blue - set_pwm 1 + set_pwm 0 end */ /* RGB set to 000000, resulting in all LEDs off. */ static const uint8_t solid_000000_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9F, 0x80, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9F, 0x80, 0x40, 0, 0xC0, 0x00, 0x9F, 0x81, 0x40, 0, 0xC0, 0x00, 0x9F, 0x82, 0x40, 0, 0xC0, 0x00 }; /* Rgb set to 128, resulting in a brightish white color. */ static const uint8_t solid_808080_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9F, 0x80, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9F, 0x80, 0x40, 128, 0xC0, 0x00, 0x9F, 0x81, 0x40, 128, 0xC0, 0x00, 0x9F, 0x82, 0x40, 128, 0xC0, 0x00 }; @@ -100,20 +100,10 @@ static const TiLp55231Program solid_000000_program = { * The three internal engines seem to be competing for resources and get out * of sync in seconds if left running asynchronously. * - * When there are two separate controllers, with three engine each, they all - * run away from each other in no time, resulting in some completely chaotic - * LED behavior. - * * When solid patterns are deployed with instanteneous color intensity * changes, all three LEDs can be controlled by one engine in sequential * accesses. But the controllers still neeed to be synchronized. * - * The first controller is loaded and started first, but it sits waiting for - * the trigger from the second controller to actually start the cycle. Once - * both controllers start running, the first controller is the master, sending - * sych triggers to the second one each time the LED is supposed to be turned - * on or off. - * * The maximum timer duration of lp55231 is .48 seconds. To achieve longer * blinking intervals the loops delays are deployed. Only the first controller * intervals need to be changed, as the second one is in lockstep with the @@ -126,29 +116,26 @@ static const TiLp55231Program solid_000000_program = { */ /* * blink_solid1.src -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b +row_red: dw 0000000000000001b +row_green: dw 0000000000000010b +row_blue: dw 0000000000000100b .segment program1 ld ra, 2 # LED on duration - ld rb, 10 # LED off duration + ld rb, 2 # LED off duration mux_map_addr row_red - trigger w{e} loop: - trigger s{e} - ld rc, 98 ; red intensity + ld rc, 180 ; red intensity set_pwm rc mux_map_addr row_green - ld rc, 0 ; green intensity + ld rc, 80 ; green intensity set_pwm rc mux_map_addr row_blue - ld rc, 234 ; blue intensity + ld rc, 0 ; blue intensity set_pwm rc wait1: wait 0.1 branch ra, wait1 - trigger s{e} set_pwm 0 mux_map_addr row_green set_pwm 0 @@ -158,203 +145,82 @@ wait2: wait 0.1 branch rb, wait2 branch 0, loop - -.segment program2 - end - -.segment program3 - end*/ -/* - * blink_solid2.src - -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b - -.segment program1 - ld ra, 98 - ld rb, 0 - ld rc, 234 - trigger s{e} - mux_map_addr row_red -loop: - trigger w{e} - set_pwm ra ; red intensity - mux_map_addr row_green - set_pwm rb ; green intensity - mux_map_addr row_blue - set_pwm rc ; blue intensity -wait1: - wait 0.1 - branch 1, wait1 - trigger w{e} - set_pwm 0 - mux_map_addr row_green - set_pwm 0 - mux_map_addr row_red - set_pwm 0 -wait2: - wait 0.1 - branch 1, wait2 - branch 0, loop - .segment program2 end - .segment program3 end */ static const uint8_t blink_wipeout1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0xf0, 0x00, 0xe0, 0x40, - 0x98, 255, 0x84, 0x62, 0x9f, 0x81, 0x98, 80, - 0x84, 0x62, 0x9f, 0x82, 0x98, 0, 0x84, 0x62, - 0x4c, 0x00, 0x86, 0x34, 0xe0, 0x40, 0x40, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, - 0x4c, 0x00, 0x86, 0x55, 0xa0, 0x04, 0xc0, 0x00, - 0xc0, 0x00, 0x00, -}; - -static const uint8_t blink_wipeout2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 255, - 0x94, 80, 0x98, 0, 0xe0, 0x40, 0x9f, 0x80, - 0xf0, 0x00, 0x84, 0x60, 0x9f, 0x81, 0x84, 0x61, - 0x9f, 0x82, 0x84, 0x62, 0x4c, 0x00, 0xa0, 0x8b, - 0xf0, 0x00, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, - 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0xa0, 0x93, - 0xa0, 0x05, 0xc0, 0x00, 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, + 0x94, 0x02, 0x9f, 0x80, 0x98, 180, 0x84, 0x62, + 0x9f, 0x81, 0x98, 80, 0x84, 0x62, 0x9f, 0x82, + 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, + 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, + 0xc0, 0x00, 0xc0, 0x00, 0x00, }; static const TiLp55231Program blink_wipeout1_program = { blink_wipeout1_text, sizeof(blink_wipeout1_text), 0, - { 3, 27, 28, } -}; -static const TiLp55231Program blink_wipeout2_program = { - blink_wipeout2_text, - sizeof(blink_wipeout2_text), - 0, - { 3, 26, 26, } + { 3, 24, 25, } }; static const uint8_t blink_recovery1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0xf0, 0x00, 0xe0, 0x40, - 0x98, 255, 0x84, 0x62, 0x9f, 0x81, 0x98, 24, - 0x84, 0x62, 0x9f, 0x82, 0x98, 0, 0x84, 0x62, - 0x4c, 0x00, 0x86, 0x34, 0xe0, 0x40, 0x40, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, - 0x4c, 0x00, 0x86, 0x55, 0xa0, 0x04, 0xc0, 0x00, - 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, + 0x94, 0x02, 0x9f, 0x80, 0x98, 255, 0x84, 0x62, + 0x9f, 0x81, 0x98, 50, 0x84, 0x62, 0x9f, 0x82, + 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, + 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, + 0xc0, 0x00, 0xc0, 0x00, 0x00, }; static const TiLp55231Program blink_recovery1_program = { blink_recovery1_text, sizeof(blink_recovery1_text), 0, - { 3, 27, 28, } -}; -static const uint8_t blink_recovery2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 255, - 0x94, 24, 0x98, 0, 0xe0, 0x40, 0x9f, 0x80, - 0xf0, 0x00, 0x84, 0x60, 0x9f, 0x81, 0x84, 0x61, - 0x9f, 0x82, 0x84, 0x62, 0x4c, 0x00, 0xa0, 0x8b, - 0xf0, 0x00, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, - 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0xa0, 0x93, - 0xa0, 0x05, 0xc0, 0x00, 0xc0, 0x00, 0x00, -}; -static const TiLp55231Program blink_recovery2_program = { - blink_recovery2_text, - sizeof(blink_recovery2_text), - 0, - { 3, 26, 26, } + { 3, 24, 25, } }; /* * fade_in1.src * - row_red: dw 0000000001001001b - row_green: dw 0000000010010010b - row_blue: dw 0000000100100100b + row_red: dw 0000000000000001b + row_green: dw 0000000000000010b + row_blue: dw 0000000000000100b .segment program1 mux_map_addr row_red - set_pwm 0h - trigger w{e} + set_pwm 1h trigger s{2|3} end - .segment program2 mux_map_addr row_green set_pwm 0h - trigger w{1} - ramp 2, 87 + ramp 2, 50 end - .segment program3 mux_map_addr row_blue set_pwm 0h loop3: trigger w{1} - ramp 2, 155 - end -*/ -/* - * fade_in2.src - * - row_red: dw 0000000001001001b - row_green: dw 0000000010010010b - row_blue: dw 0000000100100100b - - .segment program1 - mux_map_addr row_red - set_pwm 0h - trigger s{e} - trigger s{2|3} - end - - .segment program2 - mux_map_addr row_green - set_pwm 0h - - trigger w{1} - ramp 2, 87 - end - -.segment program3 - mux_map_addr row_blue - set_pwm 0h - loop3: trigger w{1} - ramp 2, 155 + ramp 2, 255 end */ static const uint8_t fade_in1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9f, 0x80, - 0x40, 0x00, 0xf0, 0x00, 0xe0, 0x0c, 0xc0, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x42, 0x57, - 0xc0, 0x00, 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, - 0x34, 0x9b, 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9f, 0x80, + 0x40, 0x01, 0xe0, 0x0c, 0xc0, 0x00, 0x9f, 0x81, + 0x40, 0x00, 0xe0, 0x80, 0x46, 0x32, 0xc0, 0x00, + 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, 0x20, 0xff, + 0xc0, 0x00, 0x00, }; static const TiLp55231Program fade_in1_program = { fade_in1_text, sizeof(fade_in1_text), 0, - { 3, 8, 13, } -}; - -static const uint8_t fade_in2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9f, 0x80, - 0x40, 0x00, 0xe0, 0x40, 0xe0, 0x0c, 0xc0, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x42, 0x57, - 0xc0, 0x00, 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, - 0x34, 0x9b, 0xc0, 0x00, 0x00, -}; -static const TiLp55231Program fade_in2_program = { - fade_in2_text, - sizeof(fade_in2_text), - 0, - { 3, 8, 13, } + { 3, 7, 12, } }; const WwRingStateProg wwr_state_programs[] = { @@ -362,12 +228,10 @@ const WwRingStateProg wwr_state_programs[] = { * for test purposes the blank screen program is set to blinking, will * be changed soon. */ - {WWR_ALL_OFF, {&solid_000000_program, &solid_000000_program} }, - {WWR_RECOVERY_PUSHED, {&solid_808080_program, &solid_808080_program} }, - {WWR_WIPEOUT_REQUEST, {&blink_wipeout1_program, - &blink_wipeout2_program} }, - {WWR_RECOVERY_REQUEST, {&blink_recovery1_program, - &blink_recovery2_program} }, - {WWR_NORMAL_BOOT, {&fade_in1_program, &fade_in2_program} }, + {WWR_ALL_OFF, {&solid_000000_program} }, + {WWR_RECOVERY_PUSHED, {&solid_808080_program} }, + {WWR_WIPEOUT_REQUEST, {&blink_wipeout1_program} }, + {WWR_RECOVERY_REQUEST, {&blink_recovery1_program} }, + {WWR_NORMAL_BOOT, {&fade_in1_program} }, {}, /* Empty record to mark the end of the table. */ }; diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index 9f4b928..5fb8ebf 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -36,7 +36,7 @@ #define LP55231_NUM_OF_ENGINES 3 /* Number of lp55321 controllers on the ring */ -#define WW_RING_NUM_LED_CONTROLLERS 2 +#define WW_RING_NUM_LED_CONTROLLERS 1 /* * Structure to describe an lp55231 program: pointer to the text of the

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Patch set updated for coreboot: rockchip/rk3399: Remove CONFIG_ARM64_A53_ERRATUM_843419
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16702 -gerrit commit 472299d5b9c364b490fdc70993ec2c43bfdfa01c Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Aug 25 22:37:38 2016 -0700 rockchip/rk3399: Remove CONFIG_ARM64_A53_ERRATUM_843419 As far as I know, the Cortex-A53 cores in RK3399 are of a newer revision that is not affected by ARM erratum 843419. If it was, the workaround would also need to be enabled in libpayload and Chrome OS userspace, which it currently isn't. I assume this was just incorrectly copied over from another SoC and we can safely remove it. BRANCH=None BUG=chrome-os-partner:56700 TEST=Booted Kevin. Change-Id: I5b1534c954a6d985499b481738723cabbdc07253 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4891cc866583532ee3dcb1a5ad5b81670eb0743d Original-Change-Id: Iadb57428f8727ce0e563204723644e2c79e3007c Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376363 Original-Commit-Queue: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/soc/rockchip/rk3399/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 1eaa870..b4017c8 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -5,7 +5,6 @@ config SOC_ROCKCHIP_RK3399 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 - select ARM64_A53_ERRATUM_843419 select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select DRIVERS_UART_8250MEM_32

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Patch set updated for coreboot: rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16703 -gerrit commit 8b57fbce1e3ff1c9c19974e791be5f7a313ba1c0 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 2 23:48:10 2016 -0700 rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ This patch fixes a typo in the clock initialization code that caused the PERILP1_PCLK_HZ constant to be ignored and the clock to always run at the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our previous tests and validation with this bug, we should probably increase the value of the constant (that had not actually been used) to the value that we had been incorrectly using instead (which also makes effective SPI read times faster). BRANCH=None BUG=chrome-os-partner:56556 TEST=Booted Kevin. Change-Id: Ibeb08f5fe5e984a74e3f57e60c62d4bfb644b6ca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 06e605a5fcb9bdf13a3d301112380633b892fd4e Original-Change-Id: Icb5e079f53eb22b0dbf0ea4d1c2ff08688e3fa8e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381031 Original-Reviewed-by: Simon Glass <sjg(a)chromium.org> --- src/soc/rockchip/rk3399/clock.c | 6 +++--- src/soc/rockchip/rk3399/include/soc/clock.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 1ae254d..ded0a94 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -477,9 +477,9 @@ void rkclk_init(void) assert((hclk_div + 1) * PERILP1_HCLK_HZ == GPLL_HZ && (hclk_div < 0x1f)); - pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; - assert((pclk_div + 1) * PERILP1_HCLK_HZ == - PERILP1_HCLK_HZ && (hclk_div < 0x7)); + pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; + assert((pclk_div + 1) * PERILP1_PCLK_HZ == + PERILP1_HCLK_HZ && (pclk_div < 0x7)); write32(&cru_ptr->clksel_con[25], RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 9d57e46..5926051 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -92,7 +92,7 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PERILP0_PCLK_HZ (49500*KHz) #define PERILP1_HCLK_HZ (99000*KHz) -#define PERILP1_PCLK_HZ (49500*KHz) +#define PERILP1_PCLK_HZ (99000*KHz) #define PWM_CLOCK_HZ PMU_PCLK_HZ

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Patch set updated for coreboot: google/gru: Init the PWM pinmux after setting up the PWM
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16700 -gerrit commit ea6078903682a28d72ba69748d135854f6392e07 Author: Douglas Anderson <dianders(a)chromium.org> Date: Tue Sep 6 13:51:03 2016 -0700 google/gru: Init the PWM pinmux after setting up the PWM If we setup the PWM _after_ the pinmux then there's a period of time when we're driving the PWM incorrectly. Let's setup the regulator and _then_ configure the pinmux. This fixes no known bugs, but it is more correct and probably makes the signals look better at bootup. BRANCH=None BUG=None TEST=scope Change-Id: I311c0eded873b65e0489373e87b88bcdd8e4b806 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fcf4d0ba29d82cce779c0b25ead36de4a95d97a1 Original-Change-Id: I5124f48d04a18c07bbd2d54bc08ee001c9c7e8d1 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381592 Original-Reviewed-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/pwm_regulator.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index d0cdf43..d6d2eec 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -44,21 +44,6 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) int duty_ns, voltage_max, voltage_min; int voltage = millivolt * 10; /* for higer calculation accuracy */ - switch (pwm) { - case PWM_REGULATOR_GPU: - write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); - break; - case PWM_REGULATOR_BIG: - write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); - break; - case PWM_REGULATOR_LIT: - write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); - break; - case PWM_REGULATOR_CENTERLOG: - write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); - break; - } - voltage_min = PWM_DESIGN_VOLTAGE_MIN; voltage_max = PWM_DESIGN_VOLTAGE_MAX; if (!(IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) && @@ -80,4 +65,19 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) / (voltage_max - voltage_min); pwm_init(pwm, PWM_PERIOD, duty_ns); + + switch (pwm) { + case PWM_REGULATOR_GPU: + write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); + break; + case PWM_REGULATOR_BIG: + write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); + break; + case PWM_REGULATOR_LIT: + write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); + break; + case PWM_REGULATOR_CENTERLOG: + write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); + break; + } }

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Patch set updated for coreboot: spi: Add a way to show SPI transfer speed for reads
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16701 -gerrit commit 8f17afd8240e5fac85b49ba327546c9a9c3c6503 Author: Simon Glass <sjg(a)chromium.org> Date: Sat Aug 27 15:03:02 2016 -0600 spi: Add a way to show SPI transfer speed for reads SPI read speed directly impacts boot time and we do quite a lot of reading. Add a way to easily find out the speed of SPI flash reads within coreboot. Write speed is less important since there are very few writes and they are small. BUG=chrome-os-partner:56556 BRANCH=none TEST=run on gru with SPI_SPEED_DEBUG set to 1. See the output messages: read SPI 627d4 7d73: 18455 us, 1740 KB/s, 13.920 Mbps Change-Id: Id3814bd2b7bd045cdfcc67eb1fabc861bf9ed3b2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 82cb93f6be47efce3b0a3843bab89d2381baef89 Original-Change-Id: Iec66f5b8e3ad62f14d836a538dc7801e4ca669e7 Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376944 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/spi/cbfs_spi.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index 1895b9d..e76a665 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -23,14 +23,44 @@ #include <spi_flash.h> #include <symbols.h> #include <cbmem.h> +#include <timer.h> static struct spi_flash *spi_flash_info; +/* + * Set this to 1 to debug SPI speed, 0 to disable it + * The format is: + * + * read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps + * + * The important number is the last one. It should roughyly match your SPI + * clock. If it doesn't, your driver might need a little tuning. + */ +#define SPI_SPEED_DEBUG 0 + static ssize_t spi_readat(const struct region_device *rd, void *b, size_t offset, size_t size) { + struct stopwatch sw; + bool show = SPI_SPEED_DEBUG && size >= 4*KiB; + + if (show) + stopwatch_init(&sw); if (spi_flash_info->read(spi_flash_info, offset, size, b)) return -1; + if (show) { + long usecs; + + usecs = stopwatch_duration_usecs(&sw); + u64 speed; /* KiB/s */ + int bps; /* Bits per second */ + + speed = (u64)size * 1000 / usecs; + bps = speed * 8; + + printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n", + offset, size, usecs, speed, bps / 1000, bps % 1000); + } return size; }

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Patch set updated for coreboot: google/gru: pass apio number to arm-trust-firmware
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16720 -gerrit commit 925ff6b742787e69efb26b055c95c75b4b7d3fee Author: Lin Huang <hl(a)rock-chips.com> Date: Tue Aug 30 15:34:42 2016 -0700 google/gru: pass apio number to arm-trust-firmware for save power consumption, some gpio2 ~ gpio4 need to set to input and pull none mode. It depend on these gpio should shut down there power supply, so pass apio number to ATF, to decide which gpio need to config. BRANCH=None BUG=chrome-os-partner:56423 TEST=run suspend_stress_test on kevin board Change-Id: Id57fe8f622ae3f9c2bc7e58be89518b2b846cd37 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9c42082d1ca9a6baa735821382d3e83c1f8dc9ad Original-Change-Id: Iaf441e8e34c5591ffe7c65f6533fcf0b733ff5ac Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/378475 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/mainboard.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 902228b..8b9f595 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -43,6 +43,23 @@ static void configure_emmc(void) rkclk_configure_emmc(); } +static void register_apio_suspend(void) +{ + static struct bl31_apio_param param_apio = { + .h = { + .type = PARAM_SUSPEND_APIO, + }, + .apio = { + .apio1 = 1, + .apio2 = 1, + .apio3 = 1, + .apio4 = 1, + .apio5 = 1, + }, + }; + register_bl31_param(&param_apio.h); +} + static void register_gpio_suspend(void) { /* @@ -227,6 +244,7 @@ static void mainboard_init(device_t dev) register_reset_to_bl31(); register_poweroff_to_bl31(); register_gpio_suspend(); + register_apio_suspend(); } static void enable_backlight_booster(void)

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Patch set updated for coreboot: google/gru: set W2W_DIFFCS_DLY to 5
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16721 -gerrit commit 81b941167af36ebb68a5b1d519458b9997b03796 Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Sep 21 17:05:43 2016 +0800 google/gru: set W2W_DIFFCS_DLY to 5 It will enable PHY_PER_CS_TRAINING when DDR DDR frequency >= 666. For per cs training, the controller should consider the PHY delay line switch time,there should be more cycles to switch delay line. So need increase W2W_DIFFCS_DLY_ value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387506 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 4 ++-- src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 6 +++--- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c index c877158..5330141 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x05050502, /* DENALI_CTL_215_DATA */ 0x02080808, /* DENALI_CTL_216_DATA */ 0x02050202, /* DENALI_CTL_217_DATA */ - 0x02010202, /* DENALI_CTL_218_DATA */ - 0x00010202, /* DENALI_CTL_219_DATA */ + 0x02050202, /* DENALI_CTL_218_DATA */ + 0x00050202, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x02010200, /* DENALI_CTL_221_DATA */ 0x00010201, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index 591924d..4b73cb0 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x08080803, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050203, /* DENALI_CTL_217_DATA */ - 0x02010303, /* DENALI_CTL_218_DATA */ - 0x00010203, /* DENALI_CTL_219_DATA */ + 0x02050303, /* DENALI_CTL_218_DATA */ + 0x00050203, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020400, /* DENALI_CTL_221_DATA */ 0x00020401, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index b738644..3056e55 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -279,8 +279,8 @@ struct rk3399_sdram_params params = { 0x0a0a0a03, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ 0x02050103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x03020500, /* DENALI_CTL_221_DATA */ 0x00020501, /* DENALI_CTL_222_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 362489b..3947881 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -278,9 +278,9 @@ struct rk3399_sdram_params params = { 0x04040001, /* DENALI_CTL_214_DATA */ 0x0c0c0c04, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ - 0x02010103, /* DENALI_CTL_217_DATA */ - 0x02010103, /* DENALI_CTL_218_DATA */ - 0x00010103, /* DENALI_CTL_219_DATA */ + 0x02050103, /* DENALI_CTL_217_DATA */ + 0x02050103, /* DENALI_CTL_218_DATA */ + 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ 0x06030600, /* DENALI_CTL_221_DATA */ 0x00030603, /* DENALI_CTL_222_DATA */

1 0

Patch set updated for coreboot: rockchip/rk3399: dram: improve dram stability when run high frequency
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16722 -gerrit commit 1967b0246ca0b3441e40efc9e00af4b8015a9638 Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Sep 21 18:19:24 2016 +0800 rockchip/rk3399: dram: improve dram stability when run high frequency there are two modify in the driver: 1. correctly set speeds base on DDR frequency. Controls the speeds in the predriver circuits to reduce power. SPEED[1:0] 2'b00:less than 800Mbps(400MHz) 2b01 : 800Mbps(400MHz) to 1600Mbps(800MHz) 2b10 : 1600Mbsp(800MHz) to 2400Mbps(1200MHz) 2b11 : 3200Mbps and greater 2. config the number of cycles phy clock pll wait time after locking base on ddr config file. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: Iaf6da59c6c5c290867e0922a2a99de272f4c7bde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 125cf8afac3a682d33896fe74a20ba1d498a3bd2 Original-Change-Id: Iabc17df37a701c4f052540c3c259f209a1db3c59 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387428 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/sdram.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9211895..1021c6b 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -322,6 +322,7 @@ static void phy_io_config(u32 channel, u32 mode_sel = 0; u32 reg_value; u32 drv_value, odt_value; + u32 speed; /* vref setting */ if (sdram_params->dramtype == LPDDR4) { @@ -436,22 +437,33 @@ static void phy_io_config(u32 channel, /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + + /* speed setting */ + if (sdram_params->ddr_freq < 400*MHz) + speed = 0x0; + else if (sdram_params->ddr_freq < 800*MHz) + speed = 0x1; + else if (sdram_params->ddr_freq < 1200*MHz) + speed = 0x2; + else + speed = 0x3; + /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x3 << 21, mode_sel << 21); + clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x3 << 9, mode_sel << 9); + clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x3 << 9, mode_sel << 9); + clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x3 << 17, mode_sel << 17); + clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); } static void pctl_cfg(u32 channel, @@ -477,9 +489,10 @@ static void pctl_cfg(u32 channel, /* rank count need to set for init */ set_memory_map(channel, sdram_params); - write32(&denali_phy[910], 0x6400); - write32(&denali_phy[911], 0x01221102); - write32(&denali_phy[912], 0x0); + write32(&denali_phy[910], sdram_params->phy_regs.denali_phy[910]); + write32(&denali_phy[911], sdram_params->phy_regs.denali_phy[911]); + write32(&denali_phy[912], sdram_params->phy_regs.denali_phy[912]); + pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);

1 0

Patch set updated for coreboot: superio: Add back Nuvoton NCT6776 to support Intel Saddle Brook
by Boon Tiong Teo 27 Sep '16

27 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16519 -gerrit commit 571896f467a60c9c89f7515b0f3cafd8840d4556 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Mon Sep 5 16:00:07 2016 +0800 superio: Add back Nuvoton NCT6776 to support Intel Saddle Brook Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/common/early_serial.c | 3 + src/superio/nuvoton/nct6776/Kconfig | 23 +++++++ src/superio/nuvoton/nct6776/Makefile.inc | 18 ++++++ src/superio/nuvoton/nct6776/nct6776.h | 58 ++++++++++++++++++ src/superio/nuvoton/nct6776/superio.c | 99 +++++++++++++++++++++++++++++++ 6 files changed, 202 insertions(+) diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 94cc6b7..e2e178b 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -19,5 +19,6 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index fca5ed6..d1958a0 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -63,6 +63,9 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); + if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A)) + /* Route GPIO8 pin group to COM A */ + pnp_write_config(dev, 0x2a, 0x40); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); diff --git a/src/superio/nuvoton/nct6776/Kconfig b/src/superio/nuvoton/nct6776/Kconfig new file mode 100644 index 0000000..cf0fe21 --- /dev/null +++ b/src/superio/nuvoton/nct6776/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_NUVOTON_NCT6776 + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT6776_COM_A + bool + default n diff --git a/src/superio/nuvoton/nct6776/Makefile.inc b/src/superio/nuvoton/nct6776/Makefile.inc new file mode 100644 index 0000000..13fe527 --- /dev/null +++ b/src/superio/nuvoton/nct6776/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += superio.c diff --git a/src/superio/nuvoton/nct6776/nct6776.h b/src/superio/nuvoton/nct6776/nct6776.h new file mode 100644 index 0000000..520401e --- /dev/null +++ b/src/superio/nuvoton/nct6776/nct6776.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +#ifndef SUPERIO_NUVOTON_NCT6776_H +#define SUPERIO_NUVOTON_NCT6776_H + +/* Logical Device Numbers (LDN). */ +#define NCT6776_FDC 0x00 /* Floppy */ +#define NCT6776_PP 0x01 /* Parallel port */ +#define NCT6776_SP1 0x02 /* Com1 */ +#define NCT6776_SP2 0x03 /* Com2 & IR */ +#define NCT6776_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT6776_CIR 0x06 +#define NCT6776_GPIO6789_V 0x07 +#define NCT6776_WDT1_GPIO01A_V 0x08 +#define NCT6776_GPIO1234567_V 0x09 +#define NCT6776_ACPI 0x0A +#define NCT6776_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT6776_VID 0x0D +#define NCT6776_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT6776_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT6776_SVID 0x14 +#define NCT6776_DSLP 0x16 /* Deep sleep */ +#define NCT6776_GPIOA_LDN 0x17 + +/* virtual LDN for GPIO and WDT */ +#define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V) + +#define NCT6776_GPIOBASE ((0 << 8) | NCT6776_WDT1_GPIO01A_V) //? + +#define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V) +#define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO2 ((2 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO3 ((3 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO4 ((4 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO5 ((5 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO6 ((6 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO7 ((7 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO8 ((0 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIO9 ((1 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIOA ((2 << 8) | NCT6776_WDT1_GPIO01A_V) + +#endif /* SUPERIO_NUVOTON_NCT6776_H */ diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c new file mode 100644 index 0000000..85f52cf --- /dev/null +++ b/src/superio/nuvoton/nct6776/superio.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct6776.h" + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +static void nct6776_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case NCT6776_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6776_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_SP1, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_SP2, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, NCT6776_CIR, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_ACPI}, + { &ops, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + {0x0ffe, 0}, {0x0ffe, 4}, }, + { &ops, NCT6776_VID}, + { &ops, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO_PP_OD}, + { &ops, NCT6776_SVID}, + { &ops, NCT6776_DSLP}, + { &ops, NCT6776_GPIOA_LDN}, + { &ops, NCT6776_WDT1}, + { &ops, NCT6776_GPIOBASE, PNP_IO0, + {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO0}, + { &ops, NCT6776_GPIO1}, + { &ops, NCT6776_GPIO2}, + { &ops, NCT6776_GPIO3}, + { &ops, NCT6776_GPIO4}, + { &ops, NCT6776_GPIO5}, + { &ops, NCT6776_GPIO6}, + { &ops, NCT6776_GPIO7}, + { &ops, NCT6776_GPIO8}, + { &ops, NCT6776_GPIO9}, + { &ops, NCT6776_GPIOA}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6776_ops = { + CHIP_NAME("NUVOTON NCT6776 Super I/O") + .enable_dev = enable_dev, +};

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Patch merged into coreboot/master: x86: acpi: Use GOOG ID for coreboot table
by gerrit＠coreboot.org 27 Sep '16

27 Sep '16

the following patch was just integrated into master: commit 02fdb3e0142a263d839f1a11f1b6b7aa98351ddd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 22 14:08:33 2016 -0700 x86: acpi: Use GOOG ID for coreboot table Use the GOOG ACPI ID until there is an official ID allocation for coreboot. Since I administer this range I allocated 0xCB00-0xCBFF for coreboot use. Change-Id: I38ac0a0267e21f7282c89ef19e8bb72339f13846 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/16724 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16724 for details. -gerrit

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coreboot-gerrit September 2016