coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: mainboards, ec: provide common declaration for mainboard_ec_init()
by gerrit＠coreboot.org 26 Sep '16

26 Sep '16

the following patch was just integrated into master: commit 91fa9d7696ef88e580caa1f762e72bd9e3e18a18 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 23 16:38:27 2016 -0500 mainboards,ec: provide common declaration for mainboard_ec_init() Add a header file to provide common declarations that the mainboards can use regarding EC init. BUG=chrome-os-partner:56677 Change-Id: Iaa0b37eff4de644e969a18364713b90b7f27fa1c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16734 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16734 for details. -gerrit

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Patch merged into coreboot/master: mainboards/google/reef: use chromeec's ASL lid switch implementation
by gerrit＠coreboot.org 26 Sep '16

26 Sep '16

the following patch was just integrated into master: commit 59cf5028a85b2696ce2dc12b857c886cb05e9671 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 23 16:08:21 2016 -0500 mainboards/google/reef: use chromeec's ASL lid switch implementation Defer to the lid switch implementation provided by the chromeec. BUG=chrome-os-partner:56677 Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16733 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16733 for details. -gerrit

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Patch merged into coreboot/master: ec/google/chromeec: provide optional ASL lid switch implementation
by gerrit＠coreboot.org 26 Sep '16

26 Sep '16

the following patch was just integrated into master: commit 05201d778336f474e3f9df55431340fa95521aee Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 23 16:06:14 2016 -0500 ec/google/chromeec: provide optional ASL lid switch implementation Instead of relying on the mainboards to provide their own LID0 ACPI device, provide the infrastructure so that the mainboards can signal to the EC ASL code to provide the default lid switch implementation. BUG=chrome-os-partner:56677 Change-Id: Ie43b1c4f8522db1245f1f479bfdb685d3066121d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16732 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16732 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: provide power button ACPI device
by gerrit＠coreboot.org 26 Sep '16

26 Sep '16

the following patch was just integrated into master: commit c64a6d63ed9cbd20d8acd8d50ce76af275cca526 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 23 15:06:37 2016 -0500 soc/intel/apollolake: provide power button ACPI device Instead of having each mainboard provide the power button, uncondtionally provide the power button ACPI device on behalf of each mainboard. BUG=chrome-os-partner:56677 Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16731 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/16731 for details. -gerrit

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New patch to review for coreboot: fsp_Broadwell_DE: Set proper UART register width
by Kevin Herbert 26 Sep '16

26 Sep '16

Kevin Herbert (kevin(a)trippers.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16748 -gerrit commit 0270cdb826db2481b3d5352373bb0220cb1ae345 Author: Kevin Paul Herbert <kevin(a)trippers.org> Date: Mon Sep 26 14:23:43 2016 -0700 fsp_Broadwell_DE: Set proper UART register width The FSP version of Broadwell UART support removes the UART hardware initialization, as the FSP initializes the UART. Too much of the software initialization was removed, as the setup of the register width was omitted. This impacts payloads using coreboot tables for UART configuration, such as libpayload. Reproduced using FILO on Intel Camelback Mountain CRB. Change-Id: Iac43a5f8128eaa5c958649cf07d97e8623fb8ac3 --- src/soc/intel/fsp_broadwell_de/uart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/fsp_broadwell_de/uart.c b/src/soc/intel/fsp_broadwell_de/uart.c index d22dd0d..e1e1acd 100644 --- a/src/soc/intel/fsp_broadwell_de/uart.c +++ b/src/soc/intel/fsp_broadwell_de/uart.c @@ -105,6 +105,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_IO_MAPPED; serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); + serial.regwidth = 1; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data);

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Patch set updated for coreboot: rotor: Compose BOOTBLOCK region
by Daisuke Nojiri 26 Sep '16

26 Sep '16

Daisuke Nojiri (dnojiri(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16747 -gerrit commit 2919c3fa0ffd5b1e9bae980a3c5c919dfe404d12 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Sep 23 17:40:15 2016 -0700 rotor: Compose BOOTBLOCK region This patch adds a Makefile rule for mvmap2315 to install a BDB and bootblock code in the BOOTBLOCK region. BUG=chrome-os-partner:51907 BRANCH=none TEST=emerge-rotor coreboot and examined the output binary Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/soc/marvell/mvmap2315/Makefile.inc | 56 +++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index d30ab68..d215552 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -63,4 +63,58 @@ romstage-y += wdt.c CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ -endif +# Common Boot Flow parameters +KEYDIR = $(VBOOT_SOURCE)/tests/testkeys +BOOTBLOCK_REGION_SIZE = 131072 +BOOTBLOCK_TYPE = -1 +BOOTBLOCK_PARTITION = -1 +BOOTBLOCK_LOAD_ADDRESS = -1 +BDB = $(obj)/bdb.bin + +# Calculate bootblock.raw.bin's size and offset +.PHONY: bootblock_offset +bootblock_offset: $(objcbfs)/bootblock.raw.bin + $(eval BOOTBLOCK_SIZE = $(call file-size, $<)) + $(eval BOOTBLOCK_OFFSET = $(call int-subtract, \ + $(BOOTBLOCK_REGION_SIZE) $(BOOTBLOCK_SIZE))) + +# Create a BDB +$(BDB): $(objcbfs)/bootblock.raw.bin $(FUTILITY) bootblock_offset \ + $(KEYDIR)/bdbkey.pem $(KEYDIR)/bdbkey.keyb \ + $(KEYDIR)/datakey.pem $(KEYDIR)/datakey.keyb + $(FUTILITY) bdb --create $@.tmp \ + --bdbkey_pri $(KEYDIR)/bdbkey.pem \ + --bdbkey_pub $(KEYDIR)/bdbkey.keyb \ + --datakey_pri $(KEYDIR)/datakey.pem \ + --datakey_pub $(KEYDIR)/datakey.keyb + $(FUTILITY) bdb --add $@.tmp \ + --data $< \ + --offset $(BOOTBLOCK_OFFSET) \ + --partition $(BOOTBLOCK_PARTITION) \ + --type $(BOOTBLOCK_TYPE) \ + --load_address $(BOOTBLOCK_LOAD_ADDRESS) + $(FUTILITY) bdb --resign $@.tmp \ + --datakey_pri $(KEYDIR)/datakey.pem + $(FUTILITY) bdb --verify $@.tmp \ + --key_digest $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin + mv $@.tmp $@ + +# Overrides generic pattern rule *.raw.bin -> *.bin for bootblock.bin +# +# bootblock.bin is structured as follows: +# +------------------+ +# | BDB | +# +------------------+ +# | 000............0 | +# +------------------+ +# |bootblock.raw.bin | +# +------------------+ +# And this will be placed in BOOTBLOCK region. +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BDB) bootblock_offset + dd if=/dev/zero bs=1 count=$(BOOTBLOCK_REGION_SIZE) of=$@.tmp + dd if=$(BDB) bs=1 count=$(call file-size, $(BDB)) conv=notrunc of=$@.tmp + dd if=$(objcbfs)/bootblock.raw.bin bs=1 count=$(BOOTBLOCK_SIZE) \ + seek=$(BOOTBLOCK_OFFSET) conv=notrunc of=$@.tmp + mv $@.tmp $@ + +endif \ No newline at end of file

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New patch to review for coreboot: rotor: Compose BOOTBLOCK region
by Daisuke Nojiri 26 Sep '16

26 Sep '16

Daisuke Nojiri (dnojiri(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16747 -gerrit commit 2ffa0cbb62d996984a8c68d697761b44f2b5cee9 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Sep 23 17:40:15 2016 -0700 rotor: Compose BOOTBLOCK region This patch adds a Makefile rule for mvmap2315 to install a BDB and bootblock code in the BOOTBLOCK region. BUG=chrome-os-partner:51907 BRANCH=none TEST=emerge-rotor coreboot and examined the output binary Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/soc/marvell/mvmap2315/Makefile.inc | 57 +++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index d30ab68..f681c76 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -63,4 +63,59 @@ romstage-y += wdt.c CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ -endif +# Common Boot Flow parameters +KEYDIR = $(VBOOT_SOURCE)/tests/testkeys +BOOTBLOCK_REGION_SIZE = 131072 +BOOTBLOCK_LOAD_ADDRESS = -1 +BDB = $(obj)/bdb.bin + +# Calculate bootblock.raw.bin's size and offset +.PHONY: bootblock_offset +bootblock_offset: $(objcbfs)/bootblock.raw.bin + $(eval BOOTBLOCK_SIZE = $(call file-size, $<)) + $(eval BOOTBLOCK_OFFSET = $(call int-subtract, \ + $(BOOTBLOCK_REGION_SIZE) $(BOOTBLOCK_SIZE))) + +# Create a BDB. The followings are needed: +# - Hash of bootblock.raw.bin +# - Offset, type, partition, load address of bootblock.raw.bin +# - a BDB key pair +# - a data key pair +# - futility (from vboot_reference) +$(BDB): $(objcbfs)/bootblock.raw.bin $(FUTILITY) bootblock_offset + $(FUTILITY) bdb --create $@.tmp \ + --bdbkey_pri $(KEYDIR)/bdbkey.pem \ + --bdbkey_pub $(KEYDIR)/bdbkey.keyb \ + --datakey_pri $(KEYDIR)/datakey.pem \ + --datakey_pub $(KEYDIR)/datakey.keyb + $(FUTILITY) bdb --add $@.tmp \ + --data $< \ + --offset $(BOOTBLOCK_OFFSET) \ + --partition -1 \ + --type -1 \ + --load_address $(BOOTBLOCK_LOAD_ADDRESS) + $(FUTILITY) bdb --resign $@.tmp \ + --datakey_pri $(KEYDIR)/datakey.pem + $(FUTILITY) bdb --verify $@.tmp \ + --key_digest $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin + mv $@.tmp $@ + +# Overrides generic pattern rule *.raw.bin -> *.bin for bootblock.bin +# +# bootblock.bin is structured as follows: +# +------------------+ +# | BDB | +# +------------------+ +# | 000............0 | +# +------------------+ +# |bootblock.raw.bin | +# +------------------+ +# And this will be placed in BOOTBLOCK region. +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BDB) bootblock_offset + dd if=/dev/zero bs=1 count=$(BOOTBLOCK_REGION_SIZE) of=$@.tmp + dd if=$(BDB) bs=1 count=$(call file-size, $(BDB)) conv=notrunc of=$@.tmp + dd if=$(objcbfs)/bootblock.raw.bin bs=1 count=$(BOOTBLOCK_SIZE) \ + seek=$(BOOTBLOCK_OFFSET) conv=notrunc of=$@.tmp + mv $@.tmp $@ + +endif \ No newline at end of file

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New patch to review for coreboot: mvmap2315: Skip uart_init when serial is disabled
by Daisuke Nojiri 26 Sep '16

26 Sep '16

Daisuke Nojiri (dnojiri(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16746 -gerrit commit 2174be47093eb472494fa5007b84f4f65241b134 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Sep 26 10:46:53 2016 -0700 mvmap2315: Skip uart_init when serial is disabled When coreboot is built with CONFIG_CONSOLE_SERIAL not set, uart_init does not exist, causing compilation to fail. This patch fixes it by skipping uart_init when serial is disabled. BUG=none BRANCH=none TEST=emerge-rotor coreboot Change-Id: If7f475eae9008b392f8f1e5cb5568c93113ee3f1 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/soc/marvell/mvmap2315/bootblock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 6b0a333..4a9ea08 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -94,8 +94,10 @@ void bootblock_soc_init(void) ap_start((void *)MVMAP2315_ROMSTAGE_BASE); /* initializing UART1 to free UART0 to be used by romstage */ +#if __CONSOLE_SERIAL_ENABLE__ uart_num = 1; uart_init(uart_num); +#endif while (read32((void *)MVMAP2315_BOOTBLOCK_CB1) != 0x4) ;

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Patch merged into coreboot/master: crossgcc: Add Dockerfile
by gerrit＠coreboot.org 26 Sep '16

26 Sep '16

the following patch was just integrated into master: commit fe222005b813975d7370fd8c91a10fc46e4f9c93 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Sep 18 20:11:15 2016 +0200 crossgcc: Add Dockerfile The dockerfile allows building an image with the current tree's crossgcc code. Change-Id: I59cd85b0acdf8776e3e090742d7f5d89d1c154e7 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: https://review.coreboot.org/16636 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16636 for details. -gerrit

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Patch merged into coreboot/master: payloads/external/Memtest86Plus: Update stable to latest commit
by gerrit＠coreboot.org 26 Sep '16

26 Sep '16

the following patch was just integrated into master: commit 89189685570d33958aa27764614ab92f39b7c844 Author: Martin Roth <martinroth(a)google.com> Date: Wed Sep 14 17:52:15 2016 -0700 payloads/external/Memtest86Plus: Update stable to latest commit This brings in two additional changes: - Use OBJCOPY if available. - Fix strstr() indent and rewrite to not call strlen() on each char. Change-Id: Id13dfda28c545332fce8282e849f379bf50629b9 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16605 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16605 for details. -gerrit

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coreboot-gerrit September 2016