coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard/broadcom/blast: Use tabs for indents
by HAOUAS Elyes 26 Sep '16

26 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16745 -gerrit commit 39e26a21b0c72ff9396ac34bbac4f991f5699ce5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Sep 26 21:11:58 2016 +0200 mainboard/broadcom/blast: Use tabs for indents Change-Id: I61bef70ec572c12518cd3763a6a860e56bfdb716 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/broadcom/blast/romstage.c | 48 ++++++++++++++++----------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index e687c2e..33d939a 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -28,13 +28,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x71 - unsigned device=(ctrl->channel0[0])>>8; - smbus_send_byte(SMBUS_HUB, device); + unsigned device=(ctrl->channel0[0])>>8; + smbus_send_byte(SMBUS_HUB, device); } static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } #include "northbridge/amd/amdk8/raminit.c" @@ -52,52 +52,52 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, - RC1|DIMM0, RC1|DIMM2, 0, 0, - RC1|DIMM1, RC1|DIMM3, 0, 0, + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, + RC1|DIMM0, RC1|DIMM2, 0, 0, + RC1|DIMM1, RC1|DIMM3, 0, 0, }; - int needs_reset; + int needs_reset; unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + struct mem_controller ctrl[8]; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ - } + } - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - setup_blast_resource_map(); + setup_blast_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - wait_all_core0_started(); - start_other_cores(); + // It is said that we should start core1 after all core0 launched + wait_all_core0_started(); + start_other_cores(); #endif - wait_all_aps_started(bsp_apicid); + wait_all_aps_started(bsp_apicid); - needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x(); bcm5785_early_setup(); @@ -108,9 +108,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) allow_all_aps_stop(bsp_apicid); - nodes = get_nodes(); - //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); @@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(nodes, ctrl); #if 0 - print_pci_devices(); + print_pci_devices(); dump_pci_devices(); #endif

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New patch to review for coreboot: mainboard/broadcom/blast: Use tabs for indents
by HAOUAS Elyes 26 Sep '16

26 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16745 -gerrit commit 2291c88b46381edede5b284f403d5b931aaf6c5c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Sep 26 21:11:58 2016 +0200 mainboard/broadcom/blast: Use tabs for indents Change-Id: I61bef70ec572c12518cd3763a6a860e56bfdb716 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/broadcom/blast/romstage.c | 48 ++++++++++++++++----------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index e687c2e..fe02f08 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -28,13 +28,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x71 - unsigned device=(ctrl->channel0[0])>>8; - smbus_send_byte(SMBUS_HUB, device); + unsigned device=(ctrl->channel0[0])>>8; + smbus_send_byte(SMBUS_HUB, device); } static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } #include "northbridge/amd/amdk8/raminit.c" @@ -52,52 +52,52 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, - RC1|DIMM0, RC1|DIMM2, 0, 0, - RC1|DIMM1, RC1|DIMM3, 0, 0, + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, + RC1|DIMM0, RC1|DIMM2, 0, 0, + RC1|DIMM1, RC1|DIMM3, 0, 0, }; - int needs_reset; + int needs_reset; unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + struct mem_controller ctrl[8]; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ - } + } - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - setup_blast_resource_map(); + setup_blast_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - wait_all_core0_started(); - start_other_cores(); + // It is said that we should start core1 after all core0 launched + wait_all_core0_started(); + start_other_cores(); #endif - wait_all_aps_started(bsp_apicid); + wait_all_aps_started(bsp_apicid); - needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x(); bcm5785_early_setup(); @@ -108,9 +108,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) allow_all_aps_stop(bsp_apicid); - nodes = get_nodes(); - //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); @@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(nodes, ctrl); #if 0 - print_pci_devices(); + print_pci_devices(); dump_pci_devices(); #endif

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New patch to review for coreboot: mainboard/digitallogic/msm800sev: Use tabs for indents
by HAOUAS Elyes 26 Sep '16

26 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16744 -gerrit commit 7b65219556e3de3ca9f4ceeba07baf75653afc01 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Sep 26 21:05:10 2016 +0200 mainboard/digitallogic/msm800sev: Use tabs for indents Change-Id: Iaa67db6e08a4465608d81b176d6fa7b6ccc195ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/digitallogic/msm800sev/devicetree.cb | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index db511e5..b03d4c5 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -1,8 +1,8 @@ chip northbridge/amd/lx - device domain 0 on - device pci 1.0 on end + device domain 0 on + device pci 1.0 on end device pci 1.1 on end - chip southbridge/amd/cs5536 + chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK @@ -25,7 +25,7 @@ chip northbridge/amd/lx register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge + device pci f.0 on # ISA Bridge chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 @@ -69,10 +69,10 @@ chip northbridge/amd/lx end device pci f.1 on end # Flash controller device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI + device pci f.3 on end # Audio + device pci f.4 on end # OHCI device pci f.5 on end # EHCI - end + end end # APIC cluster is late CPU init.

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New patch to review for coreboot: google/reef: Mark touchpad and touchscreen as probed devices
by Duncan Laurie 26 Sep '16

26 Sep '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16743 -gerrit commit 5437dacdeaa1deb366a150da1e5fecc5174939e4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 26 10:33:51 2016 -0700 google/reef: Mark touchpad and touchscreen as probed devices Add the 'probed' flag to the touchpad and touchscreen devices so they are probed by the kernel before being loaded, in case they do not exist or are replaced with another vendor. BUG=chrome-os-partner:57686 Change-Id: I0a61964e6874cd99fab0c21fa404a43548fc8ab5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index f1ce8c5..087f858 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -135,6 +135,7 @@ chip soc/intel/apollolake register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" device i2c 10 on end end end # - I2C 3 @@ -144,6 +145,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" register "wake" = "GPE0_DW1_15" + register "probed" = "1" device i2c 15 on end end end # - I2C 4

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New patch to review for coreboot: drivers/i2c/generic: Add config for marking device as probed
by Duncan Laurie 26 Sep '16

26 Sep '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16742 -gerrit commit 01a142857b11c4aadb837096f0b213b3764765f7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Sep 26 10:31:22 2016 -0700 drivers/i2c/generic: Add config for marking device as probed Add a config option to the generic I2C device driver to indicate to the OS that this device should be probed before being added. This can be used to provide ACPI device instantiations to devices that may not actually exist on the board. For example, if multiple trackpad vendors are supported on the same board they can both be described in ACPI and the OS will probe the address and load the driver only if the device responds to the probe at that address. BUG=chrome-os-partner:57686 Change-Id: I22cffb4b15f25d97dfd37dc58bca315f57bafc59 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 9 +++++++++ src/drivers/i2c/generic/generic.c | 7 +++++++ 2 files changed, 16 insertions(+) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index 84657d5..d84097f 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -10,6 +10,15 @@ struct drivers_i2c_generic_config { unsigned wake; /* Wake GPE */ struct acpi_irq irq; /* Interrupt */ + /* + * This flag will add a device propery which will indicate + * to the OS that it should probe this device before adding it. + * + * This can be used to declare a device that may not exist on + * the board, for example to support multiple trackpad vendors. + */ + int probed; + /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 62e2e9a..30a280b 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -35,6 +35,7 @@ static void i2c_generic_fill_ssdt(struct device *dev) .speed = config->speed ? : I2C_SPEED_FAST, .resource = scope, }; + struct acpi_dp *dsd = NULL; if (!dev->enabled || !scope) return; @@ -65,6 +66,12 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_PRW(config->wake, 3); } + if (config->probed) { + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dsd, "linux,probed", 1); + acpi_dp_write(dsd); + } + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

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Patch set updated for coreboot: x86: acpi: Use GOOG ID for coreboot table
by Duncan Laurie 26 Sep '16

26 Sep '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16724 -gerrit commit 84d62d5e3ea8c1925fc34cd84606c34a893c378b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Sep 22 14:08:33 2016 -0700 x86: acpi: Use GOOG ID for coreboot table Use the GOOG ACPI ID until there is an official ID allocation for coreboot. Since I administer this range I allocated 0xCB00-0xCBFF for coreboot use. Change-Id: I38ac0a0267e21f7282c89ef19e8bb72339f13846 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/acpigen.c | 2 +- src/arch/x86/include/arch/acpi.h | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index c55611b..2d626ab 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -224,7 +224,7 @@ void acpigen_write_coreboot_hid(enum coreboot_acpi_ids id) { char hid[9]; /* CORExxxx */ - snprintf(hid, sizeof(hid), "%.4s%04u", COREBOOT_ACPI_ID, id); + snprintf(hid, sizeof(hid), "%.4s%04X", COREBOOT_ACPI_ID, id); acpigen_write_name_string("_HID", hid); } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7d29931..7fc1c50 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -57,11 +57,14 @@ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "CORE " /* Must be exactly 6 bytes long! */ #define ASLC "CORE" /* Must be exactly 4 bytes long! */ -#define COREBOOT_ACPI_ID "CORE" /* ACPI ID for coreboot HIDs */ + +/* Use GOOGCBxx range until coreboot ID is official */ +#define COREBOOT_ACPI_ID "GOOG" /* ACPI ID for coreboot HIDs */ /* List of ACPI HID that use the coreboot ACPI ID */ enum coreboot_acpi_ids { - COREBOOT_ACPI_ID_CBTABLE, /* CORE0000 */ + COREBOOT_ACPI_ID_CBTABLE = 0xCB00, /* GOOGCB00 */ + COREBOOT_ACPI_ID_MAX = 0xCBFF, /* GOOGCBFF */ }; /* RSDP (Root System Description Pointer) */

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Patch set updated for coreboot: i945/gma.c: Generate fake VBT
by Arthur Heymans 26 Sep '16

26 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16530 -gerrit commit 2b84b53158515fb86583e1d20a051919fe97941c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Sep 7 22:10:57 2016 +0200 i945/gma.c: Generate fake VBT This generates a fake VBT for the Intel i945 graphic device. i945 supports both the mobile chipset 945gm (calistoga) and the desktop chipset 945gc (lakeport), which is why a VBT with a different id string needs to be created for each target. The VBT id string is obtained from the vbios blob in the following way: "strings vbios.bin | grep VBT". Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 17e0d70..0f829f1 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -623,6 +623,15 @@ static void gma_func0_init(struct device *dev) iobase, mmiobase, graphics_base); if (err == 0) gfx_set_init_done(1); + /* Linux relies on VBT for panel info. */ + if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { + generate_fake_intel_oprom(&conf->gfx, dev, + "$VBT CALISTOGA"); + } + if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { + generate_fake_intel_oprom(&conf->gfx, dev, + "$VBT LAKEPORT-G"); + } #endif }

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Patch set updated for coreboot: superio: Add back Nuvoton NCT6776 support from https://review.coreboot.org/#/c/12241 by Felix Held
by Boon Tiong Teo 26 Sep '16

26 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16519 -gerrit commit 19ed144a9522c403547c2e45671c643b4475b3e1 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Mon Sep 5 16:00:07 2016 +0800 superio: Add back Nuvoton NCT6776 support from https://review.coreboot.org/#/c/12241 by Felix Held Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/common/early_serial.c | 3 + src/superio/nuvoton/nct6776/Kconfig | 23 +++++++ src/superio/nuvoton/nct6776/Makefile.inc | 18 ++++++ src/superio/nuvoton/nct6776/nct6776.h | 58 ++++++++++++++++++ src/superio/nuvoton/nct6776/superio.c | 99 +++++++++++++++++++++++++++++++ 6 files changed, 202 insertions(+) diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 94cc6b7..e2e178b 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -19,5 +19,6 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index fca5ed6..d1958a0 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -63,6 +63,9 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); + if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A)) + /* Route GPIO8 pin group to COM A */ + pnp_write_config(dev, 0x2a, 0x40); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); diff --git a/src/superio/nuvoton/nct6776/Kconfig b/src/superio/nuvoton/nct6776/Kconfig new file mode 100644 index 0000000..cf0fe21 --- /dev/null +++ b/src/superio/nuvoton/nct6776/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_NUVOTON_NCT6776 + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT6776_COM_A + bool + default n diff --git a/src/superio/nuvoton/nct6776/Makefile.inc b/src/superio/nuvoton/nct6776/Makefile.inc new file mode 100644 index 0000000..13fe527 --- /dev/null +++ b/src/superio/nuvoton/nct6776/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += superio.c diff --git a/src/superio/nuvoton/nct6776/nct6776.h b/src/superio/nuvoton/nct6776/nct6776.h new file mode 100644 index 0000000..520401e --- /dev/null +++ b/src/superio/nuvoton/nct6776/nct6776.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +#ifndef SUPERIO_NUVOTON_NCT6776_H +#define SUPERIO_NUVOTON_NCT6776_H + +/* Logical Device Numbers (LDN). */ +#define NCT6776_FDC 0x00 /* Floppy */ +#define NCT6776_PP 0x01 /* Parallel port */ +#define NCT6776_SP1 0x02 /* Com1 */ +#define NCT6776_SP2 0x03 /* Com2 & IR */ +#define NCT6776_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT6776_CIR 0x06 +#define NCT6776_GPIO6789_V 0x07 +#define NCT6776_WDT1_GPIO01A_V 0x08 +#define NCT6776_GPIO1234567_V 0x09 +#define NCT6776_ACPI 0x0A +#define NCT6776_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT6776_VID 0x0D +#define NCT6776_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT6776_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT6776_SVID 0x14 +#define NCT6776_DSLP 0x16 /* Deep sleep */ +#define NCT6776_GPIOA_LDN 0x17 + +/* virtual LDN for GPIO and WDT */ +#define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V) + +#define NCT6776_GPIOBASE ((0 << 8) | NCT6776_WDT1_GPIO01A_V) //? + +#define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V) +#define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO2 ((2 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO3 ((3 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO4 ((4 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO5 ((5 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO6 ((6 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO7 ((7 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO8 ((0 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIO9 ((1 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIOA ((2 << 8) | NCT6776_WDT1_GPIO01A_V) + +#endif /* SUPERIO_NUVOTON_NCT6776_H */ diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c new file mode 100644 index 0000000..85f52cf --- /dev/null +++ b/src/superio/nuvoton/nct6776/superio.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct6776.h" + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +static void nct6776_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case NCT6776_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6776_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_SP1, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_SP2, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, NCT6776_CIR, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_ACPI}, + { &ops, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + {0x0ffe, 0}, {0x0ffe, 4}, }, + { &ops, NCT6776_VID}, + { &ops, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO_PP_OD}, + { &ops, NCT6776_SVID}, + { &ops, NCT6776_DSLP}, + { &ops, NCT6776_GPIOA_LDN}, + { &ops, NCT6776_WDT1}, + { &ops, NCT6776_GPIOBASE, PNP_IO0, + {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO0}, + { &ops, NCT6776_GPIO1}, + { &ops, NCT6776_GPIO2}, + { &ops, NCT6776_GPIO3}, + { &ops, NCT6776_GPIO4}, + { &ops, NCT6776_GPIO5}, + { &ops, NCT6776_GPIO6}, + { &ops, NCT6776_GPIO7}, + { &ops, NCT6776_GPIO8}, + { &ops, NCT6776_GPIO9}, + { &ops, NCT6776_GPIOA}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6776_ops = { + CHIP_NAME("NUVOTON NCT6776 Super I/O") + .enable_dev = enable_dev, +};

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Patch set updated for coreboot: nb/intel/*/gma.c: remove spaces at the fake vbt generation
by Arthur Heymans 26 Sep '16

26 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16740 -gerrit commit aba4e7021ad18613a58fec457c58a6501c9c9c71 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Sep 25 22:48:00 2016 +0200 nb/intel/*/gma.c: remove spaces at the fake vbt generation Padding the VBT id string is now done automatically. Change-Id: I8f9baf7b1585026bc29b82d07e451aa11e284ffb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 3 +-- src/northbridge/intel/pineview/gma.c | 3 +-- src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 2 +- src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c | 2 +- src/northbridge/intel/x4x/gma.c | 2 +- 5 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 14f695e..0545ba5 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -740,8 +740,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, - "$VBT CANTIGA "); + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA"); } } diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 335e38a..d670198 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -277,8 +277,7 @@ static void gma_func0_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, - "$VBT PINEVIEW "); + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW"); } } diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index f6818dd..831e8ce 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -524,7 +524,7 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info, /* Linux relies on VBT for panel info. */ generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), - "$VBT SNB/IVB-MOBILE "); + "$VBT SNB/IVB-MOBILE"); return 1; } diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 3b4b64c..c2c8087 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -479,7 +479,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, /* Linux relies on VBT for panel info. */ generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), - "$VBT SNB/IVB-MOBILE "); + "$VBT SNB/IVB-MOBILE"); return 1; } diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 2679026..a98a1dc 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -177,7 +177,7 @@ static void native_init(struct device *dev) } /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE "); + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE"); } static void gma_func0_init(struct device *dev)

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Patch set updated for coreboot: intel/gma/vbt.c: pad the ID string with spaces.
by Arthur Heymans 26 Sep '16

26 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16739 -gerrit commit 5d2e40b4645afa613f9d71a0224aaeaf4c5e9b3a Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Sep 25 22:36:26 2016 +0200 intel/gma/vbt.c: pad the ID string with spaces. The VBT id string is 20 characters long. If the string is shorter than 20 it needs spaces at the end. This change is cosmetic as all strings were padded by hand. Change-Id: Id6439f1d3dbd09319ee99ce9d15dbc3bcead1f53 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/intel/gma/vbt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index e768402..9ec09d3 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -34,7 +34,9 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *conf, memset (head, 0, sizeof (*head)); - memcpy (head->signature, idstr, 20); + memset(head->signature, ' ', sizeof(head->signature)); + memcpy(head->signature, idstr, MIN(strlen(idstr), + sizeof(head->signature))); head->version = 100; head->header_size = sizeof (*head); head->bdb_offset = sizeof (*head);

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coreboot-gerrit September 2016