coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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1340 discussions

Patch merged into coreboot/master: mainboard/msi/ms9185/mb_sysconf.h: Use tabs for indents
by gerrit＠coreboot.org 27 Sep '16

27 Sep '16

the following patch was just integrated into master: commit bf97ca42cd0d6a7e5c27aed568d7f05b2de5184a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Sep 25 15:36:55 2016 +0200 mainboard/msi/ms9185/mb_sysconf.h: Use tabs for indents Change-Id: Ib2ab95b26c3bb1cbd58aafb1fafd1b285d6a5ba8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16738 for details. -gerrit

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Patch merged into coreboot/master: i945/gma.c: Generate fake VBT
by gerrit＠coreboot.org 27 Sep '16

27 Sep '16

the following patch was just integrated into master: commit 333176e5d3b77da6e49a1ddd868a180e6d878e20 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Sep 7 22:10:57 2016 +0200 i945/gma.c: Generate fake VBT This generates a fake VBT for the Intel i945 graphic device. i945 supports both the mobile chipset 945gm (calistoga) and the desktop chipset 945gc (lakeport), which is why a VBT with a different id string needs to be created for each target. The VBT id string is obtained from the vbios blob in the following way: "strings vbios.bin | grep VBT". Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/16530 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/16530 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/*/gma.c: remove spaces at the fake vbt generation
by gerrit＠coreboot.org 27 Sep '16

27 Sep '16

the following patch was just integrated into master: commit d3284a69772c84c7d9ff7f486837fd970a4ea717 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Sep 25 22:48:00 2016 +0200 nb/intel/*/gma.c: remove spaces at the fake vbt generation Padding the VBT id string is now done automatically. Change-Id: I8f9baf7b1585026bc29b82d07e451aa11e284ffb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/16740 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/16740 for details. -gerrit

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Patch merged into coreboot/master: intel/gma/vbt.c: pad the ID string with spaces.
by gerrit＠coreboot.org 27 Sep '16

27 Sep '16

the following patch was just integrated into master: commit 2e77e0aa3fa9d2fd7b65f19c6fcabcbcfba7be2d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Sep 25 22:36:26 2016 +0200 intel/gma/vbt.c: pad the ID string with spaces. The VBT id string is 20 characters long. If the string is shorter than 20 it needs spaces at the end. This change is cosmetic as all strings were padded by hand. Change-Id: Id6439f1d3dbd09319ee99ce9d15dbc3bcead1f53 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/16739 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/16739 for details. -gerrit

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New patch to review for coreboot: mainboard/google/reef: Update DPTF policy temp. values for CPU
by Sumeet R Pawnikar 27 Sep '16

27 Sep '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16766 -gerrit commit f07c220471b51942de267c59a7eb57347ba4c870 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Sep 27 11:55:24 2016 +0530 mainboard/google/reef: Update DPTF policy temp. values for CPU This patch updates the CPU specific passive temp. trip point and critical temp. trip point value for DPTF policy. BUG=chrome-os-partner:57903 TEST=Built, booted on reef and verifed this passive and critical temp. trip points with heavy workload. Change-Id: I2a38d01a6539c1bd478f8716c4b543ebcd1f2080 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- .../google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl index 8c18687..43e2e93 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 80 #define DPTF_CPU_ACTIVE_AC2 70

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Patch set updated for coreboot: src/mainboard/intel: Added basic Skylake Saddle Brook board support
by Boon Tiong Teo 27 Sep '16

27 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16608 -gerrit commit 771b9445f7fc9e13e4b26c614a76fc8843423963 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Sep 15 11:49:04 2016 +0800 src/mainboard/intel: Added basic Skylake Saddle Brook board support Change-Id: I95c752922a74369cb8ae77be6cb886e4597814e4 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/mainboard/intel/sklsdlbrk/Kconfig | 45 ++++++++ src/mainboard/intel/sklsdlbrk/Kconfig.name | 2 + src/mainboard/intel/sklsdlbrk/acpi/ec.asl | 14 +++ src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl | 26 +++++ src/mainboard/intel/sklsdlbrk/acpi/superio.asl | 14 +++ src/mainboard/intel/sklsdlbrk/acpi_tables.c | 15 +++ src/mainboard/intel/sklsdlbrk/board_info.txt | 6 + src/mainboard/intel/sklsdlbrk/cmos.layout | 135 +++++++++++++++++++++++ src/mainboard/intel/sklsdlbrk/devicetree.cb | 112 +++++++++++++++++++ src/mainboard/intel/sklsdlbrk/dsdt.asl | 49 ++++++++ src/mainboard/intel/sklsdlbrk/fadt.c | 47 ++++++++ src/mainboard/intel/sklsdlbrk/onboard.h | 19 ++++ src/mainboard/intel/sklsdlbrk/romstage.c | 87 +++++++++++++++ 13 files changed, 571 insertions(+) diff --git a/src/mainboard/intel/sklsdlbrk/Kconfig b/src/mainboard/intel/sklsdlbrk/Kconfig new file mode 100644 index 0000000..656d165 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_SKLSDLBRK + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select MMCONF_SUPPORT + select MONOTONIC_TIMER_MSR + select PCIEXP_L1_SUB_STATE + select SOC_INTEL_SKYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select CONSOLE_SERIAL + select DRIVERS_UART + + +config IRQ_SLOT_COUNT + int + default 18 + +config BOOT_MEDIA_SPI_BUS + int + default 0 + +config MAINBOARD_DIR + string + default "intel/sklsdlbrk" + +config MAINBOARD_PART_NUMBER + string + default "Skylake Saddle Brook" + +config MAX_CPUS + int + default 8 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +endif diff --git a/src/mainboard/intel/sklsdlbrk/Kconfig.name b/src/mainboard/intel/sklsdlbrk/Kconfig.name new file mode 100644 index 0000000..c85fb81 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SKLSDLBRK + bool "Skylake Saddle Brook" diff --git a/src/mainboard/intel/sklsdlbrk/acpi/ec.asl b/src/mainboard/intel/sklsdlbrk/acpi/ec.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl b/src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl new file mode 100644 index 0000000..ddccc21 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> +#include <mainboard/intel/sklsdlbrk/onboard.h> + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} \ No newline at end of file diff --git a/src/mainboard/intel/sklsdlbrk/acpi/superio.asl b/src/mainboard/intel/sklsdlbrk/acpi/superio.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/sklsdlbrk/acpi_tables.c b/src/mainboard/intel/sklsdlbrk/acpi_tables.c new file mode 100644 index 0000000..ccf9f74 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/acpi_tables.c @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/sklsdlbrk/board_info.txt b/src/mainboard/intel/sklsdlbrk/board_info.txt new file mode 100644 index 0000000..5b33adf --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Saddle Brook Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/sklsdlbrk/cmos.layout b/src/mainboard/intel/sklsdlbrk/cmos.layout new file mode 100644 index 0000000..8467747 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/sklsdlbrk/devicetree.cb b/src/mainboard/intel/sklsdlbrk/devicetree.cb new file mode 100644 index 0000000..bd2a552 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/devicetree.cb @@ -0,0 +1,112 @@ +chip soc/intel/skylake + + # SerialIO device modes + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoPci, \ + }" + + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # Enable S0ix + register "s0ix_enable" = "0" + + # Probeless Trace function + register "ProbelessTrace" = "0" + + # I/O Buffer Ownership: + # 0: HD-A Link + # 1 Shared, HD-A Link and I2S Port + # 3: I2S Ports + register "IoBufferOwnership" = "3" + + # Audio related + register "DspEnable" = "0" + + # USB related + register "SsicPortEnable" = "0" + + # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "2" + + # Integrated Sensor + register "IshEnable" = "0" + + # XDCI controller + register "XdciEnable" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT-Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 off end # PCI Express Port 17 + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on end # LPC Interface (eSPI Enable Strap = 0) eSPI Interface (eSPI Enable Strap = 1) + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus Controller + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/intel/sklsdlbrk/dsdt.asl b/src/mainboard/intel/sklsdlbrk/dsdt.asl new file mode 100644 index 0000000..4134867 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/sklsdlbrk/fadt.c b/src/mainboard/intel/sklsdlbrk/fadt.c new file mode 100644 index 0000000..05fea01 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/fadt.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/sklsdlbrk/onboard.h b/src/mainboard/intel/sklsdlbrk/onboard.h new file mode 100644 index 0000000..f902542 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/onboard.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#endif diff --git a/src/mainboard/intel/sklsdlbrk/romstage.c b/src/mainboard/intel/sklsdlbrk/romstage.c new file mode 100644 index 0000000..5671357 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/romstage.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <soc/cpu.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +void car_mainboard_pre_console_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_romstage_entry(struct romstage_params *params) +{ + post_code(0x31); + /* Fill out PEI DATA */ + mainboard_fill_pei_data(params->pei_data); + mainboard_fill_spd_data(params->pei_data); + /* Initliaze memory */ + romstage_common(params); +} + +void mainboard_memory_init_params( + struct romstage_params *params, + MEMORY_INIT_UPD *mupd) +{ + /* Get SPD data passing strucutre and initialize it.*/ + if (params->pei_data->spd_data[0][0][0] != 0) { + mupd->MemorySpdPtr00 = + (UINT32)(params->pei_data->spd_data[0][0]); + mupd->MemorySpdPtr10 = + (UINT32)(params->pei_data->spd_data[1][0]); + } + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", + mupd->MemorySpdPtr00); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", + mupd->MemorySpdPtr01); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", + mupd->MemorySpdPtr10); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", + mupd->MemorySpdPtr11); + + /* + * Configure the DQ/DQS settings if required. In general the settings + * should be set in the FSP flash image and should not need to be + * changed. + */ + memcpy(mupd->DqByteMapCh0, params->pei_data->dq_map[0], + sizeof(params->pei_data->dq_map[0])); + memcpy(mupd->DqByteMapCh1, params->pei_data->dq_map[1], + sizeof(params->pei_data->dq_map[1])); + memcpy(mupd->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], + sizeof(params->pei_data->dqs_map[0])); + memcpy(mupd->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], + sizeof(params->pei_data->dqs_map[1])); + memcpy(mupd->RcompResistor, params->pei_data->RcompResistor, + sizeof(params->pei_data->RcompResistor)); + memcpy(mupd->RcompTarget, params->pei_data->RcompTarget, + sizeof(params->pei_data->RcompTarget)); + + mupd->DqPinsInterleaved = TRUE; +}

1 0

Patch set updated for coreboot: src/soc/intel/skylake: Added config option for Skylake-H Sku support
by Boon Tiong Teo 27 Sep '16

27 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16607 -gerrit commit 06431385c1957de66158b0d42ebe21d7b176119c Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Sep 15 11:11:45 2016 +0800 src/soc/intel/skylake: Added config option for Skylake-H Sku support Change-Id: Ia9c1c065f20bf2b37afc7485ef8df3abd35e2f14 --- src/soc/intel/skylake/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index edf5db3..c44d73f 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -169,6 +169,12 @@ config UART_DEBUG select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO +config SKYLAKE_SOC_PCH_H + bool + default n + help + Choose this option if you have a PCH-H chipset. + config CHIPSET_BOOTBLOCK_INCLUDE string default "soc/intel/skylake/bootblock/timestamp.inc"

1 0

Patch set updated for coreboot: src/mainboard/intel: Added basic Skylake Saddle Brook board support
by Boon Tiong Teo 27 Sep '16

27 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16608 -gerrit commit 56ef3761703294f90b90776c90b61ce738f9bd94 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Sep 15 11:49:04 2016 +0800 src/mainboard/intel: Added basic Skylake Saddle Brook board support Change-Id: I95c752922a74369cb8ae77be6cb886e4597814e4 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/mainboard/intel/sklsdlbrk/Kconfig | 45 ++++++++ src/mainboard/intel/sklsdlbrk/Kconfig.name | 2 + src/mainboard/intel/sklsdlbrk/acpi/ec.asl | 14 +++ src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl | 26 +++++ src/mainboard/intel/sklsdlbrk/acpi/superio.asl | 14 +++ src/mainboard/intel/sklsdlbrk/acpi_tables.c | 15 +++ src/mainboard/intel/sklsdlbrk/cmos.layout | 135 +++++++++++++++++++++++ src/mainboard/intel/sklsdlbrk/devicetree.cb | 112 +++++++++++++++++++ src/mainboard/intel/sklsdlbrk/dsdt.asl | 49 ++++++++ src/mainboard/intel/sklsdlbrk/fadt.c | 47 ++++++++ src/mainboard/intel/sklsdlbrk/onboard.h | 19 ++++ src/mainboard/intel/sklsdlbrk/romstage.c | 87 +++++++++++++++ 12 files changed, 565 insertions(+) diff --git a/src/mainboard/intel/sklsdlbrk/Kconfig b/src/mainboard/intel/sklsdlbrk/Kconfig new file mode 100644 index 0000000..656d165 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_SKLSDLBRK + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select MMCONF_SUPPORT + select MONOTONIC_TIMER_MSR + select PCIEXP_L1_SUB_STATE + select SOC_INTEL_SKYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select CONSOLE_SERIAL + select DRIVERS_UART + + +config IRQ_SLOT_COUNT + int + default 18 + +config BOOT_MEDIA_SPI_BUS + int + default 0 + +config MAINBOARD_DIR + string + default "intel/sklsdlbrk" + +config MAINBOARD_PART_NUMBER + string + default "Skylake Saddle Brook" + +config MAX_CPUS + int + default 8 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +endif diff --git a/src/mainboard/intel/sklsdlbrk/Kconfig.name b/src/mainboard/intel/sklsdlbrk/Kconfig.name new file mode 100644 index 0000000..c85fb81 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SKLSDLBRK + bool "Skylake Saddle Brook" diff --git a/src/mainboard/intel/sklsdlbrk/acpi/ec.asl b/src/mainboard/intel/sklsdlbrk/acpi/ec.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl b/src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl new file mode 100644 index 0000000..ddccc21 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> +#include <mainboard/intel/sklsdlbrk/onboard.h> + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} \ No newline at end of file diff --git a/src/mainboard/intel/sklsdlbrk/acpi/superio.asl b/src/mainboard/intel/sklsdlbrk/acpi/superio.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/sklsdlbrk/acpi_tables.c b/src/mainboard/intel/sklsdlbrk/acpi_tables.c new file mode 100644 index 0000000..ccf9f74 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/acpi_tables.c @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/sklsdlbrk/cmos.layout b/src/mainboard/intel/sklsdlbrk/cmos.layout new file mode 100644 index 0000000..8467747 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/sklsdlbrk/devicetree.cb b/src/mainboard/intel/sklsdlbrk/devicetree.cb new file mode 100644 index 0000000..bd2a552 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/devicetree.cb @@ -0,0 +1,112 @@ +chip soc/intel/skylake + + # SerialIO device modes + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoPci, \ + }" + + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # Enable S0ix + register "s0ix_enable" = "0" + + # Probeless Trace function + register "ProbelessTrace" = "0" + + # I/O Buffer Ownership: + # 0: HD-A Link + # 1 Shared, HD-A Link and I2S Port + # 3: I2S Ports + register "IoBufferOwnership" = "3" + + # Audio related + register "DspEnable" = "0" + + # USB related + register "SsicPortEnable" = "0" + + # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "2" + + # Integrated Sensor + register "IshEnable" = "0" + + # XDCI controller + register "XdciEnable" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT-Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 off end # PCI Express Port 17 + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on end # LPC Interface (eSPI Enable Strap = 0) eSPI Interface (eSPI Enable Strap = 1) + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus Controller + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/intel/sklsdlbrk/dsdt.asl b/src/mainboard/intel/sklsdlbrk/dsdt.asl new file mode 100644 index 0000000..4134867 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/sklsdlbrk/fadt.c b/src/mainboard/intel/sklsdlbrk/fadt.c new file mode 100644 index 0000000..05fea01 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/fadt.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/sklsdlbrk/onboard.h b/src/mainboard/intel/sklsdlbrk/onboard.h new file mode 100644 index 0000000..f902542 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/onboard.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#endif diff --git a/src/mainboard/intel/sklsdlbrk/romstage.c b/src/mainboard/intel/sklsdlbrk/romstage.c new file mode 100644 index 0000000..5671357 --- /dev/null +++ b/src/mainboard/intel/sklsdlbrk/romstage.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <soc/cpu.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +void car_mainboard_pre_console_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_romstage_entry(struct romstage_params *params) +{ + post_code(0x31); + /* Fill out PEI DATA */ + mainboard_fill_pei_data(params->pei_data); + mainboard_fill_spd_data(params->pei_data); + /* Initliaze memory */ + romstage_common(params); +} + +void mainboard_memory_init_params( + struct romstage_params *params, + MEMORY_INIT_UPD *mupd) +{ + /* Get SPD data passing strucutre and initialize it.*/ + if (params->pei_data->spd_data[0][0][0] != 0) { + mupd->MemorySpdPtr00 = + (UINT32)(params->pei_data->spd_data[0][0]); + mupd->MemorySpdPtr10 = + (UINT32)(params->pei_data->spd_data[1][0]); + } + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", + mupd->MemorySpdPtr00); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", + mupd->MemorySpdPtr01); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", + mupd->MemorySpdPtr10); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", + mupd->MemorySpdPtr11); + + /* + * Configure the DQ/DQS settings if required. In general the settings + * should be set in the FSP flash image and should not need to be + * changed. + */ + memcpy(mupd->DqByteMapCh0, params->pei_data->dq_map[0], + sizeof(params->pei_data->dq_map[0])); + memcpy(mupd->DqByteMapCh1, params->pei_data->dq_map[1], + sizeof(params->pei_data->dq_map[1])); + memcpy(mupd->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], + sizeof(params->pei_data->dqs_map[0])); + memcpy(mupd->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], + sizeof(params->pei_data->dqs_map[1])); + memcpy(mupd->RcompResistor, params->pei_data->RcompResistor, + sizeof(params->pei_data->RcompResistor)); + memcpy(mupd->RcompTarget, params->pei_data->RcompTarget, + sizeof(params->pei_data->RcompTarget)); + + mupd->DqPinsInterleaved = TRUE; +}

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Patch set updated for coreboot: soc/intel/apollolake: Use fixed resource for SRAM and IPC1
by Lijian Zhao 27 Sep '16

27 Sep '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16648 -gerrit commit 76d94527d36dc9082f4d0024cb1adfb6a2a5c015 Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:15:29 2016 -0700 soc/intel/apollolake: Use fixed resource for SRAM and IPC1 Intel telemetry support will require PMC IPC1 and SRAM devices to be operated in ACPI mode. Then using fixed resources on BAR0, BAR1 and BAR2(PMC only) for those two devices will help the resource assignment in DSDT stage. BUG=chrome-os-partner:57364 BRANCH=None TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/iomap.h | 6 +++ src/soc/intel/apollolake/include/soc/pci_ids.h | 1 + src/soc/intel/apollolake/pmc.c | 11 +++++ src/soc/intel/apollolake/pmutil.c | 3 +- src/soc/intel/apollolake/sram.c | 68 ++++++++++++++++++++++++++ 6 files changed, 88 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3c45cbe..4f867e1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -71,6 +71,7 @@ ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smi.c +ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 2045434..621b0a6 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -32,6 +32,12 @@ /* Accesses to these BARs are hardcoded in FSP */ #define PMC_BAR0 0xfe042000 #define PMC_BAR1 0xfe044000 +#define PMC_BAR0_SIZE (8 * KiB) + +#define PMC_SRAM_BASE_0 0xfe900000 +#define PMC_SRAM_SIZE_0 (8 * KiB) +#define PMC_SRAM_BASE_1 0xfe902000 +#define PMC_SRAM_SIZE_1 (4 * KiB) /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index cd56fdd..130263b 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -24,6 +24,7 @@ #define PCI_DEVICE_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_PMC 0x5a94 /* 00:0d.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ +#define PCI_DEVICE_ID_APOLLOLAKE_SRAM 0x5aec /* 00:0d.3 */ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */ diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 20c9492..4544e0d 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -39,6 +39,11 @@ static void read_resources(device_t dev) struct resource *res; pci_dev_read_resources(dev); + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = PMC_BAR0; + res->size = PMC_BAR0_SIZE; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = ACPI_PMIO_BASE; res->size = ACPI_PMIO_SIZE; @@ -58,6 +63,12 @@ static void set_resources(device_t dev) pci_dev_set_resources(dev); + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " PMC BAR"); + res = find_resource(dev, PCI_BASE_ADDRESS_4); pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_IO; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 56bb33d..80aaf71 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -34,8 +34,7 @@ static uintptr_t read_pmc_mmio_bar(void) { - uint32_t bar = pci_read_config32(PMC_DEV, PCI_BASE_ADDRESS_0); - return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + return PMC_BAR0; } uintptr_t get_pmc_mmio_bar(void) diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c new file mode 100644 index 0000000..44eb0ee --- /dev/null +++ b/src/soc/intel/apollolake/sram.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/iomap.h> + +static void read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = PMC_SRAM_BASE_0; + res->size = PMC_SRAM_SIZE_0; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, PCI_BASE_ADDRESS_2); + res->base = PMC_SRAM_BASE_1; + res->size = PMC_SRAM_SIZE_1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void set_resources(device_t dev) +{ + struct resource *res; + pci_dev_set_resources(dev); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " SRAM BAR 0"); + + res = find_resource(dev, PCI_BASE_ADDRESS_2); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " SRAM BAR 1"); +} + +static const struct device_operations device_ops = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_SRAM, +};

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Patch set updated for coreboot: [WIP]soc/apollolake: Set package lelve MSR
by Ravishankar Sarawadi 26 Sep '16

26 Sep '16

Ravishankar Sarawadi (ravishankar.sarawadi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16587 -gerrit commit bd8e15c4e31f0174f3ae6a502e876e2c076d6d1e Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Mon Sep 26 14:48:18 2016 -0700 [WIP]soc/apollolake: Set package lelve MSR Set package level MSRs after boot/suspend-cycle. BUG=chrome-os-partner:56922 BRANCH=None TEST=Use iotools rdmsr and 'powertop' to check MSRs Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767 --- src/soc/intel/apollolake/cpu.c | 11 +++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 1 + 2 files changed, 12 insertions(+) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 86fe3e1..8d02080 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> +#include <reg_script.h> #include <soc/cpu.h> #include <soc/smm.h> @@ -62,6 +63,13 @@ static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) *num_phys = (msr.lo >> 16) & 0xffff; } +/* Package level MSRs */ +static const struct reg_script package_msr_script[] = { + /* Set Package TDP to ~12W */ + REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x8f0000dd8c00), + REG_SCRIPT_END +}; + /* * Do essential initialization tasks before APs can be fired up * @@ -73,6 +81,9 @@ static void pre_mp_init(void) { x86_setup_mtrrs_with_detect(); x86_mtrr_check(); + + /* Set package MSRs */ + reg_script_run(package_msr_script); } /* Find CPU topology */ diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 22412af..78de6f8 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -39,6 +39,7 @@ void apollolake_init_cpus(struct device *dev); #define PREFETCH_L2_DISABLE (1 << 2) #define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_LIMIT 0x610 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f

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coreboot-gerrit September 2016