coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/skylake: Add config option for Skylake-H Sku support
by Boon Tiong Teo 28 Sep '16

28 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16607 -gerrit commit b8be3b4708d983d9c1d8f22ede814835a6773381 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Sep 15 11:11:45 2016 +0800 soc/intel/skylake: Add config option for Skylake-H Sku support Change-Id: Ia9c1c065f20bf2b37afc7485ef8df3abd35e2f14 --- src/soc/intel/skylake/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index edf5db3..c44d73f 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -169,6 +169,12 @@ config UART_DEBUG select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO +config SKYLAKE_SOC_PCH_H + bool + default n + help + Choose this option if you have a PCH-H chipset. + config CHIPSET_BOOTBLOCK_INCLUDE string default "soc/intel/skylake/bootblock/timestamp.inc"

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Patch set updated for coreboot: mb/intel: Add Saddle Brook board support
by Boon Tiong Teo 28 Sep '16

28 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16608 -gerrit commit dd86775c7b116e1cf8712dea83aeb716f66c5d7a Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Sep 15 11:49:04 2016 +0800 mb/intel: Add Saddle Brook board support Change-Id: I95c752922a74369cb8ae77be6cb886e4597814e4 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/mainboard/intel/saddlebrook/Kconfig | 45 +++++++ src/mainboard/intel/saddlebrook/Kconfig.name | 2 + src/mainboard/intel/saddlebrook/acpi/ec.asl | 14 +++ src/mainboard/intel/saddlebrook/acpi/mainboard.asl | 26 ++++ src/mainboard/intel/saddlebrook/acpi/superio.asl | 14 +++ src/mainboard/intel/saddlebrook/acpi_tables.c | 15 +++ src/mainboard/intel/saddlebrook/board_info.txt | 6 + src/mainboard/intel/saddlebrook/cmos.layout | 135 +++++++++++++++++++++ src/mainboard/intel/saddlebrook/devicetree.cb | 112 +++++++++++++++++ src/mainboard/intel/saddlebrook/dsdt.asl | 49 ++++++++ src/mainboard/intel/saddlebrook/fadt.c | 47 +++++++ src/mainboard/intel/saddlebrook/onboard.h | 19 +++ src/mainboard/intel/saddlebrook/romstage.c | 87 +++++++++++++ 13 files changed, 571 insertions(+) diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig new file mode 100644 index 0000000..691a080 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_SKLSDLBRK + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select MMCONF_SUPPORT + select MONOTONIC_TIMER_MSR + select PCIEXP_L1_SUB_STATE + select SOC_INTEL_SKYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select CONSOLE_SERIAL + select DRIVERS_UART + + +config IRQ_SLOT_COUNT + int + default 18 + +config BOOT_MEDIA_SPI_BUS + int + default 0 + +config MAINBOARD_DIR + string + default "intel/saddlebrook" + +config MAINBOARD_PART_NUMBER + string + default "Skylake Saddle Brook" + +config MAX_CPUS + int + default 8 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +endif diff --git a/src/mainboard/intel/saddlebrook/Kconfig.name b/src/mainboard/intel/saddlebrook/Kconfig.name new file mode 100644 index 0000000..c85fb81 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SKLSDLBRK + bool "Skylake Saddle Brook" diff --git a/src/mainboard/intel/saddlebrook/acpi/ec.asl b/src/mainboard/intel/saddlebrook/acpi/ec.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl new file mode 100644 index 0000000..76e9707 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> +#include <mainboard/intel/saddlebrook/onboard.h> + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} diff --git a/src/mainboard/intel/saddlebrook/acpi/superio.asl b/src/mainboard/intel/saddlebrook/acpi/superio.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/saddlebrook/acpi_tables.c b/src/mainboard/intel/saddlebrook/acpi_tables.c new file mode 100644 index 0000000..ccf9f74 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi_tables.c @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/saddlebrook/board_info.txt b/src/mainboard/intel/saddlebrook/board_info.txt new file mode 100644 index 0000000..5b33adf --- /dev/null +++ b/src/mainboard/intel/saddlebrook/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Saddle Brook Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout new file mode 100644 index 0000000..8467747 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb new file mode 100644 index 0000000..bd2a552 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -0,0 +1,112 @@ +chip soc/intel/skylake + + # SerialIO device modes + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoPci, \ + }" + + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # Enable S0ix + register "s0ix_enable" = "0" + + # Probeless Trace function + register "ProbelessTrace" = "0" + + # I/O Buffer Ownership: + # 0: HD-A Link + # 1 Shared, HD-A Link and I2S Port + # 3: I2S Ports + register "IoBufferOwnership" = "3" + + # Audio related + register "DspEnable" = "0" + + # USB related + register "SsicPortEnable" = "0" + + # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "2" + + # Integrated Sensor + register "IshEnable" = "0" + + # XDCI controller + register "XdciEnable" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT-Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 off end # PCI Express Port 17 + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on end # LPC Interface (eSPI Enable Strap = 0) eSPI Interface (eSPI Enable Strap = 1) + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus Controller + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl new file mode 100644 index 0000000..4134867 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/saddlebrook/fadt.c b/src/mainboard/intel/saddlebrook/fadt.c new file mode 100644 index 0000000..05fea01 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/fadt.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/saddlebrook/onboard.h b/src/mainboard/intel/saddlebrook/onboard.h new file mode 100644 index 0000000..f902542 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/onboard.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#endif diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c new file mode 100644 index 0000000..5671357 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <soc/cpu.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +void car_mainboard_pre_console_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_romstage_entry(struct romstage_params *params) +{ + post_code(0x31); + /* Fill out PEI DATA */ + mainboard_fill_pei_data(params->pei_data); + mainboard_fill_spd_data(params->pei_data); + /* Initliaze memory */ + romstage_common(params); +} + +void mainboard_memory_init_params( + struct romstage_params *params, + MEMORY_INIT_UPD *mupd) +{ + /* Get SPD data passing strucutre and initialize it.*/ + if (params->pei_data->spd_data[0][0][0] != 0) { + mupd->MemorySpdPtr00 = + (UINT32)(params->pei_data->spd_data[0][0]); + mupd->MemorySpdPtr10 = + (UINT32)(params->pei_data->spd_data[1][0]); + } + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", + mupd->MemorySpdPtr00); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", + mupd->MemorySpdPtr01); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", + mupd->MemorySpdPtr10); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", + mupd->MemorySpdPtr11); + + /* + * Configure the DQ/DQS settings if required. In general the settings + * should be set in the FSP flash image and should not need to be + * changed. + */ + memcpy(mupd->DqByteMapCh0, params->pei_data->dq_map[0], + sizeof(params->pei_data->dq_map[0])); + memcpy(mupd->DqByteMapCh1, params->pei_data->dq_map[1], + sizeof(params->pei_data->dq_map[1])); + memcpy(mupd->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], + sizeof(params->pei_data->dqs_map[0])); + memcpy(mupd->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], + sizeof(params->pei_data->dqs_map[1])); + memcpy(mupd->RcompResistor, params->pei_data->RcompResistor, + sizeof(params->pei_data->RcompResistor)); + memcpy(mupd->RcompTarget, params->pei_data->RcompTarget, + sizeof(params->pei_data->RcompTarget)); + + mupd->DqPinsInterleaved = TRUE; +}

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Patch set updated for coreboot: soc/intel/skylake: Add config option for Skylake-H Sku support
by Boon Tiong Teo 28 Sep '16

28 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16607 -gerrit commit 29c0af2007ded9799b3dd9f7d0ffb4e3b3c1aaed Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Sep 15 11:11:45 2016 +0800 soc/intel/skylake: Add config option for Skylake-H Sku support Change-Id: Ia9c1c065f20bf2b37afc7485ef8df3abd35e2f14 --- src/soc/intel/skylake/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index edf5db3..c44d73f 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -169,6 +169,12 @@ config UART_DEBUG select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO +config SKYLAKE_SOC_PCH_H + bool + default n + help + Choose this option if you have a PCH-H chipset. + config CHIPSET_BOOTBLOCK_INCLUDE string default "soc/intel/skylake/bootblock/timestamp.inc"

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Patch set updated for coreboot: src/soc/intel/skylake: Add config option for Skylake-H Sku support
by Boon Tiong Teo 28 Sep '16

28 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16607 -gerrit commit 5bc4a89e31c5bcf2ac0a4b3904f869f849b94e0e Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Sep 15 11:11:45 2016 +0800 src/soc/intel/skylake: Add config option for Skylake-H Sku support Change-Id: Ia9c1c065f20bf2b37afc7485ef8df3abd35e2f14 --- src/soc/intel/skylake/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index edf5db3..c44d73f 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -169,6 +169,12 @@ config UART_DEBUG select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO +config SKYLAKE_SOC_PCH_H + bool + default n + help + Choose this option if you have a PCH-H chipset. + config CHIPSET_BOOTBLOCK_INCLUDE string default "soc/intel/skylake/bootblock/timestamp.inc"

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Patch set updated for coreboot: mb/intel: Add Saddle Brook board support
by Boon Tiong Teo 28 Sep '16

28 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16608 -gerrit commit ca9e985ff4815d3556ce7db88a21136fd286f194 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Sep 15 11:49:04 2016 +0800 mb/intel: Add Saddle Brook board support Change-Id: I95c752922a74369cb8ae77be6cb886e4597814e4 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/mainboard/intel/saddlebrook/Kconfig | 45 +++++++ src/mainboard/intel/saddlebrook/Kconfig.name | 2 + src/mainboard/intel/saddlebrook/acpi/ec.asl | 14 +++ src/mainboard/intel/saddlebrook/acpi/mainboard.asl | 26 ++++ src/mainboard/intel/saddlebrook/acpi/superio.asl | 14 +++ src/mainboard/intel/saddlebrook/acpi_tables.c | 15 +++ src/mainboard/intel/saddlebrook/board_info.txt | 6 + src/mainboard/intel/saddlebrook/cmos.layout | 135 +++++++++++++++++++++ src/mainboard/intel/saddlebrook/devicetree.cb | 112 +++++++++++++++++ src/mainboard/intel/saddlebrook/dsdt.asl | 49 ++++++++ src/mainboard/intel/saddlebrook/fadt.c | 47 +++++++ src/mainboard/intel/saddlebrook/onboard.h | 19 +++ src/mainboard/intel/saddlebrook/romstage.c | 87 +++++++++++++ 13 files changed, 571 insertions(+) diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig new file mode 100644 index 0000000..656d165 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_SKLSDLBRK + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select MMCONF_SUPPORT + select MONOTONIC_TIMER_MSR + select PCIEXP_L1_SUB_STATE + select SOC_INTEL_SKYLAKE + select SKYLAKE_SOC_PCH_H + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select CONSOLE_SERIAL + select DRIVERS_UART + + +config IRQ_SLOT_COUNT + int + default 18 + +config BOOT_MEDIA_SPI_BUS + int + default 0 + +config MAINBOARD_DIR + string + default "intel/sklsdlbrk" + +config MAINBOARD_PART_NUMBER + string + default "Skylake Saddle Brook" + +config MAX_CPUS + int + default 8 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + +endif diff --git a/src/mainboard/intel/saddlebrook/Kconfig.name b/src/mainboard/intel/saddlebrook/Kconfig.name new file mode 100644 index 0000000..c85fb81 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SKLSDLBRK + bool "Skylake Saddle Brook" diff --git a/src/mainboard/intel/saddlebrook/acpi/ec.asl b/src/mainboard/intel/saddlebrook/acpi/ec.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi/ec.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl new file mode 100644 index 0000000..ddccc21 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> +#include <mainboard/intel/sklsdlbrk/onboard.h> + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} \ No newline at end of file diff --git a/src/mainboard/intel/saddlebrook/acpi/superio.asl b/src/mainboard/intel/saddlebrook/acpi/superio.asl new file mode 100644 index 0000000..de9dc8c --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi/superio.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/saddlebrook/acpi_tables.c b/src/mainboard/intel/saddlebrook/acpi_tables.c new file mode 100644 index 0000000..ccf9f74 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/acpi_tables.c @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/mainboard/intel/saddlebrook/board_info.txt b/src/mainboard/intel/saddlebrook/board_info.txt new file mode 100644 index 0000000..5b33adf --- /dev/null +++ b/src/mainboard/intel/saddlebrook/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Saddle Brook Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout new file mode 100644 index 0000000..8467747 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb new file mode 100644 index 0000000..bd2a552 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -0,0 +1,112 @@ +chip soc/intel/skylake + + # SerialIO device modes + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoPci, \ + }" + + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # Enable S0ix + register "s0ix_enable" = "0" + + # Probeless Trace function + register "ProbelessTrace" = "0" + + # I/O Buffer Ownership: + # 0: HD-A Link + # 1 Shared, HD-A Link and I2S Port + # 3: I2S Ports + register "IoBufferOwnership" = "3" + + # Audio related + register "DspEnable" = "0" + + # USB related + register "SsicPortEnable" = "0" + + # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "2" + + # Integrated Sensor + register "IshEnable" = "0" + + # XDCI controller + register "XdciEnable" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT-Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 off end # PCI Express Port 17 + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on end # LPC Interface (eSPI Enable Strap = 0) eSPI Interface (eSPI Enable Strap = 1) + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus Controller + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl new file mode 100644 index 0000000..4134867 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/saddlebrook/fadt.c b/src/mainboard/intel/saddlebrook/fadt.c new file mode 100644 index 0000000..05fea01 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/fadt.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/saddlebrook/onboard.h b/src/mainboard/intel/saddlebrook/onboard.h new file mode 100644 index 0000000..f902542 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/onboard.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#endif diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c new file mode 100644 index 0000000..5671357 --- /dev/null +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <soc/cpu.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +void car_mainboard_pre_console_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_romstage_entry(struct romstage_params *params) +{ + post_code(0x31); + /* Fill out PEI DATA */ + mainboard_fill_pei_data(params->pei_data); + mainboard_fill_spd_data(params->pei_data); + /* Initliaze memory */ + romstage_common(params); +} + +void mainboard_memory_init_params( + struct romstage_params *params, + MEMORY_INIT_UPD *mupd) +{ + /* Get SPD data passing strucutre and initialize it.*/ + if (params->pei_data->spd_data[0][0][0] != 0) { + mupd->MemorySpdPtr00 = + (UINT32)(params->pei_data->spd_data[0][0]); + mupd->MemorySpdPtr10 = + (UINT32)(params->pei_data->spd_data[1][0]); + } + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", + mupd->MemorySpdPtr00); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", + mupd->MemorySpdPtr01); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", + mupd->MemorySpdPtr10); + printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", + mupd->MemorySpdPtr11); + + /* + * Configure the DQ/DQS settings if required. In general the settings + * should be set in the FSP flash image and should not need to be + * changed. + */ + memcpy(mupd->DqByteMapCh0, params->pei_data->dq_map[0], + sizeof(params->pei_data->dq_map[0])); + memcpy(mupd->DqByteMapCh1, params->pei_data->dq_map[1], + sizeof(params->pei_data->dq_map[1])); + memcpy(mupd->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], + sizeof(params->pei_data->dqs_map[0])); + memcpy(mupd->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], + sizeof(params->pei_data->dqs_map[1])); + memcpy(mupd->RcompResistor, params->pei_data->RcompResistor, + sizeof(params->pei_data->RcompResistor)); + memcpy(mupd->RcompTarget, params->pei_data->RcompTarget, + sizeof(params->pei_data->RcompTarget)); + + mupd->DqPinsInterleaved = TRUE; +}

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Patch set updated for coreboot: superio/nuvoton: Add back Nuvoton NCT6776 support
by Boon Tiong Teo 28 Sep '16

28 Sep '16

Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16519 -gerrit commit c02ad5968181d692c7e16f5900f5cf5fbb38b2a5 Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Mon Sep 5 16:00:07 2016 +0800 superio/nuvoton: Add back Nuvoton NCT6776 support Revert commit 53552cc0 (Drop SuperIO nuvoton/nct6776), removing the code as no other mainboard uses it. The board Intel Saddle Brook uses this device, so add the code back with minor adaptations. Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> --- src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/common/early_serial.c | 3 + src/superio/nuvoton/nct6776/Kconfig | 23 +++++++ src/superio/nuvoton/nct6776/Makefile.inc | 18 ++++++ src/superio/nuvoton/nct6776/nct6776.h | 58 ++++++++++++++++++ src/superio/nuvoton/nct6776/superio.c | 99 +++++++++++++++++++++++++++++++ 6 files changed, 202 insertions(+) diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 94cc6b7..e2e178b 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -19,5 +19,6 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index fca5ed6..d1958a0 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -63,6 +63,9 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); + if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A)) + /* Route GPIO8 pin group to COM A */ + pnp_write_config(dev, 0x2a, 0x40); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); diff --git a/src/superio/nuvoton/nct6776/Kconfig b/src/superio/nuvoton/nct6776/Kconfig new file mode 100644 index 0000000..cf0fe21 --- /dev/null +++ b/src/superio/nuvoton/nct6776/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_NUVOTON_NCT6776 + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT6776_COM_A + bool + default n diff --git a/src/superio/nuvoton/nct6776/Makefile.inc b/src/superio/nuvoton/nct6776/Makefile.inc new file mode 100644 index 0000000..13fe527 --- /dev/null +++ b/src/superio/nuvoton/nct6776/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += superio.c diff --git a/src/superio/nuvoton/nct6776/nct6776.h b/src/superio/nuvoton/nct6776/nct6776.h new file mode 100644 index 0000000..520401e --- /dev/null +++ b/src/superio/nuvoton/nct6776/nct6776.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +#ifndef SUPERIO_NUVOTON_NCT6776_H +#define SUPERIO_NUVOTON_NCT6776_H + +/* Logical Device Numbers (LDN). */ +#define NCT6776_FDC 0x00 /* Floppy */ +#define NCT6776_PP 0x01 /* Parallel port */ +#define NCT6776_SP1 0x02 /* Com1 */ +#define NCT6776_SP2 0x03 /* Com2 & IR */ +#define NCT6776_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT6776_CIR 0x06 +#define NCT6776_GPIO6789_V 0x07 +#define NCT6776_WDT1_GPIO01A_V 0x08 +#define NCT6776_GPIO1234567_V 0x09 +#define NCT6776_ACPI 0x0A +#define NCT6776_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT6776_VID 0x0D +#define NCT6776_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT6776_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT6776_SVID 0x14 +#define NCT6776_DSLP 0x16 /* Deep sleep */ +#define NCT6776_GPIOA_LDN 0x17 + +/* virtual LDN for GPIO and WDT */ +#define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V) + +#define NCT6776_GPIOBASE ((0 << 8) | NCT6776_WDT1_GPIO01A_V) //? + +#define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V) +#define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO2 ((2 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO3 ((3 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO4 ((4 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO5 ((5 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO6 ((6 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO7 ((7 << 8) | NCT6776_GPIO1234567_V) +#define NCT6776_GPIO8 ((0 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIO9 ((1 << 8) | NCT6776_GPIO6789_V) +#define NCT6776_GPIOA ((2 << 8) | NCT6776_WDT1_GPIO01A_V) + +#endif /* SUPERIO_NUVOTON_NCT6776_H */ diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c new file mode 100644 index 0000000..85f52cf --- /dev/null +++ b/src/superio/nuvoton/nct6776/superio.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct6776.h" + +/* Both NCT6776D and NCT6776F package variants are supported. */ + +static void nct6776_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case NCT6776_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6776_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_SP1, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_SP2, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, NCT6776_CIR, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_ACPI}, + { &ops, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + {0x0ffe, 0}, {0x0ffe, 4}, }, + { &ops, NCT6776_VID}, + { &ops, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO_PP_OD}, + { &ops, NCT6776_SVID}, + { &ops, NCT6776_DSLP}, + { &ops, NCT6776_GPIOA_LDN}, + { &ops, NCT6776_WDT1}, + { &ops, NCT6776_GPIOBASE, PNP_IO0, + {0x0ff8, 0}, }, + { &ops, NCT6776_GPIO0}, + { &ops, NCT6776_GPIO1}, + { &ops, NCT6776_GPIO2}, + { &ops, NCT6776_GPIO3}, + { &ops, NCT6776_GPIO4}, + { &ops, NCT6776_GPIO5}, + { &ops, NCT6776_GPIO6}, + { &ops, NCT6776_GPIO7}, + { &ops, NCT6776_GPIO8}, + { &ops, NCT6776_GPIO9}, + { &ops, NCT6776_GPIOA}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6776_ops = { + CHIP_NAME("NUVOTON NCT6776 Super I/O") + .enable_dev = enable_dev, +};

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New patch to review for coreboot: mainboard/gigabyte/ga_2761gxdk: Use tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16779 -gerrit commit 2a05fd8452eca1639e2cc8385116b2c71fdefcbd Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 22:05:31 2016 +0200 mainboard/gigabyte/ga_2761gxdk: Use tabs for indents Change-Id: Ie752fe0a74acd4b79711596e56fc5ebf83884a0d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb | 100 ++++++++-------- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 138 +++++++++++------------ 2 files changed, 119 insertions(+), 119 deletions(-) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb index 33b8505..6c99032 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb +++ b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb @@ -1,83 +1,83 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_AM2 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x1039 0x1234 inherit chip northbridge/amd/amdk8 #mc0 device pci 18.0 on # devices on link 0, link 0 == LDT 0 - chip southbridge/sis/sis966 + chip southbridge/sis/sis966 device pci 0.0 on end # Northbridge device pci 1.0 on # AGP bridge device pci 0.0 on end end - device pci 2.0 on # LPC + device pci 2.0 on # LPC chip superio/ite/it8716f device pnp 2e.0 off # Floppy (N/A) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.2 off # Com2 (N/A) - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.2 off # Com2 (N/A) + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.3 off # Parallel port (N/A) - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.3 off # Parallel port (N/A) + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 end device pnp 2e.5 off # PS/2 keyboard (N/A) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 end device pnp 2e.6 off # Mouse (N/A) - irq 0x70 = 12 + irq 0x70 = 12 end - device pnp 2e.8 off # MIDI (N/A) + device pnp 2e.8 off # MIDI (N/A) io 0x60 = 0x300 irq 0x70 = 10 end - device pnp 2e.9 off # GAME (N/A) + device pnp 2e.9 off # GAME (N/A) io 0x60 = 0x220 end - device pnp 2e.a off end # CIR (N/A) + device pnp 2e.a off end # CIR (N/A) end end - device pci 2.5 off end # IDE (SiS5513) - device pci 2.6 off end # Modem (SiS7013) - device pci 2.7 off end # Audio (SiS7012) - device pci 3.0 on end # USB (SiS7001,USB1.1) - device pci 3.1 on end # USB (SiS7001,USB1.1) - device pci 3.3 on end # USB (SiS7002,USB2.0) - device pci 4.0 on end # NIC (SiS191) - device pci 5.0 on end # SATA (SiS1183,Native Mode) - device pci 6.0 on end # PCI-e x1 - device pci 7.0 on end # PCI-e x1 - device pci a.0 off end - device pci b.0 off end - device pci c.0 off end - device pci d.0 off end - device pci e.0 off end - device pci f.0 off end # HD Audio (SiS7502) + device pci 2.5 off end # IDE (SiS5513) + device pci 2.6 off end # Modem (SiS7013) + device pci 2.7 off end # Audio (SiS7012) + device pci 3.0 on end # USB (SiS7001,USB1.1) + device pci 3.1 on end # USB (SiS7001,USB1.1) + device pci 3.3 on end # USB (SiS7002,USB2.0) + device pci 4.0 on end # NIC (SiS191) + device pci 5.0 on end # SATA (SiS1183,Native Mode) + device pci 6.0 on end # PCI-e x1 + device pci 7.0 on end # PCI-e x1 + device pci a.0 off end + device pci b.0 off end + device pci c.0 off end + device pci d.0 off end + device pci e.0 off end + device pci f.0 off end # HD Audio (SiS7502) - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end end # device pci 18.0 device pci 18.0 on end # Link 1 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 68cbaad..337423f 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -67,12 +67,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define SIS966_PCI_E_X_0 0 #define SIS966_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include <southbridge/sis/sis966/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" @@ -81,20 +81,20 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + uint32_t dword; + uint8_t byte; - byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0); - dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0); + dword |= (1 << 0); + pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword); - dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4); - dword |= (1 << 16); - pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4); + dword |= (1 << 16); + pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -108,90 +108,90 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = &sysinfo_car; - int needs_reset = 0; - unsigned bsp_apicid = 0; + struct sys_info *sysinfo = &sysinfo_car; + int needs_reset = 0; + unsigned bsp_apicid = 0; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + } - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - setup_mb_resource_map(); + setup_mb_resource_map(); - console_init(); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); // routing table and start other core0 + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + setup_coherent_ht_domain(); // routing table and start other core0 - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif - /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); - } + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); + } #endif - needs_reset |= optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } - allow_all_aps_stop(bsp_apicid); + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } + allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - sis_init_stage1(); - enable_smbus(); + sis_init_stage1(); + enable_smbus(); - //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synchronize FID/VID + //do we need apci timer, tsc...., only debug need it for better output + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synchronize FID/VID - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - sis_init_stage2(); - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + sis_init_stage2(); + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }

1 0

New patch to review for coreboot: mainboard/amd/rumba: Use tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16778 -gerrit commit 29e5cc090b9c2cc93e8d7e28294962f3856bd14c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 21:56:36 2016 +0200 mainboard/amd/rumba: Use tabs for indents Change-Id: I005e607faa2a6c527584ba9cdcad92f4517a15e6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/rumba/devicetree.cb | 20 ++++++++++---------- src/mainboard/amd/rumba/mainboard.c | 4 ++-- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index 62fb287..d480355 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -4,17 +4,17 @@ chip northbridge/amd/gx2 device lapic 0 on end end end - device domain 0 on - device pci 1.0 on end + device domain 0 on + device pci 1.0 on end device pci 1.1 on end - chip southbridge/amd/cs5536 + chip southbridge/amd/cs5536 register "lpc_serirq_enable" = "0x80" # enabled with default timing - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI + device pci d.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI device pci f.5 on end # EHCI - end - end + end + end end diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index f0c2a3a..a971db6 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -42,9 +42,9 @@ static void init(struct device *dev) static void mainboard_enable(struct device *dev) { - dev->ops->init = init; + dev->ops->init = init; } struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .enable_dev = mainboard_enable, };

1 0

New patch to review for coreboot: mainboard/technexion/tim5690: Use tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16777 -gerrit commit 0ebc89dfdddf36ac9e0b8404620c55a4ac1c6b2a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 21:36:55 2016 +0200 mainboard/technexion/tim5690: Use tabs for indents Change-Id: Icd1f145b3575c6d95dacceb9c0426fbdedcdd686 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/technexion/tim5690/acpi/usb.asl | 4 +- src/mainboard/technexion/tim5690/mainboard.c | 48 ++-- src/mainboard/technexion/tim5690/speaker.c | 66 ++--- src/mainboard/technexion/tim5690/tn_post_code.c | 340 ++++++++++++------------ src/mainboard/technexion/tim5690/vgabios.c | 48 ++-- 5 files changed, 253 insertions(+), 253 deletions(-) diff --git a/src/mainboard/technexion/tim5690/acpi/usb.asl b/src/mainboard/technexion/tim5690/acpi/usb.asl index 5381e76..dbffa39 100644 --- a/src/mainboard/technexion/tim5690/acpi/usb.asl +++ b/src/mainboard/technexion/tim5690/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } @@ -122,7 +122,7 @@ If (LLessEqual(UOM6,9)) { /* USB Port 7 overcurrent uses Gpm 7 */ If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { + Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index f84b7a0..8bc1075 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -82,29 +82,29 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); LDN the register belongs to, before you can access the register. */ static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) { - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); + outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); } static void it8712f_enter_conf(void) { - /* Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8712F_CONFIGURATION_PORT); - outb(0x01, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); + /* Enter the configuration state (MB PnP mode). */ + + /* Perform MB PnP setup to put the SIO chip at 0x2e. */ + /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ + /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ + outb(0x87, IT8712F_CONFIGURATION_PORT); + outb(0x01, IT8712F_CONFIGURATION_PORT); + outb(0x55, IT8712F_CONFIGURATION_PORT); + outb(0x55, IT8712F_CONFIGURATION_PORT); } static void it8712f_exit_conf(void) { - /* Exit the configuration state (MB PnP mode). */ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); + /* Exit the configuration state (MB PnP mode). */ + it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } /* set thermal config @@ -173,15 +173,15 @@ static void set_thermal_config(void) /* Mainboard specific GPIO setup. */ static void mb_gpio_init(u16 *iobase) { - /* Init Super I/O GPIOs. */ - it8712f_enter_conf(); - outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); - outb(IT8712F_GPIO, SIO_DATA); - outb(0x62, SIO_INDEX); - outb((*iobase >> 8), SIO_DATA); - outb(0x63, SIO_INDEX); - outb((*iobase & 0xff), SIO_DATA); - it8712f_exit_conf(); + /* Init Super I/O GPIOs. */ + it8712f_enter_conf(); + outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); + outb(IT8712F_GPIO, SIO_DATA); + outb(0x62, SIO_INDEX); + outb((*iobase >> 8), SIO_DATA); + outb(0x63, SIO_INDEX); + outb((*iobase & 0xff), SIO_DATA); + it8712f_exit_conf(); } #if CONFIG_VGA_ROM_RUN diff --git a/src/mainboard/technexion/tim5690/speaker.c b/src/mainboard/technexion/tim5690/speaker.c index 50f510d..7c0ea64 100644 --- a/src/mainboard/technexion/tim5690/speaker.c +++ b/src/mainboard/technexion/tim5690/speaker.c @@ -33,55 +33,55 @@ #include "speaker.h" void speaker_init(uint8_t time) { - /* SB600 RRG. - * Options_0 - RW - 8 bits - [PM_Reg: 60h]. - * SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output. - */ + /* SB600 RRG. + * Options_0 - RW - 8 bits - [PM_Reg: 60h]. + * SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output. + */ #ifdef __PRE_RAM__ - pmio_write(0x60, (pmio_read(0x60) | (1<<5))); + pmio_write(0x60, (pmio_read(0x60) | (1<<5))); #else - pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5))); + pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5))); #endif /* __PRE_RAM__ */ - /* SB600 RRG. - * Tmr1CntrlWord - RW - 8 bits - [IO_Reg: 43h]. - * ModeSelect, bit[3:1]=011b, Square wave output. - * CmmandSelect, bit[5:4]=11b, Read/write least, and then most significant byte. - * CounterSelect, bit[7:6]=10b, Select counter 2. - */ - outb(0xb6, 0x43); + /* SB600 RRG. + * Tmr1CntrlWord - RW - 8 bits - [IO_Reg: 43h]. + * ModeSelect, bit[3:1]=011b, Square wave output. + * CmmandSelect, bit[5:4]=11b, Read/write least, and then most significant byte. + * CounterSelect, bit[7:6]=10b, Select counter 2. + */ + outb(0xb6, 0x43); - /* SB600 RRG. - * TimerCh2- RW - 8 bits - [IO_Reg: 42h]. - */ - outb(time, 0x42); + /* SB600 RRG. + * TimerCh2- RW - 8 bits - [IO_Reg: 42h]. + */ + outb(time, 0x42); } void speaker_on_nodelay(void) { - /* SB600 RRG. - * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. - * SpkrEnable, bit[0]=1b, Enable counter 2 - * SpkrTmrEnable, bit[1]=1b, Speaker timer on - */ - outb(inb(0x61) | 0x03, 0x61); + /* SB600 RRG. + * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. + * SpkrEnable, bit[0]=1b, Enable counter 2 + * SpkrTmrEnable, bit[1]=1b, Speaker timer on + */ + outb(inb(0x61) | 0x03, 0x61); } void speaker_on_delay(void) { - speaker_on_nodelay(); - mdelay(100); + speaker_on_nodelay(); + mdelay(100); } void speaker_off_nodelay(void) { - /* SB600 RRG. - * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. - * SpkrEnable, bit[0]=0b, Disable counter 2 - * SpkrTmrEnable, bit[1]=0b, Speaker timer off - */ - outb(inb(0x61) & ~0x03, 0x61); + /* SB600 RRG. + * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. + * SpkrEnable, bit[0]=0b, Disable counter 2 + * SpkrTmrEnable, bit[1]=0b, Speaker timer off + */ + outb(inb(0x61) & ~0x03, 0x61); } void speaker_off_delay(void) { - speaker_off_nodelay(); - mdelay(100); + speaker_off_nodelay(); + mdelay(100); } diff --git a/src/mainboard/technexion/tim5690/tn_post_code.c b/src/mainboard/technexion/tim5690/tn_post_code.c index 213034a..fba0d75 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.c +++ b/src/mainboard/technexion/tim5690/tn_post_code.c @@ -35,90 +35,90 @@ // TechNexion's Post Code Initially. void technexion_post_code_init(void) { - uint8_t reg8_data; - device_t dev = 0; - - // SMBus Module and ACPI Block (Device 20, Function 0) - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); - - // LED[bit0]:GPIO0 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pmio_read(0x60); - reg8_data |= (1 << 7); // 1: GPIO if not used by SATA - pmio_write(0x60, reg8_data); - - reg8_data = pci_read_config8(dev, 0x80); - reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 4)); - pci_write_config8(dev, 0x80, reg8_data); - - // LED[bit1]:GPIO1 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pci_read_config8(dev, 0x80); - reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5)); - pci_write_config8(dev, 0x80, reg8_data); - - // LED[bit2]:GPIO4 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pmio_read(0x5e); - reg8_data &= ~(1 << 7); // 0: GPIO if not used by SATA - pmio_write(0x5e, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1 << 0); - pci_write_config8(dev, 0xa8, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1 << 0); - pci_write_config8(dev, 0xa9, reg8_data); - - // LED[bit3]:GPIO6 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pmio_read(0x60); - reg8_data |= (1 << 7); // 1: GPIO if not used by SATA - pmio_write(0x60, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1 << 2); - pci_write_config8(dev, 0xa8, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1 << 2); - pci_write_config8(dev, 0xa9, reg8_data); - // LED[bit4]:GPIO7 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1 << 3); - pci_write_config8(dev, 0xa8, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1 << 3); - pci_write_config8(dev, 0xa9, reg8_data); - - // LED[bit5]:GPIO8 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pci_read_config8(dev, 0xa8); - reg8_data |= (1 << 4); - pci_write_config8(dev, 0xa8, reg8_data); - - reg8_data = pci_read_config8(dev, 0xa9); - reg8_data &= ~(1 << 4); - pci_write_config8(dev, 0xa9, reg8_data); - - // LED[bit6]:GPIO10 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pci_read_config8(dev, 0xab); - reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 1)); - pci_write_config8(dev, 0xab, reg8_data); - - // LED[bit7]:GPIO66 - // This is reference SB600 RRG 4.1.1 GPIO - reg8_data = pmio_read(0x68); - reg8_data &= ~(1 << 5); // 0: GPIO - pmio_write(0x68, reg8_data); - - reg8_data = pci_read_config8(dev, 0x7e); - reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5)); - pci_write_config8(dev, 0x7e, reg8_data); + uint8_t reg8_data; + device_t dev = 0; + + // SMBus Module and ACPI Block (Device 20, Function 0) + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); + + // LED[bit0]:GPIO0 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x60); + reg8_data |= (1 << 7); // 1: GPIO if not used by SATA + pmio_write(0x60, reg8_data); + + reg8_data = pci_read_config8(dev, 0x80); + reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 4)); + pci_write_config8(dev, 0x80, reg8_data); + + // LED[bit1]:GPIO1 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0x80); + reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5)); + pci_write_config8(dev, 0x80, reg8_data); + + // LED[bit2]:GPIO4 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x5e); + reg8_data &= ~(1 << 7); // 0: GPIO if not used by SATA + pmio_write(0x5e, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1 << 0); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1 << 0); + pci_write_config8(dev, 0xa9, reg8_data); + + // LED[bit3]:GPIO6 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x60); + reg8_data |= (1 << 7); // 1: GPIO if not used by SATA + pmio_write(0x60, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1 << 2); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1 << 2); + pci_write_config8(dev, 0xa9, reg8_data); + // LED[bit4]:GPIO7 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1 << 3); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1 << 3); + pci_write_config8(dev, 0xa9, reg8_data); + + // LED[bit5]:GPIO8 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0xa8); + reg8_data |= (1 << 4); + pci_write_config8(dev, 0xa8, reg8_data); + + reg8_data = pci_read_config8(dev, 0xa9); + reg8_data &= ~(1 << 4); + pci_write_config8(dev, 0xa9, reg8_data); + + // LED[bit6]:GPIO10 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pci_read_config8(dev, 0xab); + reg8_data = ((reg8_data | (1 << 0)) & ~(1 << 1)); + pci_write_config8(dev, 0xab, reg8_data); + + // LED[bit7]:GPIO66 + // This is reference SB600 RRG 4.1.1 GPIO + reg8_data = pmio_read(0x68); + reg8_data &= ~(1 << 5); // 0: GPIO + pmio_write(0x68, reg8_data); + + reg8_data = pci_read_config8(dev, 0x7e); + reg8_data = ((reg8_data | (1 << 1)) & ~(1 << 5)); + pci_write_config8(dev, 0x7e, reg8_data); } @@ -128,96 +128,96 @@ void technexion_post_code_init(void) */ void technexion_post_code(uint8_t udata8) { - uint8_t u8_data; - device_t dev = 0; + uint8_t u8_data; + device_t dev = 0; - // SMBus Module and ACPI Block (Device 20, Function 0) + // SMBus Module and ACPI Block (Device 20, Function 0) #ifdef __PRE_RAM__ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); #else - dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0); + dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0); #endif - udata8 = ~(udata8); - - // LED[bit0]:GPIO0 - u8_data = pci_read_config8(dev, 0x80); - if (udata8 & 0x1) { - u8_data |= (1 << 0); - } - else { - u8_data &= ~(1 << 0); - } - pci_write_config8(dev, 0x80, u8_data); - - // LED[bit1]:GPIO1 - u8_data = pci_read_config8(dev, 0x80); - if (udata8 & 0x2) { - u8_data |= (1 << 1); - } - else { - u8_data &= ~(1 << 1); - } - pci_write_config8(dev, 0x80, u8_data); - - // LED[bit2]:GPIO4 - u8_data = pci_read_config8(dev, 0xa8); - if (udata8 & 0x4) { - u8_data |= (1 << 0); - } - else { - u8_data &= ~(1 << 0); - } - pci_write_config8(dev, 0xa8, u8_data); - - // LED[bit3]:GPIO6 - u8_data = pci_read_config8(dev, 0xa8); - if (udata8 & 0x8) { - u8_data |= (1 << 2); - } - else { - u8_data &= ~(1 << 2); - } - pci_write_config8(dev, 0xa8, u8_data); - - // LED[bit4]:GPIO7 - u8_data = pci_read_config8(dev, 0xa8); - if (udata8 & 0x10) { - u8_data |= (1 << 3); - } - else { - u8_data &= ~(1 << 3); - } - pci_write_config8(dev, 0xa8, u8_data); - - // LED[bit5]:GPIO8 - u8_data = pci_read_config8(dev, 0xa8); - if (udata8 & 0x20) { - u8_data |= (1 << 4); - } - else { - u8_data &= ~(1 << 4); - } - pci_write_config8(dev, 0xa8, u8_data); - - // LED[bit6]:GPIO10 - u8_data = pci_read_config8(dev, 0xab); - if (udata8 & 0x40) { - u8_data |= (1 << 0); - } - else { - u8_data &= ~(1 << 0); - } - pci_write_config8(dev, 0xab, u8_data); - - // LED[bit7]:GPIO66 - u8_data = pci_read_config8(dev, 0x7e); - if (udata8 & 0x80) { - u8_data |= (1 << 1); - } - else { - u8_data &= ~(1 << 1); - } - pci_write_config8(dev, 0x7e, u8_data); + udata8 = ~(udata8); + + // LED[bit0]:GPIO0 + u8_data = pci_read_config8(dev, 0x80); + if (udata8 & 0x1) { + u8_data |= (1 << 0); + } + else { + u8_data &= ~(1 << 0); + } + pci_write_config8(dev, 0x80, u8_data); + + // LED[bit1]:GPIO1 + u8_data = pci_read_config8(dev, 0x80); + if (udata8 & 0x2) { + u8_data |= (1 << 1); + } + else { + u8_data &= ~(1 << 1); + } + pci_write_config8(dev, 0x80, u8_data); + + // LED[bit2]:GPIO4 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x4) { + u8_data |= (1 << 0); + } + else { + u8_data &= ~(1 << 0); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit3]:GPIO6 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x8) { + u8_data |= (1 << 2); + } + else { + u8_data &= ~(1 << 2); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit4]:GPIO7 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x10) { + u8_data |= (1 << 3); + } + else { + u8_data &= ~(1 << 3); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit5]:GPIO8 + u8_data = pci_read_config8(dev, 0xa8); + if (udata8 & 0x20) { + u8_data |= (1 << 4); + } + else { + u8_data &= ~(1 << 4); + } + pci_write_config8(dev, 0xa8, u8_data); + + // LED[bit6]:GPIO10 + u8_data = pci_read_config8(dev, 0xab); + if (udata8 & 0x40) { + u8_data |= (1 << 0); + } + else { + u8_data &= ~(1 << 0); + } + pci_write_config8(dev, 0xab, u8_data); + + // LED[bit7]:GPIO66 + u8_data = pci_read_config8(dev, 0x7e); + if (udata8 & 0x80) { + u8_data |= (1 << 1); + } + else { + u8_data &= ~(1 << 1); + } + pci_write_config8(dev, 0x7e, u8_data); } diff --git a/src/mainboard/technexion/tim5690/vgabios.c b/src/mainboard/technexion/tim5690/vgabios.c index f62bc87..fe4b41c 100644 --- a/src/mainboard/technexion/tim5690/vgabios.c +++ b/src/mainboard/technexion/tim5690/vgabios.c @@ -30,39 +30,39 @@ static rs690_vbios_regs vbios_regs_local; /* Initialization interrupt function */ static void vbios_fun_init(rs690_vbios_regs *vbios_regs) { - vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id; - vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard; + vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id; + vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard; } /* BIOS int15 function */ int tim5690_int15_handler(void) { - int res = 0; + int res = 0; - printk(BIOS_DEBUG, "tim5690_int15_handler\n"); + printk(BIOS_DEBUG, "tim5690_int15_handler\n"); - switch (X86_EAX & 0xffff) { - case AMD_RS690_INT15: - switch (X86_EBX & 0xff) { - case 0x00: - X86_EAX &= ~(0xff); - X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun00_panel_id; - res = 1; - break; - case 0x05: - X86_EAX &= ~(0xff); - X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun05_tv_standard; - res = 1; - break; - } - break; - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - X86_EAX & 0xffff); + switch (X86_EAX & 0xffff) { + case AMD_RS690_INT15: + switch (X86_EBX & 0xff) { + case 0x00: + X86_EAX &= ~(0xff); + X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun00_panel_id; + res = 1; + break; + case 0x05: + X86_EAX &= ~(0xff); + X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun05_tv_standard; + res = 1; + break; + } break; - } + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + X86_EAX & 0xffff); + break; + } - return res; + return res; } /* Initialization VBIOS function */

1 0

New patch to review for coreboot: mainboard/sunw/ultra40/romstage.c: Use tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16776 -gerrit commit 22b3cffb9fc32ab479b4d302f0db45d076fb698b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 21:28:57 2016 +0200 mainboard/sunw/ultra40/romstage.c: Use tabs for indents Change-Id: I9b7be74625dfcb6317a1cdb61d0dc77d7f359462 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/sunw/ultra40/romstage.c | 96 +++++++++++++++++------------------ 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index d0f569c..397acfe 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -30,12 +30,12 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } #ifdef ENABLE_ONBOARD_SCSI static void sio_gpio_setup(void) { - unsigned value; + unsigned value; - /*Enable onboard scsi*/ - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1 << 7)|(0 << 2)|(0 << 1)|(0 << 0)); // GP21, offset 0x2c, DISABLE_SCSI_L - value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1 << 1))); + /*Enable onboard scsi*/ + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1 << 7)|(0 << 2)|(0 << 1)|(0 << 0)); // GP21, offset 0x2c, DISABLE_SCSI_L + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1 << 1))); } #endif @@ -55,12 +55,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) //set GPIO to input mode #define CK804_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -68,25 +68,25 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void sio_setup(void) { - unsigned value; - uint32_t dword; - uint8_t byte; + unsigned value; + uint32_t dword; + uint8_t byte; - pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); - byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); - dword |= (1 << 29)|(1 << 0); - pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); + dword |= (1 << 29)|(1 << 0); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); - lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); + lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); - value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); - value &= 0xbf; - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); + value &= 0xbf; + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -100,49 +100,49 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - int needs_reset; - unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + int needs_reset; + unsigned bsp_apicid = 0, nodes; + struct mem_controller ctrl[8]; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + } - if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx); + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx); lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - setup_ultra40_resource_map(); + setup_ultra40_resource_map(); needs_reset = setup_coherent_ht_domain(); - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif - needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } + needs_reset |= ht_setup_chains_x(); + needs_reset |= ck804_early_setup_x(); + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } - allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid); - nodes = get_nodes(); - //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus();

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coreboot-gerrit September 2016