coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mainboard/supermicro/h8dmr/romstage.c: Use tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16775 -gerrit commit c49908d69f88238349342c59054890bfe19b3bb7 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 21:22:54 2016 +0200 mainboard/supermicro/h8dmr/romstage.c: Use tabs for indents Change-Id: I008ccc5fa9d96e52ee59a4562d81e4f7c1d1a6ac Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/supermicro/h8dmr/romstage.c | 120 +++++++++++++++--------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index b137b6b..a7e69bd 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -65,24 +65,24 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + uint32_t dword; + uint8_t byte; - enable_smbus(); + enable_smbus(); // smbusx_write_byte(1, (0x58 >> 1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1 << 0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1 << 0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1 << 16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1 << 16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -96,90 +96,90 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = &sysinfo_car; - int needs_reset = 0; - unsigned bsp_apicid = 0; + struct sys_info *sysinfo = &sysinfo_car; + int needs_reset = 0; + unsigned bsp_apicid = 0; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + } - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); w83627hf_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - setup_mb_resource_map(); + setup_mb_resource_map(); - printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram - setup_coherent_ht_domain(); // routing table and start other core0 + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + setup_coherent_ht_domain(); // routing table and start other core0 - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif - /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr = rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); - } + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr = rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); + } #endif init_timer(); // Need to use TMICT to synchronize FID/VID - needs_reset |= optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - needs_reset |= mcp55_early_setup_x(); + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= mcp55_early_setup_x(); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\n"); - soft_reset(); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\n"); + soft_reset(); + } - allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); // enable_smbus(); /* enable in sio_setup */ - /* all ap stopped? */ + /* all ap stopped? */ - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now }

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New patch to review for coreboot: mainboard/supermicro/h8qme_fam10/romstage.c: Use tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16774 -gerrit commit 33c6e87bcc024cae15456d8131a0a688d7210cfb Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 21:11:57 2016 +0200 mainboard/supermicro/h8qme_fam10/romstage.c: Use tabs for indents Change-Id: I6ca564294ff3d8eaeae21c0e2c008401aa3f32ff Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/supermicro/h8qme_fam10/romstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index f82ddd1..16f0d8a 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -172,17 +172,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - } + } post_code(0x30); - if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); post_code(0x32);

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Patch set updated for coreboot: mainboard/asus/dsbf/romstage.c: Use tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16773 -gerrit commit f327c4b8f67f73af2515e375ad9900475fb835e5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 20:59:00 2016 +0200 mainboard/asus/dsbf/romstage.c: Use tabs for indents Change-Id: I74d4ef76b8166c8567b1b855c6bc963b4312df77 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/asus/dsbf/romstage.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index 45ca046..273b6d2 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -75,13 +75,13 @@ static void setup_gpio(void) pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); - outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ + outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ } @@ -126,12 +126,12 @@ void mainboard_romstage_entry(unsigned long bist) enable_smbus(); - smbus_write_byte(0x6f, 0x00, 0x63); - smbus_write_byte(0x6f, 0x01, 0x04); - smbus_write_byte(0x6f, 0x02, 0x53); - smbus_write_byte(0x6f, 0x03, 0x39); - smbus_write_byte(0x6f, 0x08, 0x06); - smbus_write_byte(0x6f, 0x09, 0x00); + smbus_write_byte(0x6f, 0x00, 0x63); + smbus_write_byte(0x6f, 0x01, 0x04); + smbus_write_byte(0x6f, 0x02, 0x53); + smbus_write_byte(0x6f, 0x03, 0x39); + smbus_write_byte(0x6f, 0x08, 0x06); + smbus_write_byte(0x6f, 0x09, 0x00); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); i5000_fbdimm_init();

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New patch to review for coreboot: mainboard/asus/dsbf/romstage.c: Use tabs for indentsUse tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16773 -gerrit commit 8b4420c808d414ba738f1e063c03464710baa91f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 20:59:00 2016 +0200 mainboard/asus/dsbf/romstage.c: Use tabs for indentsUse tabs for indents Change-Id: I74d4ef76b8166c8567b1b855c6bc963b4312df77 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/asus/dsbf/romstage.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index 45ca046..273b6d2 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -75,13 +75,13 @@ static void setup_gpio(void) pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); - outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ + outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ } @@ -126,12 +126,12 @@ void mainboard_romstage_entry(unsigned long bist) enable_smbus(); - smbus_write_byte(0x6f, 0x00, 0x63); - smbus_write_byte(0x6f, 0x01, 0x04); - smbus_write_byte(0x6f, 0x02, 0x53); - smbus_write_byte(0x6f, 0x03, 0x39); - smbus_write_byte(0x6f, 0x08, 0x06); - smbus_write_byte(0x6f, 0x09, 0x00); + smbus_write_byte(0x6f, 0x00, 0x63); + smbus_write_byte(0x6f, 0x01, 0x04); + smbus_write_byte(0x6f, 0x02, 0x53); + smbus_write_byte(0x6f, 0x03, 0x39); + smbus_write_byte(0x6f, 0x08, 0x06); + smbus_write_byte(0x6f, 0x09, 0x00); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); i5000_fbdimm_init();

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New patch to review for coreboot: mainboard/intel/emeraldlake2/gpio.c: Use tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16772 -gerrit commit 99fb32d0318b890869ef3fd2f90b5fc2815d6fda Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 20:52:06 2016 +0200 mainboard/intel/emeraldlake2/gpio.c: Use tabs for indents Change-Id: I369c2063a5e57d1fd33d3c6bf7c715c22970fc32 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/intel/emeraldlake2/gpio.c | 56 ++++++++++++++++----------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/gpio.c b/src/mainboard/intel/emeraldlake2/gpio.c index 050d44e..36c52e3 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.c +++ b/src/mainboard/intel/emeraldlake2/gpio.c @@ -19,35 +19,35 @@ #include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, - .gpio1 = GPIO_MODE_GPIO, - .gpio3 = GPIO_MODE_GPIO, - .gpio5 = GPIO_MODE_GPIO, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_GPIO, - .gpio12 = GPIO_MODE_GPIO, - .gpio15 = GPIO_MODE_GPIO, - .gpio21 = GPIO_MODE_GPIO, + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, .gpio22 = GPIO_MODE_GPIO, - .gpio24 = GPIO_MODE_GPIO, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, }; const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, .gpio22 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, }; const struct pch_gpio_set1 pch_gpio_set1_level = { @@ -57,15 +57,15 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { }; const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, .gpio48 = GPIO_MODE_GPIO, - .gpio57 = GPIO_MODE_GPIO, - .gpio60 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, }; const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio48 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, }; const struct pch_gpio_set2 pch_gpio_set2_level = {

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New patch to review for coreboot: mainboard/intel/eagleheights/debug.c: Use tabs for indents
by HAOUAS Elyes 27 Sep '16

27 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16771 -gerrit commit 510202c50502330cefc90c3c0c24089e2675da61 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Sep 27 20:40:06 2016 +0200 mainboard/intel/eagleheights/debug.c: Use tabs for indents Change-Id: I4d2d876d48e018c247e7f365f7c237a4d8ced332 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/intel/eagleheights/debug.c | 186 +++++++++++++++---------------- 1 file changed, 93 insertions(+), 93 deletions(-) diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index 79ca0a4..c380795 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -19,104 +19,104 @@ static void print_reg(unsigned char index) { - unsigned char data; + unsigned char data; - outb(index, 0x2e); - data = inb(0x2f); + outb(index, 0x2e); + data = inb(0x2f); printk(BIOS_DEBUG, "0x%02x: 0x%02x\n", index, data); - return; + return; } static inline void xbus_en(void) { - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); return; } static void setup_func(unsigned char func) { - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; } static inline void siodump(void) { - int i; - unsigned char data; + int i; + unsigned char data; printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n"); - for (i = 0x10; i <= 0x2d; i++) { - print_reg((unsigned char)i); - } + for (i = 0x10; i <= 0x2d; i++) { + print_reg((unsigned char)i); + } #if 0 - printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i = 0xf0; i <= 0xff; i++) { - print_reg((unsigned char)i); - } + printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n"); + setup_func(0x0f); + for (i = 0xf0; i <= 0xff; i++) { + print_reg((unsigned char)i); + } - printk(BIOS_DEBUG, "\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); + printk(BIOS_DEBUG, "\n*** SERIAL 1 CONFIG REGISTERS ***\n"); + setup_func(0x03); + print_reg(0xf0); - printk(BIOS_DEBUG, "\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); + printk(BIOS_DEBUG, "\n*** SERIAL 2 CONFIG REGISTERS ***\n"); + setup_func(0x02); + print_reg(0xf0); #endif - printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i = 0xf0; i <= 0xf8; i++) { - print_reg((unsigned char)i); - } - printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n"); - data = inb(0x68a); + printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n"); + setup_func(0x07); + for (i = 0xf0; i <= 0xf8; i++) { + print_reg((unsigned char)i); + } + printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n"); + data = inb(0x68a); printk(BIOS_DEBUG, "\nGPDO 4: 0x%02x", data); - data = inb(0x68b); + data = inb(0x68b); printk(BIOS_DEBUG, "\nGPDI 4: 0x%02x\n", data); #if 0 - printk(BIOS_DEBUG, "\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); - - printk(BIOS_DEBUG, "\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); - - printk(BIOS_DEBUG, "\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); - - printk(BIOS_DEBUG, "\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); + printk(BIOS_DEBUG, "\n*** WATCHDOG TIMER REGISTERS ***\n"); + setup_func(0x0a); + print_reg(0xf0); + + printk(BIOS_DEBUG, "\n*** FAN CONTROL REGISTERS ***\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1); + + printk(BIOS_DEBUG, "\n*** RTC REGISTERS ***\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff); + + printk(BIOS_DEBUG, "\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); + setup_func(0x14); + print_reg(0xf0); #endif - return; + return; } static inline void dump_bar14(unsigned dev) @@ -143,20 +143,20 @@ static inline void dump_bar14(unsigned dev) static inline void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - printk(BIOS_DEBUG, "\ndimm %02x", device); - - for(i = 0; (i < 256) ; i++) { - if ((i % 16) == 0) + unsigned device; + device = DIMM0; + while(device <= DIMM7) { + int status = 0; + int i; + printk(BIOS_DEBUG, "\ndimm %02x", device); + + for(i = 0; (i < 256) ; i++) { + if ((i % 16) == 0) printk(BIOS_DEBUG, "\n%02x: ", i); status = smbus_read_byte(device, i); - if (status < 0) { - printk(BIOS_DEBUG, "bad device: %d\n", -status); - break; + if (status < 0) { + printk(BIOS_DEBUG, "bad device: %d\n", -status); + break; } printk(BIOS_DEBUG, "%02x ", status); } @@ -167,18 +167,18 @@ static inline void dump_spd_registers(void) static inline void dump_ipmi_registers(void) { - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - printk(BIOS_DEBUG, "\nipmi %02x", device); - - for(i = 0; (i < 8) ; i++) { + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + printk(BIOS_DEBUG, "\nipmi %02x", device); + + for(i = 0; (i < 8) ; i++) { status = smbus_read_byte(device, 2); - if (status < 0) { - printk(BIOS_DEBUG, "bad device: %d\n", -status); - break; + if (status < 0) { + printk(BIOS_DEBUG, "bad device: %d\n", -status); + break; } printk(BIOS_DEBUG, "%02x ", status); }

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Patch merged into coreboot/master: northbridge/sandybridge/raminit_mrc.c: fix missing include
by gerrit＠coreboot.org 27 Sep '16

27 Sep '16

the following patch was just integrated into master: commit f9c41974cd20a392125932c3376c4dfc20455331 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Fri Sep 23 19:40:54 2016 -0500 northbridge/sandybridge/raminit_mrc.c: fix missing include Compilation (w/o native raminit) fails due to missing include Change-Id: Ic79a77006257b32e0181c88c4e24d7c1f5c5f7ce Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/16735 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16735 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/msi/ms9185/resourcemap.c: Use tabs for indents
by gerrit＠coreboot.org 27 Sep '16

27 Sep '16

the following patch was just integrated into master: commit a6b863a2bcac77cfa3e74df23416b73faadc5232 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Sep 25 15:31:41 2016 +0200 mainboard/msi/ms9185/resourcemap.c: Use tabs for indents Change-Id: I30b5830442da65ae3ddd35e8bca67795c34e9020 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16737 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16737 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/msi/ms9185/romstage: Use tabs for indents
by gerrit＠coreboot.org 27 Sep '16

27 Sep '16

the following patch was just integrated into master: commit 99a92ac7222aa0469c3e6462272105bbf3de0526 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Sep 25 15:21:37 2016 +0200 mainboard/msi/ms9185/romstage: Use tabs for indents Change-Id: I101462105da31654032ac7e6abd3f9423ad7a7ef Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16736 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16736 for details. -gerrit

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Patch set updated for coreboot: rockchip/rk3399: select rank before triggering training
by Patrick Georgi 27 Sep '16

27 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16768 -gerrit commit 431e3453651a144fa71615f3294d05ef54d712a3 Author: Derek Basehore <dbasehore(a)chromium.org> Date: Wed Sep 21 15:43:36 2016 -0700 rockchip/rk3399: select rank before triggering training This selects the rank to train before training is triggered. This is to prevent any race conditions with the hardware. BRANCH=none BUG=chrome-os-partner:56940 TEST=stressapptest -M 1536 -s 1000 Change-Id: I892bace414cf4495619d41bdaea0c4e91c1e29b3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8f2dd6f52978a9e54ddd2688eb68fd237aabfe2d Original-Change-Id: I4e7118d8509b59e391d0a254477b5390dfdd43a5 Original-Signed-off-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/387907 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: 云平汤 <typ(a)rock-chips.com> --- src/soc/rockchip/rk3399/sdram.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 1021c6b..42b2574 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -685,15 +685,14 @@ static int data_training(u32 channel, /* ca training(LPDDR4,LPDDR3 support) */ if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_100 PI_CALVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); - /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ clrsetbits_le32(&denali_pi[92], (0x1 << 16) | (0x3 << 24), (0x1 << 16) | (i << 24)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -726,6 +725,7 @@ static int data_training(u32 channel, /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_60 PI_WRLVL_EN:RW:8:2 */ clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ @@ -733,7 +733,6 @@ static int data_training(u32 channel, (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -772,6 +771,7 @@ static int data_training(u32 channel, /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); /* @@ -782,7 +782,6 @@ static int data_training(u32 channel, (0x1 << 16) | (0x3 << 24), (0x1 << 16) | (i << 24)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -818,6 +817,7 @@ static int data_training(u32 channel, /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_EN:RW:16:2 */ clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ @@ -825,7 +825,6 @@ static int data_training(u32 channel, (0x1 << 8) | (0x3 << 24), (0x1 << 8) | (i << 24)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8; @@ -850,6 +849,7 @@ static int data_training(u32 channel, /* wdq leveling(LPDDR4 support) */ if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { for (i = 0; i < rank; i++) { + select_per_cs_training_index(channel, i); /* * disable PI_WDQLVL_VREF_EN before wdq leveling? * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 @@ -862,7 +862,6 @@ static int data_training(u32 channel, (0x1 << 8) | (0x3 << 16), (0x1 << 8) | (i << 16)); - select_per_cs_training_index(channel, i); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ tmp = read32(&denali_pi[174]) >> 8;

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coreboot-gerrit September 2016