Patch set updated for coreboot: rockchip/rk3399: select rank before triggering training

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16768

-gerrit

commit 431e3453651a144fa71615f3294d05ef54d712a3
Author: Derek Basehore <[e-mail]>
Date:   Wed Sep 21 15:43:36 2016 -0700

    rockchip/rk3399: select rank before triggering training
    
    This selects the rank to train before training is triggered. This is
    to prevent any race conditions with the hardware.
    
    BRANCH=none
    BUG=chrome-os-partner:56940
    TEST=stressapptest -M 1536 -s 1000
    
    Change-Id: I892bace414cf4495619d41bdaea0c4e91c1e29b3
    Signed-off-by: Patrick Georgi <[e-mail]>
    Original-Commit-Id: 8f2dd6f52978a9e54ddd2688eb68fd237aabfe2d
    Original-Change-Id: I4e7118d8509b59e391d0a254477b5390dfdd43a5
    Original-Signed-off-by: Derek Basehore <[e-mail]>
    Original-Reviewed-on: https://chromium-review.googlesource.com/387907
    Original-Commit-Ready: Douglas Anderson <[e-mail]>
    Original-Tested-by: Douglas Anderson <[e-mail]>
    Original-Reviewed-by: Douglas Anderson <[e-mail]>
    Original-Reviewed-by: Julius Werner <[e-mail]>
    Original-Reviewed-by: 云平 汤 <[e-mail]>
---
 src/soc/rockchip/rk3399/sdram.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 1021c6b..42b2574 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -685,15 +685,14 @@ static int data_training(u32 channel,
 	/* ca training(LPDDR4,LPDDR3 support) */
 	if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
 		for (i = 0; i < rank; i++) {
+			select_per_cs_training_index(channel, i);
 			/* PI_100 PI_CALVL_EN:RW:8:2 */
 			clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
-
 			/* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
 			clrsetbits_le32(&denali_pi[92],
 					(0x1 << 16) | (0x3 << 24),
 					(0x1 << 16) | (i << 24));
 
-			select_per_cs_training_index(channel, i);
 			while (1) {
 				/* PI_174 PI_INT_STATUS:RD:8:18 */
 				tmp = read32(&denali_pi[174]) >> 8;
@@ -726,6 +725,7 @@ static int data_training(u32 channel,
 	/* write leveling(LPDDR4,LPDDR3,DDR3 support) */
 	if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
 		for (i = 0; i < rank; i++) {
+			select_per_cs_training_index(channel, i);
 			/* PI_60 PI_WRLVL_EN:RW:8:2 */
 			clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
 			/* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
@@ -733,7 +733,6 @@ static int data_training(u32 channel,
 					(0x1 << 8) | (0x3 << 16),
 					(0x1 << 8) | (i << 16));
 
-			select_per_cs_training_index(channel, i);
 			while (1) {
 				/* PI_174 PI_INT_STATUS:RD:8:18 */
 				tmp = read32(&denali_pi[174]) >> 8;
@@ -772,6 +771,7 @@ static int data_training(u32 channel,
 	/* read gate training(LPDDR4,LPDDR3,DDR3 support) */
 	if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
 		for (i = 0; i < rank; i++) {
+			select_per_cs_training_index(channel, i);
 			/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
 			clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
 			/*
@@ -782,7 +782,6 @@ static int data_training(u32 channel,
 					(0x1 << 16) | (0x3 << 24),
 					(0x1 << 16) | (i << 24));
 
-			select_per_cs_training_index(channel, i);
 			while (1) {
 				/* PI_174 PI_INT_STATUS:RD:8:18 */
 				tmp = read32(&denali_pi[174]) >> 8;
@@ -818,6 +817,7 @@ static int data_training(u32 channel,
 	/* read leveling(LPDDR4,LPDDR3,DDR3 support) */
 	if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
 		for (i = 0; i < rank; i++) {
+			select_per_cs_training_index(channel, i);
 			/* PI_80 PI_RDLVL_EN:RW:16:2 */
 			clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
 			/* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
@@ -825,7 +825,6 @@ static int data_training(u32 channel,
 					(0x1 << 8) | (0x3 << 24),
 					(0x1 << 8) | (i << 24));
 
-			select_per_cs_training_index(channel, i);
 			while (1) {
 				/* PI_174 PI_INT_STATUS:RD:8:18 */
 				tmp = read32(&denali_pi[174]) >> 8;
@@ -850,6 +849,7 @@ static int data_training(u32 channel,
 	/* wdq leveling(LPDDR4 support) */
 	if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
 		for (i = 0; i < rank; i++) {
+			select_per_cs_training_index(channel, i);
 			/*
 			 * disable PI_WDQLVL_VREF_EN before wdq leveling?
 			 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
@@ -862,7 +862,6 @@ static int data_training(u32 channel,
 					(0x1 << 8) | (0x3 << 16),
 					(0x1 << 8) | (i << 16));
 
-			select_per_cs_training_index(channel, i);
 			while (1) {
 				/* PI_174 PI_INT_STATUS:RD:8:18 */
 				tmp = read32(&denali_pi[174]) >> 8;