coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: soc/intel/quark: Fix FSP 2.0 build
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit 44ec92a48d4dd40f9cca2da66e875d0665b57215 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 17:16:44 2016 -0700 soc/intel/quark: Fix FSP 2.0 build Fix the build issues with FSP 2.0: * Remove struct from the various data structures. * Properly display the serial port UPDs. * Change chipset_handle_reset parameter type BRANCH=none BUG=None TEST=Build FSP 2.0 (SEC/PEI core with all FSP debug off) and run on Galileo Gen2 Change-Id: Icae578855006f18e7e5aa18d2fd196d300d0c658 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/16808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16808 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/quark: Support multiple version of FSP
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit 54f857b29e7d7fddf4ad2c13a16f624e25349456 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 18:03:13 2016 -0700 soc/intel/quark: Support multiple version of FSP Add support for multiple versions of FSP. BRANCH=none BUG=None TEST=Build FSP 1.1 (SEC/PEI core, with all FSP debug off) and run on Galileo Gen2 Change-Id: Ie7e7f0f883c4d3bfcb18fa25571e505cdde00b2d Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/16807 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16807 for details. -gerrit

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Patch merged into coreboot/master: mainboard/intel/quark: Add FSP selection values
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit e1654235fd941b4a4cfb5f75325fe0a496a24c5f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Sep 28 14:10:06 2016 -0700 mainboard/intel/quark: Add FSP selection values Add Kconfig values to select the FSP setup: * FSP version: 1.1 or 2.0 * Implementation: Subroutine or SEC/PEI core based * Build type: DEBUG or RELEASE * Enable all debugging for FSP * Remove USE_FSP1_1 and USE_FSP2_0 Look for include files in vendorcode/intel/fsp/fsp???/quark BRANCH=none BUG=None TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2 Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/16806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16806 for details. -gerrit

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Patch merged into coreboot/master: mainboard/asus/kfsn4-dre_k8/romstage.c: Use tabs for indents
by gerrit＠coreboot.org 29 Sep '16

29 Sep '16

the following patch was just integrated into master: commit 127b5d1270fc3c7ea8be7c80670be8dcd9ea4147 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 28 21:41:06 2016 +0200 mainboard/asus/kfsn4-dre_k8/romstage.c: Use tabs for indents Change-Id: If6b36ebef49dd2733d272f990bb7c6623d4ab1b1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16785 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16785 for details. -gerrit

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Patch merged into coreboot/master: mainboard/via/epia-m850/romstage.c: Remove unnecessary whitespace
by gerrit＠coreboot.org 29 Sep '16

29 Sep '16

the following patch was just integrated into master: commit 0c31a677b0dbc17b0909a5f6d5f0ab31294bd36b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 28 21:24:40 2016 +0200 mainboard/via/epia-m850/romstage.c: Remove unnecessary whitespace Change-Id: Ic5359f794c64a9a67ec9e059af337a65073baff4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16784 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16784 for details. -gerrit

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Patch merged into coreboot/master: mainboard/lanner/em8510: Use tabs for indents
by gerrit＠coreboot.org 29 Sep '16

29 Sep '16

the following patch was just integrated into master: commit aabd7203a8dd2874a12667f6e44bf6c4c3e5e70f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 28 21:10:08 2016 +0200 mainboard/lanner/em8510: Use tabs for indents Change-Id: Ib6191c590144438d7d9d6772d792a83e92d5516a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16783 for details. -gerrit

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Patch merged into coreboot/master: mainboard/iwill/dk8_htx: Use tabs for indents
by gerrit＠coreboot.org 29 Sep '16

29 Sep '16

the following patch was just integrated into master: commit 0e505f1bfe921b6fd9c4a8e7289f9ab0a29a20f4 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 28 19:56:00 2016 +0200 mainboard/iwill/dk8_htx: Use tabs for indents Change-Id: I303270a45171dda88b7661e3797fd3724e3b055f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16782 for details. -gerrit

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New patch to review for coreboot: google/reef: Fix default values in Kconfig
by Martin Roth 29 Sep '16

29 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16828 -gerrit commit cc189037acf8a2ff48bb845676edd48700515f8f Author: Martin Roth <martinroth(a)google.com> Date: Thu Sep 29 15:10:37 2016 -0600 google/reef: Fix default values in Kconfig These default values weren't being set with the default keyword so were ending up with different values. from the default generated config file before this change: CONFIG_DRIVER_TPM_I2C_BUS=0x9 CONFIG_DRIVER_TPM_I2C_ADDR=0x2 CONFIG_DRIVER_TPM_I2C_IRQ=-1 Change-Id: I19514d0c9b2a9b7e479f003a4d3384e073f4d531 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/reef/Kconfig | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5039725..bd3f466 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -20,13 +20,16 @@ config BASEBOARD_REEF_LAPTOP select SYSTEM_TYPE_LAPTOP config DRIVER_TPM_I2C_BUS - hex "0x2" + hex + default 0x2 config DRIVER_TPM_I2C_ADDR - hex "0x50" + hex + default 0x50 config DRIVER_TPM_I2C_IRQ - int "60" # GPE0_DW1_28 + int + default 60 # GPE0_DW1_28 config CHROMEOS select LID_SWITCH if BASEBOARD_REEF_LAPTOP

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New patch to review for coreboot: Kconfig: Prefix hex defaults with 0x
by Martin Roth 29 Sep '16

29 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16827 -gerrit commit 383a995e861651c26663740dba84dacf4f609ce2 Author: Martin Roth <martinroth(a)google.com> Date: Thu Sep 29 14:46:24 2016 -0600 Kconfig: Prefix hex defaults with 0x Because these variables had "non-hexidecimal" defaults, they were updated by kconfig when writing defconfig files. Change-Id: Ic1a070d340708f989157ad18ddc79de7bb92d873 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/intel/fsp1_1/Kconfig | 4 ++-- src/drivers/uart/Kconfig | 2 +- src/mainboard/google/daisy/Kconfig | 2 +- src/mainboard/google/smaug/Kconfig | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 17a5caf..306e09b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -34,13 +34,13 @@ config HAVE_FSP_BIN config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" - default 0 + default 0x0 help The length in bytes of the microcode update region. config CPU_MICROCODE_CBFS_LOC hex "Microcode update base address in CBFS" - default 0 + default 0x0 help The location (base address) in CBFS that contains the microcode update binary. diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 4faa48d..698564e 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -65,7 +65,7 @@ config UART_USE_REFCLK_AS_INPUT_CLOCK config UART_PCI_ADDR hex "UART's PCI bus, device, function address" - default 0 + default 0x0 help Specify zero if the UART is connected to another bus type. For PCI based UARTs, build the value as: diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index cef3f61..29d6690 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -49,7 +49,7 @@ config DRAM_SIZE_MB config EC_GOOGLE_CHROMEEC_I2C_BUS hex - default 4 + default 0x4 config UART_FOR_CONSOLE int diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index 15ff2b3..6655453 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -85,7 +85,7 @@ config DRIVER_TPM_I2C_ADDR config EC_GOOGLE_CHROMEEC_I2C_BUS hex - default 1 + default 0x1 config EC_GOOGLE_CHROMEEC_BOARDNAME string

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New patch to review for coreboot: Documentation/Intel/Soc: Update Quark FSP build instructions
by Lee Leahy 29 Sep '16

29 Sep '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16826 -gerrit commit d022320f6048e9ca2f088437569d9c255afc62c8 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Sep 29 13:56:28 2016 -0700 Documentation/Intel/Soc: Update Quark FSP build instructions Update the FSP build instructions for Quark: * Discuss multiple types BRANCH=none BUG=None TEST=Build Quark FSP using new instructions Change-Id: Ibc4bfe32d0eb3877d3b988bc185c73be58d44878 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- Documentation/Intel/SoC/quark.html | 47 +++++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index 61abebd..9c180da 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -130,14 +130,55 @@ Getting the Quark FSP source: <li>Use git to clone <a target="_blank" href="https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp">QuarkFspPkg</a> into the QuarkFpsPkg directory (.)</li> </ol> +<h2>Building QuarkFspPkg</h2> <p> -Building QuarkFspPkg: +There are two versions of FSP: FSP 1.1 and FSP 2.0. There are also two +different implementations of FSP, one using subroutines without SEC and +PEI core and the original implementation which relies on SEC and PEI core. +Finally there are two different build x86 types release (r32) and debug (d32). +</p> +<p>Note that the subroutine implementations are a <b>work in progress</b>.</p> +<p> +Build commands shown building debug FSP: </p> <ul> - <li>Linux: QuarkFspPkg/BuildFsp.sh -d32</li> - <li>Windows: QuarkFspPkg/BuildFsp.bat -d32</li> + <li>Linux: + <ul> + <li>QuarkFspPkg/BuildFsp1_1.sh -d32</li> + <li>QuarkFspPkg/BuildFsp1_1Pei.sh -d32</li> + <li>QuarkFspPkg/BuildFsp2_0.sh -d32</li> + <li>QuarkFspPkg/BuildFsp2_0Pei.sh -d32</li> + </ul> + <li>Windows: + <ul> + <li>QuarkFspPkg/BuildFsp1_1.bat -d32</li> + <li>Windows: QuarkFspPkg/BuildFsp2_0.bat -d32</li> + </ul> + </li> </ul> +<h2>Copying FSP files into coreboot Source Tree</h2> +<p> +There are some helper scripts to copy the FSP output into the coreboot +source tree. The parameters to these scripts are: +</p> +<ol> + <li>EDK2 tree root</li> + <li>coreboot tree root</li> + <li>Build type: DEBUG or RELEASE</li> +</ol> +<p> +Script files: +</p> +<ul> + <li>Linux: + <ul> + <li>QuarkFspPkg/coreboot_fsp1_1.sh</li> + <li>QuarkFspPkg/coreboot_fsp1_1Pei.sh</li> + <li>QuarkFspPkg/coreboot_fsp2_0.sh</li> + <li>QuarkFspPkg/coreboot_fsp2_0Pei.sh</li> + </ul> +</ul> <hr>

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coreboot-gerrit September 2016