coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: Provide CAR decoration for tpm2 statics
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16366 -gerrit commit 487d435ec1a173ae5bdd7396d170a740c0442e47 Author: Victor Prupis <vprupis(a)google.com> Date: Fri Aug 19 10:45:04 2016 -0700 Provide CAR decoration for tpm2 statics Decorated tpm2 statics with CAR_GLOBAL BUG=chrome-os-partner:55083 BRANCH=none TEST=none Change-Id: I85620d5c6ffddab5514c01c2c652670bf33b4e7e Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: ae43d3bb7fed5b891ed38cd268bfe4e1416b77e2 Original-Change-Id: I871442ec096836a86870f8d53a3058c9c040cff8 Original-Signed-off-by: Victor Prupis <vprupis(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/373243 Original-Commit-Ready: Stefan Reinauer <reinauer(a)google.com> Original-Tested-by: Stefan Reinauer <reinauer(a)google.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/tpm2_marshaling.c | 11 +++++++---- src/lib/tpm2_tlcl.c | 13 ++++++++----- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/lib/tpm2_marshaling.c b/src/lib/tpm2_marshaling.c index ab9a928..f4fd3cb 100644 --- a/src/lib/tpm2_marshaling.c +++ b/src/lib/tpm2_marshaling.c @@ -4,6 +4,7 @@ * found in the LICENSE file. */ +#include <arch/early_variables.h> #include <commonlib/endian.h> #include <console/console.h> #include <stdlib.h> @@ -11,7 +12,7 @@ #include "tpm2_marshaling.h" -static uint16_t tpm_tag; /* Depends on the command type. */ +static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ /* * Each unmarshaling function receives a pointer to the buffer pointer and a @@ -268,7 +269,7 @@ static void marshal_common_session_header(void **buffer, int i; struct tpm2_session_header session_header; - tpm_tag = TPM_ST_SESSIONS; + car_set_var(tpm_tag, TPM_ST_SESSIONS); for (i = 0; i < handle_count; i++) marshal_TPM_HANDLE(buffer, handles[i], buffer_space); @@ -380,7 +381,7 @@ int tpm_marshal_command(TPM_CC command, void *tpm_command_body, size_t body_size = max_body_size; /* Will be modified when marshaling some commands. */ - tpm_tag = TPM_ST_NO_SESSIONS; + car_set_var(tpm_tag, TPM_ST_NO_SESSIONS); switch (command) { case TPM2_Startup: @@ -437,7 +438,9 @@ int tpm_marshal_command(TPM_CC command, void *tpm_command_body, /* Total size includes the header size. */ marshaled_size += sizeof(struct tpm_header); - marshal_u16(&buffer, tpm_tag, &header_room); + uint16_t tpm_tag_value = car_get_var(tpm_tag); + + marshal_u16(&buffer, tpm_tag_value, &header_room); marshal_u32(&buffer, marshaled_size, &header_room); marshal_u32(&buffer, command, &header_room); return marshaled_size; diff --git a/src/lib/tpm2_tlcl.c b/src/lib/tpm2_tlcl.c index c8e7e90..7bfd40d 100644 --- a/src/lib/tpm2_tlcl.c +++ b/src/lib/tpm2_tlcl.c @@ -4,6 +4,7 @@ * found in the LICENSE file. */ +#include <arch/early_variables.h> #include <console/console.h> #include <endian.h> #include <lib/tpm2_tlcl_structures.h> @@ -24,10 +25,12 @@ static void *tpm_process_command(TPM_CC command, void *command_body) ssize_t out_size; size_t in_size; /* Command/response buffer. */ - static uint8_t cr_buffer[TPM_BUFFER_SIZE]; + static uint8_t cr_buffer[TPM_BUFFER_SIZE] CAR_GLOBAL; + + uint8_t *cr_buffer_ptr = car_get_var_ptr(cr_buffer); out_size = tpm_marshal_command(command, command_body, - cr_buffer, sizeof(cr_buffer)); + cr_buffer_ptr, sizeof(cr_buffer)); if (out_size < 0) { printk(BIOS_ERR, "command %#x, cr size %zd\n", command, out_size); @@ -35,13 +38,13 @@ static void *tpm_process_command(TPM_CC command, void *command_body) } in_size = sizeof(cr_buffer); - if (tis_sendrecv(cr_buffer, out_size, - cr_buffer, &in_size)) { + if (tis_sendrecv(cr_buffer_ptr, out_size, + cr_buffer_ptr, &in_size)) { printk(BIOS_ERR, "tpm transaction failed\n"); return NULL; } - return tpm_unmarshal_response(command, cr_buffer, in_size); + return tpm_unmarshal_response(command, cr_buffer_ptr, in_size); }

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New patch to review for coreboot: ps8640: disable mipi mcs
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16365 -gerrit commit d56f375f5c978c49cda2932bbeb27e95c2cfb8ed Author: Jitao Shi <jitao.shi(a)mediatek.com> Date: Fri Aug 19 16:00:01 2016 +0800 ps8640: disable mipi mcs Disable ps8640 mipi mcs function to avoid recognizing the normal mipi dsi signal as msc cmd. BUG=chrome-os-partner:56346 BRANCH=none TEST=build pass elm and show ui Change-Id: I91c690fb1ff3bd9b5c1f227205829c914347cd30 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 4fd441b46300fea9f238b27c9c1cda4e9e53c80d Original-Change-Id: I85b9f1e6677e4bf8ab1e30c2e69445079fff2d18 Original-Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/373219 Original-Commit-Ready: Daniel Kurtz <djkurtz(a)chromium.org> Original-Tested-by: jitao shi <jitao.shi(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz(a)chromium.org> --- src/drivers/parade/ps8640/ps8640.c | 10 ++++++++++ src/drivers/parade/ps8640/ps8640.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c index c26c6ef..f636f70 100644 --- a/src/drivers/parade/ps8640/ps8640.c +++ b/src/drivers/parade/ps8640/ps8640.c @@ -76,6 +76,16 @@ int ps8640_init(uint8_t bus, uint8_t chip) } mdelay(50); + + /** + * The Manufacturer Command Set (MCS) is a device dependent interface + * intended for factory programming of the display module default + * parameters. Once the display module is configured, the MCS shall be + * disabled by the manufacturer. Once disabled, all MCS commands are + * ignored by the display interface. + */ + i2c_write_field(bus, chip + 2, PAGE2_MCS_EN, 0x0, MCS_EN_MASK, + MCS_EN_SHIFT); i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD); i2c_writeb(bus, chip + 3, PAGE3_SET_VAL, VDO_DIS); i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD); diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h index f7b4006..4540122 100644 --- a/src/drivers/parade/ps8640/ps8640.h +++ b/src/drivers/parade/ps8640/ps8640.h @@ -26,6 +26,9 @@ enum { PS_GPIO9 = BIT(1), I2C_BYPASS_EN = BIT(7), + PAGE2_MCS_EN = 0xf3, + MCS_EN_SHIFT = 0, + MCS_EN_MASK = 0x1, PAGE3_SET_ADD = 0xfe, PAGE3_SET_VAL = 0xff, VDO_CTL_ADD = 0x13,

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New patch to review for coreboot: ps8640: add delay every loop when polling ps8640 ready
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16364 -gerrit commit 0ecba8901063e9c1e1339d814032db1df92d7e75 Author: Jitao Shi <jitao.shi(a)mediatek.com> Date: Wed Aug 17 10:21:37 2016 +0800 ps8640: add delay every loop when polling ps8640 ready Add delay before and in polling ps8640 ready to reduce the frequency of polling. BUG=chrome-os-partner:54897 BRANCH=none TEST=build pass elm and show ui Change-Id: I43c833af910490e53496a343330a6a6af35623a9 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: bc8c3d6f7cf0b2da693a465cf3845e8bbc53825a Original-Change-Id: I5c725eed8110ff9f545c1142ca28bcff336b6860 Original-Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/371718 Original-Commit-Ready: Nicolas Boichat <drinkcat(a)chromium.org> Original-Tested-by: jitao shi <jitao.shi(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz(a)chromium.org> --- src/drivers/parade/ps8640/ps8640.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c index 884b46af..c26c6ef 100644 --- a/src/drivers/parade/ps8640/ps8640.c +++ b/src/drivers/parade/ps8640/ps8640.c @@ -60,16 +60,22 @@ int ps8640_init(uint8_t bus, uint8_t chip) u8 set_vdo_done; struct stopwatch sw; - stopwatch_init_msecs_expire(&sw, 350); + mdelay(200); + stopwatch_init_msecs_expire(&sw, 200); - do { + while (true) { i2c_readb(bus, chip + 2, PAGE2_GPIO_H, &set_vdo_done); + if ((set_vdo_done & PS_GPIO9) == PS_GPIO9) + break; if (stopwatch_expired(&sw)) { printk(BIOS_INFO, "Failed to init ps8640.\n"); return -1; } - } while ((set_vdo_done & PS_GPIO9) != PS_GPIO9); + mdelay(20); + } + + mdelay(50); i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD); i2c_writeb(bus, chip + 3, PAGE3_SET_VAL, VDO_DIS); i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD);

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New patch to review for coreboot: mainboard/*/Kconfig: Set GBB_HWID where missing
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16363 -gerrit commit 12d04db59e132ca27418a8de2f60bdf2ae916c95 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Thu Aug 18 11:22:28 2016 +0200 mainboard/*/Kconfig: Set GBB_HWID where missing Provide GBB's hardware ID (used on Chrome OS devices) because it will be dropped from depthcharge. BRANCH=none BUG=none TEST=none Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00 Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/372579 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/gale/Kconfig | 5 +++++ src/mainboard/google/reef/Kconfig | 5 +++++ src/mainboard/intel/amenia/Kconfig | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig index b839fb4..5b960cd 100644 --- a/src/mainboard/google/gale/Kconfig +++ b/src/mainboard/google/gale/Kconfig @@ -49,6 +49,11 @@ config MAINBOARD_PART_NUMBER default "DK01" if BOARD_VARIANT_DK01 default "Gale" +config GBB_HWID + string + depends on CHROMEOS + default "Gale TEST 1" + config DRAM_SIZE_MB int default 512 if BOARD_VARIANT_DK01 diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index b7813b7..0464e2d 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -36,6 +36,11 @@ config MAINBOARD_FAMILY string default "Google_Reef" +config GBB_HWID + string + depends on CHROMEOS + default "REEF TEST 3240" + config MAX_CPUS int default 8 diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index 9549672..5d50d7b 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -33,6 +33,11 @@ config MAINBOARD_VENDOR string default "Intel" +config GBB_HWID + string + depends on CHROMEOS + default "AMENIA TEST" + config FMAP_FILE string default "amenia"

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Patch set updated for coreboot: mainboard/intel/kunimitsu:[WIP] Add FSP 2.0 support in ramstage
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16356 -gerrit commit cb45bcfb7894fadfd2d796a96238d34a8688a2f9 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Aug 30 20:50:03 2016 +0530 mainboard/intel/kunimitsu:[WIP] Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Change-Id: I8a9ef156a4dea89b80757f2a186d7181526b805a --- src/mainboard/intel/kunimitsu/devicetree.cb | 3 +++ src/mainboard/intel/kunimitsu/ramstage.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index a5789b0..ee3dcf6 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -193,6 +193,9 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" + # Enable/Disable VMX + register "VmxEnable" = "0" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 44fb9cd..c67bf79 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -13,11 +13,13 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <soc/ramstage.h> #include "gpio.h" void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + printk(BIOS_DEBUG, "Configure Gpio...\n"); /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));

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Patch set updated for coreboot: soc/intel/skylake:[WIP] Add FSP 2.0 support in ramstage
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16355 -gerrit commit a52da6335ce5b49d4865c458a4d6705f7e3e883e Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Aug 30 20:47:13 2016 +0530 soc/intel/skylake:[WIP] Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Implement lb_framebuffer for pre OS screens. Change-Id: Ia3c1dd741fb657ec14e305a1ef7cebc2befff188 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 24 +- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/chip.h | 13 + src/soc/intel/skylake/chip_fsp20.c | 514 ++++++++++++++++++++- src/soc/intel/skylake/igd.c | 6 +- src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 3 +- src/soc/intel/skylake/lb_framebuffer.c | 47 ++ 7 files changed, 601 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index edf5db3..34b15ed 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -42,7 +42,6 @@ config CPU_SPECIFIC_OPTIONS select RTC select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET @@ -54,6 +53,25 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC +config PLATFORM_USES_FSP2_0 + select ADD_VBT_DATA_FILE + select SOC_INTEL_COMMON_GFX_OPREGION + +config PLATFORM_USES_FSP1_1 + select GOP_SUPPORT + select DISPLAY_FSP_ENTRY_POINTS + select HAVE_FSP_BIN + +config FSP_FILE + string + depends on PLATFORM_USES_FSP1_1 + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/fsp/FSP.fd" + +config FSP_IMAGE_ID_STRING + string + depends on PLATFORM_USES_FSP1_1 + default "$SKLFSP$" + config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC @@ -213,4 +231,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config VBT_FILE + string "VBT binary path and filename" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 80562e4..15b7634 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -58,6 +58,7 @@ ramstage-y += flash_controller.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += igd.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += lb_framebuffer.c ramstage-y += lpc.c ramstage-y += me_status.c ramstage-y += memmap.c diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 62e28e6..85f6054 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -273,6 +273,19 @@ struct soc_intel_skylake_config { u16 PchConfigSubSystemVendorId; /* Subsystem ID of the PCH devices*/ u16 PchConfigSubSystemId; + + /* + * Determine if WLAN wake from Sx, corresponds to the + * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanEnable; + + /* + * Determine if WLAN wake from DeepSx, corresponds to + * the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanDeepSxEnable; + /* * Corresponds to the "WOL Enable Override" bit in the General PM * Configuration B (GEN_PMCON_B) register diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 215530c..7a403e4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify @@ -18,13 +17,524 @@ #include <bootstate.h> #include <device/pci.h> #include <fsp/api.h> +#include <arch/acpi.h> +#include <chip.h> +#include <bootstate.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <soc/acpi.h> +#include <soc/interrupt.h> +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <string.h> + +static const struct SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { + /* + * cAVS(Audio, Voice, Speach), INTA is default, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + /* + * SMBus Controller, no default value, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + /* TraceHub, INTA is default, RO register */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ), + /* + * SerialIo: UART #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[7] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), + /* + * SerialIo: UART #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[8] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), + /* + * SerialIo: SPI #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[10] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), + /* + * SerialIo: SPI #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[11] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + /* SCS: eMMC (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + /* SCS: SDIO (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + /* SCS: SDCard (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + /* PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), + /* PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), + /* PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), + /* PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + /* + * PCI Express Port 1, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + /* + * PCI Express Port 2, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + /* + * PCI Express Port 3, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + /* + * PCI Express Port 4, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + /* + * PCI Express Port 5, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + /* + * PCI Express Port 6, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + /* + * PCI Express Port 7, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + /* + * PCI Express Port 8, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + /* + * SerialIo UART Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[9] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + /* + * SerialIo UART Controller #5, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[6] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + /* + * SerialIo UART Controller #4, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[5] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + /* + * SATA Controller, INTA is default, + * programmed in PciCfgSpace + 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, + PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + /* CSME: HECI #1 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME), int_A, HECI_1_IRQ), + /* CSME: HECI #2 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_2), int_B, HECI_2_IRQ), + /* CSME: IDE-Redirection (IDE-R) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_IDER), int_C, IDER_IRQ), + /* CSME: Keyboard and Text (KT) Redirection */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_KT), int_D, KT_IRQ), + /* CSME: HECI #3 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_3), int_A, HECI_3_IRQ), + /* + * SerialIo I2C Controller #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[1] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + /* + * SerialIo I2C Controller #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[2] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + /* + * SerialIo I2C Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[3] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + /* + * SerialIo I2C Controller #3, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[4] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + /* + * USB 3.0 xHCI Controller, no default value, + * programmed in PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + /* USB Device Controller (OTG) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + /* Thermal Subsystem */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THRMAL_IRQ), + /* Camera IO Host Controller */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + /* Integrated Sensor Hub */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, + PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) +}; + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +const char *soc_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_IGD: return "GFX0"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_USBOTG: return "XDCI"; + case PCH_DEVFN_THERMAL: return "THRM"; + case PCH_DEVFN_CIO: return "ICIO"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_ME: return "MEI1"; + case PCH_DEVFN_ME_2: return "MEI2"; + case PCH_DEVFN_ME_IDER: return "MEID"; + case PCH_DEVFN_ME_KT: return "MEKT"; + case PCH_DEVFN_ME_3: return "MEI3"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_EMMC: return "EMMC"; + case PCH_DEVFN_SDIO: return "SDIO"; + case PCH_DEVFN_SDCARD: return "SDXC"; + case PCH_DEVFN_LPC: return "LPCB"; + case PCH_DEVFN_P2SB: return "P2SB"; + case PCH_DEVFN_PMC: return "PMC_"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_SPI: return "FSPI"; + case PCH_DEVFN_GBE: return "IGBE"; + case PCH_DEVFN_TRACEHUB:return "THUB"; + } + + return NULL; +} +#endif + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .ops_pci_bus = &pci_bus_default_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = &soc_init_cpus, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = generate_cpu_entries, +#endif +}; + +static void soc_enable(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle PCH device enable */ + if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD && + (dev->ops == NULL || dev->ops->enable == NULL)) { + pch_enable_dev(dev); + } + } +} + +struct chip_operations soc_intel_skylake_ops = { + CHIP_NAME("Intel 6th Gen") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, +}; /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd) { + struct FSP_S_CONFIG *params = &supd->FspsConfig; + struct FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; + static struct soc_intel_skylake_config *config; + int i, intdeventry; + uintptr_t *vbt_data = NULL; + u8 irq_config[PCH_MAX_IRQ_CONFIG]; + + int is_s3_wakeup = acpi_is_wakeup_s3(); + + struct device *dev = SA_DEV_ROOT; + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + mainboard_silicon_init_params(params); + + /* Load VBT */ + if (!is_s3_wakeup) { + vbt_data = (uintptr_t *) fsp_load_vbt(); + } + + params->GraphicsConfigPtr = (u32) vbt_data; + + /* Get Device Int Count */ + intdeventry = ARRAY_SIZE(devintconfig); + + /*update irq table */ + memcpy((struct SI_PCH_DEVICE_INTERRUPT_CONFIG *) + (params->DevIntConfigPtr), devintconfig, intdeventry * + sizeof(struct SI_PCH_DEVICE_INTERRUPT_CONFIG)); + + params->NumOfDevIntConfig = intdeventry; + /* PxRC to IRQ programing */ + for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) { + switch (i) { + case PCH_PARC: + case PCH_PCRC: + case PCH_PDRC: + case PCH_PERC: + case PCH_PFRC: + case PCH_PGRC: + case PCH_PHRC: + irq_config[i] = PCH_IRQ11; + break; + case PCH_PBRC: + irq_config[PCH_PBRC] = PCH_IRQ10; + break; + } + } + + memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); + + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = + config->usb2_ports[i].enable; + params->Usb2AfePetxiset[i] = + config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = + config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = + config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = + config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = + config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + for (i = 0; i < ARRAY_SIZE(config->i2c); i++) + params->SerialIoI2cVoltage[i] = config->i2c[i].voltage; + + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(params, i, &config->domain_vr_config[i]); + + /* GPIO IRQ Route The valid values is 14 or 15 */ + if (config->GpioIrqSelect == 0) + params->GpioIrqRoute = GPIO_IRQ14; + else + params->GpioIrqRoute = config->GpioIrqSelect; + + /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23 */ + if (config->SciIrqSelect == 0) + params->SciIrqSelect = SCI_IRQ9; + else + params->SciIrqSelect = config->SciIrqSelect; + /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23 */ + if (config->TcoIrqSelect == 0) + params->TcoIrqSelect = TCO_IRQ9; + else + params->TcoIrqSelect = config->TcoIrqSelect; + /* TCO Irq enable/disable */ + params->TcoIrqEnable = config->TcoIrqEnable; + + params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; + params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; + params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + params->PchPmDeepSxPol = config->PmConfigDeepSxPol; + params->PchLanEnable = config->EnableLan; + + params->SataEnable = config->EnableSata; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + + params->PchHdaEnable = config->EnableAzalia; + params->PchHdaDspEnable = config->DspEnable; + params->PchHdaIoBufferOwnership = config->IoBufferOwnership; + + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(params->PcieRpClkReqSupport)); + memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(params->PcieRpClkReqNumber)); + + params->XdciEnable = config->XdciEnable; + params->SsicPortEnable = config->SsicPortEnable; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, + sizeof(params->SerialIoDevMode)); + params->PchCio2Enable = config->Cio2Enable; + + params->ScsEmmcEnabled = config->ScsEmmcEnabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->ScsSdCardEnabled = config->ScsSdCardEnabled; + + params->PchIshEnable = config->IshEnable; + params->Heci3Enabled = config->Heci3Enabled; + params->LogoPtr = config->LogoPtr; + params->LogoSize = config->LogoSize; + params->Device4Enable = config->Device4Enable; + + params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; + params->PchSubSystemId = config->PchConfigSubSystemId; + params->PchLockDownSpiEiss = config->LockDownConfigSpiEiss; + params->PchLockDownBiosLock = config->LockDownConfigBiosLock; + params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; + params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; + params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; + params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; + params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; + params->PchPmLpcClockRun = config->PmConfigPciClockRun; + params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; + params->PchPmPwrBtnOverridePeriod = + config->PmConfigPwrBtnOverridePeriod; + params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + params->PchSirqEnable = config->SerialIrqConfigSirqEnable; + params->PchSirqMode = config->SerialIrqConfigSirqMode; + + params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit; + params->CpuConfig.Bits.VmxEnable = config->VmxEnable; + params->SendVrMbxCmd = config->SendVrMbxCmd; + + /* Show SPI controller if enabled in devicetree.cb */ + dev = dev_find_slot(0, PCH_DEVFN_SPI); + params->ShowSpiController = dev->enabled; + + params->PchCio2Enable = config->Cio2Enable; + + tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; + tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; + tconfig->PchLockDownBiosInterface = config->LockDownConfigBiosInterface; + params->PchLockDownBiosLock = config->LockDownConfigBiosLock; +} + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + else + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + (device << 16) | vendor); } struct pci_operations soc_pci_ops = { - /* TODO: Add set subsystem id function */ + .set_subsystem = &pci_set_subsystem }; +/* Mainboard GPIO Configuration */ +__attribute__((weak)) void mainboard_silicon_init_params(struct FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index 93f05cc..42463ee 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -79,7 +79,8 @@ static void igd_init(struct device *dev) gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); } - if (IS_ENABLED(CONFIG_GOP_SUPPORT)) + if (IS_ENABLED(CONFIG_GOP_SUPPORT) || + IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE)) return; /* IGD needs to be Bus Master */ @@ -153,7 +154,8 @@ static unsigned long write_acpi_igd_opregion(device_t device, igd_opregion_t *opregion; /* If GOP is not used, exit here */ - if (!IS_ENABLED(CONFIG_GOP_SUPPORT)) + if ((!IS_ENABLED(CONFIG_GOP_SUPPORT)) && + (!IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE))) return current; /* If IGD is disabled, exit here */ diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index 3a9d96b..fb6ac46 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -19,7 +19,6 @@ #include <chip.h> #include <device/device.h> - #include <fsp/api.h> #include <fsp/util.h> #include <soc/intel/common/opregion.h> @@ -27,7 +26,7 @@ #define FSP_SIL_UPD struct FSP_S_CONFIG #define FSP_MEM_UPD struct FSP_M_CONFIG -void intel_silicon_init(void); +inline void intel_silicon_init(void) { fsp_silicon_init(); } void mainboard_silicon_init_params(struct FSP_S_CONFIG *params); void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/skylake/lb_framebuffer.c b/src/soc/intel/skylake/lb_framebuffer.c new file mode 100644 index 0000000..b9a3cca --- /dev/null +++ b/src/soc/intel/skylake/lb_framebuffer.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> + +static uintptr_t framebuffer_bar = (uintptr_t)NULL; + +void lb_framebuffer(struct lb_header *header) +{ + enum cb_err ret; + struct lb_framebuffer *framebuffer; + + framebuffer = (void *)lb_new_record(header); + ret = fsp_fill_lb_framebuffer(framebuffer); + if (ret != CB_SUCCESS) { + printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); + return; + } + + if (!framebuffer_bar) { + printk(BIOS_ALERT, "Framebuffer BAR 0x%x \n", + (uint32_t)framebuffer->physical_address); + printk(BIOS_ALERT, "Framebuffer BAR invalid (00:02.0 BAR2)\n"); + return; + } + + /* + * Resource allocator can move the BAR + * around after FSP configures it + */ + framebuffer->physical_address = framebuffer_bar; + printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", + framebuffer->physical_address); +}

1 0

Patch merged into coreboot/master: fsp_broadwell_de: Refactor code for SPI debug messages
by gerrit＠coreboot.org 30 Aug '16

30 Aug '16

the following patch was just integrated into master: commit 62d13139256d6b6abcc7a5d88dfd6b0f2e689dd6 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Aug 29 08:00:50 2016 +0200 fsp_broadwell_de: Refactor code for SPI debug messages Currently boards based on fsp_broadwell_de fail to compile if the config switch CONFIG_DEBUG_SPI_FLASH is selected. The error is caused by the usage of const for the address pointer in the functions writeb_, writew_ and writel_. The reason why it stayed hidden for so long is the fact that the switch is used with the preprocessor and nobody really selects it until there is a bug one want to find in this area. This patch fixes the parameter type definition which solves the error. In addition the config switch is not used on preprocessor level anymore but instead on compiler level. This ensures that at least the code syntax is checked on build time even if the config option is not selected. Also prefix the messages with "SPI:" to make them more meaningful in a full log. Change-Id: I3514b0d4c08bf5a4740f2632641e09af1b3aaf3a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/16347 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16347 for details. -gerrit

1 0

Patch set updated for coreboot: driver/intel/fsp2.0: Add External stage cache region helper
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16312 -gerrit commit 9295eb97ca31b1777a19876a7e95e06287746a67 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Wed Aug 24 16:05:32 2016 +0530 driver/intel/fsp2.0: Add External stage cache region helper If ramstage caching outside CBMEM is enabled i.e CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM, then a helper function to determine the caching region in SMM should be implemented. Add the same to FSP2.0 driver. FSP1.1 driver had the same implementation hence copied stage_cache.c. The SoC code should implement the smm_subregion to provide the base and size of the caching region within SMM. The fsp/memmap.h provides the prototype and we will reuse the same from FPS 1.1. Change-Id: I4412a710391dc0cee044b96403c50260c3534e6f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 2 ++ src/drivers/intel/fsp2_0/include/fsp/memmap.h | 47 +++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/stage_cache.c | 28 ++++++++++++++++ 3 files changed, 77 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 0a6ae43..79b57f6 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -23,6 +23,7 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-y += debug.c ramstage-y += graphics.c @@ -32,6 +33,7 @@ ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c ramstage-y += silicon_init.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c diff --git a/src/drivers/intel/fsp2_0/include/fsp/memmap.h b/src/drivers/intel/fsp2_0/include/fsp/memmap.h new file mode 100644 index 0000000..965bce6 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/memmap.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _COMMON_MEMMAP_H_ +#define _COMMON_MEMMAP_H_ + +#include <types.h> + +/* + * mmap_region_granularity must to return a size which is a positive non-zero + * integer multiple of the SMM size when SMM is in use. When not using SMM, + * this value should be set to 8 MiB. + */ +size_t mmap_region_granularity(void); + +/* Fills in the arguments for the entire SMM region covered by chipset + * protections. e.g. TSEG. */ +void smm_region(void **start, size_t *size); + +enum { + /* SMM handler area. */ + SMM_SUBREGION_HANDLER, + /* SMM cache region. */ + SMM_SUBREGION_CACHE, + /* Chipset specific area. */ + SMM_SUBREGION_CHIPSET, + /* Total sub regions supported. */ + SMM_SUBREGION_NUM, +}; + +/* Fills in the start and size for the requested SMM subregion. Returns + * 0 on susccess, < 0 on failure. */ +int smm_subregion(int sub, void **start, size_t *size); + +#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c new file mode 100644 index 0000000..2d594e6 --- /dev/null +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/memmap.h> +#include <stage_cache.h> + +void stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } +}

1 0

Patch set updated for coreboot: skylake: Add initial FSP2.0 support
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16267 -gerrit commit 1fd08b7b3e7a6ca4b94ec9ef8a4e9ba28ac5284d Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Aug 23 14:31:23 2016 +0530 skylake: Add initial FSP2.0 support Add Initial pieces of code to support fsp2.0 in skylake keeping the fsp1.1 flow intact. The soc/romstage.h and soc/ramstage.h have a reference to fsp driver includes, so split these header files for each version of FSP driver. Add the below files, car_stage.S: Add romstage entry point (car_stage_entry). This calls into romstage_fsp20.c and aslo handles the car teardown. romstage_fsp20.c: Call fsp_memory_init() and also has the callback for filling memory init parameters. Also add monotonic_timer.c to verstage. With this patchset and relevant change in kunimitsu mainboard, we are able to boot to romstage. TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1 Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0 Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 13 +- src/soc/intel/skylake/chip_fsp20.c | 30 +++++ src/soc/intel/skylake/igd.c | 29 +---- src/soc/intel/skylake/include/fsp11/soc/ramstage.h | 36 ++++++ src/soc/intel/skylake/include/fsp11/soc/romstage.h | 30 +++++ src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 39 ++++++ src/soc/intel/skylake/include/fsp20/soc/romstage.h | 30 +++++ src/soc/intel/skylake/include/soc/ramstage.h | 31 ----- src/soc/intel/skylake/include/soc/romstage.h | 30 ----- src/soc/intel/skylake/include/soc/smm.h | 1 - src/soc/intel/skylake/include/soc/vr_config.h | 9 +- src/soc/intel/skylake/memmap.c | 1 - src/soc/intel/skylake/opregion.c | 49 ++++++++ src/soc/intel/skylake/reset.c | 32 +++++ src/soc/intel/skylake/romstage/Makefile.inc | 5 +- src/soc/intel/skylake/romstage/car_stage.S | 131 +++++++++++++++++++++ src/soc/intel/skylake/romstage/romstage_fsp20.c | 44 +++++++ src/soc/intel/skylake/vr_config.c | 27 +++-- 19 files changed, 460 insertions(+), 108 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 6171c41..edf5db3 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS select RTC select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 716c3d5..aa3da61 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -40,12 +40,14 @@ romstage-y += pch.c romstage-y += pcr.c romstage-y += pei_data.c romstage-y += pmutil.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += smbus_common.c romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-y += chip.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c ramstage-y += cpu.c ramstage-y += cpu_info.c ramstage-y += dsp.c @@ -59,12 +61,14 @@ ramstage-y += lpc.c ramstage-y += me_status.c ramstage-y += memmap.c ramstage-y += monotonic_timer.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c ramstage-y += pch.c ramstage-y += pcie.c ramstage-y += pcr.c ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += ramstage.c ramstage-y += sd.c ramstage-y += smbus.c @@ -93,7 +97,14 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include + +ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) +CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake +else +CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake +endif # Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c new file mode 100644 index 0000000..215530c --- /dev/null +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <chip.h> +#include <bootstate.h> +#include <device/pci.h> +#include <fsp/api.h> + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd) +{ +} + +struct pci_operations soc_pci_ops = { + /* TODO: Add set subsystem id function */ +}; + diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index a8ac645..93f05cc 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -24,7 +24,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <drivers/intel/gma/i915_reg.h> -#include <fsp/gop.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/pm.h> @@ -117,35 +116,10 @@ static void igd_init(struct device *dev) } /* Initialize IGD OpRegion, called from ACPI code */ -static int init_igd_opregion(igd_opregion_t *opregion) +static int update_igd_opregion(igd_opregion_t *opregion) { - const optionrom_vbt_t *vbt; - uint32_t vbt_len; u16 reg16; - memset(opregion, 0, sizeof(igd_opregion_t)); - - /* Read VBT table from flash */ - vbt = fsp_get_vbt(&vbt_len); - if (!vbt) - die("vbt data not found"); - - memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(IGD_OPREGION_SIGNATURE) - 1); - memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32)); - memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < - sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : - sizeof(opregion->vbt.gvd1)); - - /* Size, in KB, of the entire OpRegion structure (including header)*/ - opregion->header.size = sizeof(igd_opregion_t) / KiB; - opregion->header.version = IGD_OPREGION_VERSION; - - /* We just assume we're mobile for now */ - opregion->header.mailboxes = MAILBOXES_MOBILE; - - /* TODO Initialize Mailbox 1 */ - /* Initialize Mailbox 3 */ opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; @@ -189,6 +163,7 @@ static unsigned long write_acpi_igd_opregion(device_t device, printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); opregion = (igd_opregion_t *)current; init_igd_opregion(opregion); + update_igd_opregion(opregion); current += sizeof(igd_opregion_t); current = acpi_align_current(current); diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h new file mode 100644 index 0000000..e469554 --- /dev/null +++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include <chip.h> +#include <device/device.h> +#include <fsp/gop.h> +#include <fsp/ramstage.h> +#include <fsp/soc_binding.h> + +#define FSP_SIL_UPD SILICON_INIT_UPD +#define FSP_MEM_UPD MEMORY_INIT_UPD + +void pch_enable_dev(device_t dev); +void soc_init_pre_device(void *chip_info); +void soc_init_cpus(device_t dev); +const char *soc_acpi_name(struct device *dev); +int init_igd_opregion(igd_opregion_t *igd_opregion); +extern struct pci_operations soc_pci_ops; + +#endif diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h new file mode 100644 index 0000000..6c40bd6 --- /dev/null +++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include <fsp/romstage.h> + +void systemagent_early_init(void); +void intel_early_me_status(void); +void enable_smbus(void); +int smbus_read_byte(unsigned device, unsigned address); + +int early_spi_read_wpsr(u8 *sr); +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h new file mode 100644 index 0000000..3a9d96b --- /dev/null +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include <chip.h> +#include <device/device.h> + +#include <fsp/api.h> +#include <fsp/util.h> +#include <soc/intel/common/opregion.h> + +#define FSP_SIL_UPD struct FSP_S_CONFIG +#define FSP_MEM_UPD struct FSP_M_CONFIG + +void intel_silicon_init(void); +void mainboard_silicon_init_params(struct FSP_S_CONFIG *params); +void pch_enable_dev(device_t dev); +void soc_init_pre_device(void *chip_info); +void soc_init_cpus(device_t dev); +const char *soc_acpi_name(struct device *dev); + +extern struct pci_operations soc_pci_ops; + +#endif diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h new file mode 100644 index 0000000..d48ac67 --- /dev/null +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +asmlinkage void *car_stage_c_entry(void); +void mainboard_memory_init_params(struct FSPM_UPD *mupd); + +void systemagent_early_init(void); +int smbus_read_byte(unsigned device, unsigned address); +int early_spi_read_wpsr(u8 *sr); + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h deleted file mode 100644 index 55f9972..0000000 --- a/src/soc/intel/skylake/include/soc/ramstage.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_RAMSTAGE_H_ -#define _SOC_RAMSTAGE_H_ - -#include <chip.h> -#include <device/device.h> -#include <fsp/ramstage.h> - -void pch_enable_dev(device_t dev); -void soc_init_pre_device(void *chip_info); -void soc_init_cpus(device_t dev); -const char *soc_acpi_name(struct device *dev); - -extern struct pci_operations soc_pci_ops; - -#endif diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h deleted file mode 100644 index 6c40bd6..0000000 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_ROMSTAGE_H_ -#define _SOC_ROMSTAGE_H_ - -#include <fsp/romstage.h> - -void systemagent_early_init(void); -void intel_early_me_status(void); -void enable_smbus(void); -int smbus_read_byte(unsigned device, unsigned address); - -int early_spi_read_wpsr(u8 *sr); -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index fa8da46..1beaaa4 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -20,7 +20,6 @@ #include <stdint.h> #include <cpu/x86/msr.h> #include <fsp/memmap.h> -#include <fsp/romstage.h> #include <soc/gpio.h> struct ied_header { diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index d70fd21..1c19b88 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -19,7 +19,11 @@ #ifndef _SOC_VR_CONFIG_H_ #define _SOC_VR_CONFIG_H_ +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/soc_binding.h> +#else +#include <fsp/api.h> +#endif struct vr_config { @@ -74,7 +78,6 @@ enum vr_domain{ NUM_VR_DOMAINS }; -void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain, - const struct vr_config *cfg); - +void fill_vr_domain_config(void *params, + int domain, const struct vr_config *cfg); #endif diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 6af1371..96debfd 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -21,7 +21,6 @@ #include <device/pci.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> #include <soc/smm.h> #include <soc/systemagent.h> #include <stdlib.h> diff --git a/src/soc/intel/skylake/opregion.c b/src/soc/intel/skylake/opregion.c new file mode 100644 index 0000000..31987cb --- /dev/null +++ b/src/soc/intel/skylake/opregion.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <soc/ramstage.h> +#include <fsp/gop.h> +#include <stdlib.h> +#include <string.h> + +int init_igd_opregion(igd_opregion_t *opregion) +{ + const optionrom_vbt_t *vbt; + uint32_t vbt_len; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* Read VBT table from flash */ + vbt = fsp_get_vbt(&vbt_len); + if (!vbt) + die("vbt data not found"); + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE) - 1); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32)); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); + + /* Size, in KB, of the entire OpRegion structure (including header)*/ + opregion->header.size = sizeof(igd_opregion_t) / KiB; + opregion->header.version = IGD_OPREGION_VERSION; + + /* We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + return 0; +} diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c new file mode 100644 index 0000000..ab251ce --- /dev/null +++ b/src/soc/intel/skylake/reset.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <reset.h> + +void chipset_handle_reset(enum fsp_status status) +{ + switch(status) { + case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ + printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); + hard_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 31a452f..e552c39 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,7 +1,8 @@ - verstage-y += power_state.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage.S romstage-y += power_state.c -romstage-y += romstage.c +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += spi.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S new file mode 100644 index 0000000..c6401fa --- /dev/null +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <rules.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +.section ".text" +.global car_stage_entry + +car_stage_entry: + + /* Enter the C code */ + call car_stage_c_entry + +/* + * Car teardown + */ + /* + * eax: New stack address + */ + + /* Switch to the stack in RAM */ + movl %eax, %esp + + #include <soc/car_teardown.S> + + /* Display the MTRRs */ + call soc_display_mtrrs + + /* + * The stack contents are initialized in src/soc/intel/common/stack.c + * to be the following: + * + * * + * * + * * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * +0: Number of variable MTRRs to clear + */ + + /* Clear all of the variable MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx + clr %eax + clr %edx + +1: + testl %ebx, %ebx + jz 1f + wrmsr /* Write MTRR base. */ + inc %ecx + wrmsr /* Write MTRR mask. */ + inc %ecx + dec %ebx + jmp 1b + +1: + /* Get number of MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx +2: + testl %ebx, %ebx + jz 2f + + /* Low 32 bits of MTRR base. */ + popl %eax + /* Upper 32 bits of MTRR base. */ + popl %edx + /* Write MTRR base. */ + wrmsr + inc %ecx + /* Low 32 bits of MTRR mask. */ + popl %eax + /* Upper 32 bits of MTRR mask. */ + popl %edx + /* Write MTRR mask. */ + wrmsr + inc %ecx + + dec %ebx + jmp 2b +2: + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + call copy_and_run diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c new file mode 100644 index 0000000..8a15a69 --- /dev/null +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/romstage.h> + +asmlinkage void *car_stage_c_entry(void) +{ + bool s3wake = false; + console_init(); + /* TODO: Add fill_powerstate and determine sleep state. */ + fsp_memory_init(s3wake); + return NULL; +} +static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg) +{ + /* TODO: Fill SoC specific Memory init Params */ +} + +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){ + + struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + soc_memory_init_params(m_cfg); + mainboard_memory_init_params(mupd); +} + +__attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd) +{ + /* Do nothing */ +} diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 40223e3..17ccd7d 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -14,6 +14,8 @@ * */ +#include <fsp/api.h> +#include <soc/ramstage.h> #include <soc/vr_config.h> /* Default values for domain configuration. PSI3 and PSI4 are disabled. */ @@ -80,9 +82,10 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { }, }; -void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain, - const struct vr_config *chip_cfg) +void fill_vr_domain_config(void *params, + int domain, const struct vr_config *chip_cfg) { + FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params; const struct vr_config *cfg; if (domain < 0 || domain >= NUM_VR_DOMAINS) @@ -94,14 +97,14 @@ void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain, else cfg = &default_configs[domain]; - params->VrConfigEnable[domain] = cfg->vr_config_enable; - params->Psi1Threshold[domain] = cfg->psi1threshold; - params->Psi2Threshold[domain] = cfg->psi2threshold; - params->Psi3Threshold[domain] = cfg->psi3threshold; - params->Psi3Enable[domain] = cfg->psi3enable; - params->Psi4Enable[domain] = cfg->psi4enable; - params->ImonSlope[domain] = cfg->imon_slope; - params->ImonOffset[domain] = cfg->imon_offset; - params->IccMax[domain] = cfg->icc_max; - params->VrVoltageLimit[domain] = cfg->voltage_limit; + vr_params->VrConfigEnable[domain] = cfg->vr_config_enable; + vr_params->Psi1Threshold[domain] = cfg->psi1threshold; + vr_params->Psi2Threshold[domain] = cfg->psi2threshold; + vr_params->Psi3Threshold[domain] = cfg->psi3threshold; + vr_params->Psi3Enable[domain] = cfg->psi3enable; + vr_params->Psi4Enable[domain] = cfg->psi4enable; + vr_params->ImonSlope[domain] = cfg->imon_slope; + vr_params->ImonOffset[domain] = cfg->imon_offset; + vr_params->IccMax[domain] = cfg->icc_max; + vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; }

1 0

Patch set updated for coreboot: skylake: Add FSP 2.0 support in romstage
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16315 -gerrit commit 152538033bc0239df9bfe913cc5c9513894b8b52 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Aug 24 20:48:46 2016 +0530 skylake: Add FSP 2.0 support in romstage Set up stack and MTRRs after Dram initialization. This set up code is present in FSP1.1 driver, copy and reuse stack.c. Populate SoC related Memory related params. Make sure FSP_M binary is properly relocated to the base where it is placed in CBFS. i.e., make it XIP. TEST=Build and boot kunimitsu, dram initialization done. ramstage is loaded. Change-Id: I8d943e29b6e118986189166d92c7891ab6642193 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 2 + src/soc/intel/skylake/chip.h | 4 + src/soc/intel/skylake/include/fsp20/soc/romstage.h | 9 +- src/soc/intel/skylake/memmap.c | 1 + src/soc/intel/skylake/romstage/romstage_fsp20.c | 83 +++++++++- src/soc/intel/skylake/stack.c | 168 +++++++++++++++++++++ 6 files changed, 260 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index aa3da61..80562e4 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -42,6 +42,7 @@ romstage-y += pei_data.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += smbus_common.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += stack.c romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c @@ -104,6 +105,7 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake else CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake +$(CONFIG_FSP_M_CBFS)-options := --xip endif # Currently used for microcode path. diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a4dee51..62e28e6 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -359,6 +359,10 @@ struct soc_intel_skylake_config { * 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue */ u8 SendVrMbxCmd; + + /* Enable/Disable VMX feature */ + u8 VmxEnable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254; diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index d48ac67..ce3c7b4 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -22,9 +22,16 @@ asmlinkage void *car_stage_c_entry(void); void mainboard_memory_init_params(struct FSPM_UPD *mupd); - void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); +void *setup_stack_and_mtrrs(void); +/* Board type */ +enum board_type { + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 96debfd..6af1371 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -21,6 +21,7 @@ #include <device/pci.h> #include <soc/msr.h> #include <soc/pci_devs.h> +#include <soc/romstage.h> #include <soc/smm.h> #include <soc/systemagent.h> #include <stdlib.h> diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8a15a69..57b2a52 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -13,29 +13,100 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> +#include <arch/early_variables.h> +#include <arch/io.h> +#include <arch/symbols.h> +#include <assert.h> +#include <cpu/x86/mtrr.h> +#include <cbmem.h> +#include <chip.h> #include <console/console.h> +#include <device/pci_def.h> #include <fsp/util.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <timestamp.h> +#include <vboot/vboot_common.h> asmlinkage void *car_stage_c_entry(void) { - bool s3wake = false; + bool s3wake; + void *top_of_stack; + struct chipset_power_state *ps; + console_init(); - /* TODO: Add fill_powerstate and determine sleep state. */ + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + + ps = fill_power_state(); + timestamp_add_now(TS_START_ROMSTAGE); + s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); - return NULL; + + top_of_stack = setup_stack_and_mtrrs(); + return top_of_stack; } + static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg) { - /* TODO: Fill SoC specific Memory init Params */ -} + const struct device *dev; + const struct soc_intel_skylake_config *config; + int i; + uint32_t mask = 0; -void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){ + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + config = dev->chip_info; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not + * have access to the bios_reserved range so it always assumes 8MB is + * used and so the kernel will avoid the last 8MB of the stolen window. + * With the default stolen size of 32MB(-8MB) there is not enough space + * for FBC to work with a high resolution panel. + */ + m_cfg->IgdDvmt50PreAlloc = 2; + m_cfg->MmioSize = 0x800; /* 2GB in MB */ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->EnableTraceHub = config->EnableTraceHub; + if (vboot_recovery_mode_enabled()) + m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */ + else + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->Rmt; + m_cfg->DdrFreqLimit = config->DdrFreqLimit; + m_cfg->VmxEnable = config->VmxEnable; + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1<<i); + } + m_cfg->PcieRpEnableMask = mask; +} +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) +{ struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + struct FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; soc_memory_init_params(m_cfg); + + /* Enable DMI Virtual Channel for ME */ + m_t_cfg->DmiVcm = 0x01; + + /* Enable Sending DID to ME */ + m_t_cfg->SendDidMsg = 0x01; + m_t_cfg->DidInitStat = 0x01; + mainboard_memory_init_params(mupd); + + /* Reserve enough memory under TOLUD to save CBMEM header */ + mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); + } __attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd) diff --git a/src/soc/intel/skylake/stack.c b/src/soc/intel/skylake/stack.c new file mode 100644 index 0000000..4b934a1 --- /dev/null +++ b/src/soc/intel/skylake/stack.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <fsp/memmap.h> +#include <soc/romstage.h> +#include <stdlib.h> +#include <program_loading.h> +#include <soc/intel/common/util.h> + +static inline void *stack_push32(void *stack, uint32_t value) +{ + uint32_t *stack32 = stack; + + stack32 = &stack32[-1]; + *stack32 = value; + return stack32; +} + +/* + * setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void *setup_stack_and_mtrrs(void) +{ + size_t alignment; + uint32_t aligned_ram; + uint32_t mtrr_mask_upper; + uint32_t max_mtrrs; + uint32_t num_mtrrs; + uint32_t *slot; + unsigned long top_of_stack; + + /* Display the MTTRs */ + soc_display_mtrrs(); + + /* Top of stack needs to be aligned to a 8-byte boundary. */ + top_of_stack = romstage_ram_stack_top(); + slot = (void *)top_of_stack; + num_mtrrs = 0; + max_mtrrs = soc_get_variable_mtrr_count(NULL); + + /* + * The upper bits of the MTRR mask need to set according to the number + * of physical address bits. + */ + mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + alignment = mmap_region_granularity(); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); + + /* + * The order for each MTRR is value then base with upper 32-bits of + * each value coming before the lower 32-bits. The reasoning for + * this ordering is to create a stack layout like the following: + * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * +0: Number of variable MTRRs to clear + */ + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + /* + * Cache the stack and the other CBMEM entries as well as part or all + * of the FSP reserved memory region. + */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); + num_mtrrs++; + + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + void *smm_base; + size_t smm_size; + uint32_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uint32_t)smm_base; + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + num_mtrrs++; + } + /* Cache the ROM as WP just below 4GiB. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + num_mtrrs++; + + /* Validate the MTRR usage */ + if (num_mtrrs > max_mtrrs) { + printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d", + max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs); + die("ERROR - MTRR use count incorrect!\n"); + } + + /* + * Save the number of MTRRs to setup and clear. Return the stack + * location pointing to the number of MTRRs. + */ + slot = stack_push32(slot, num_mtrrs); + slot = stack_push32(slot, max_mtrrs); + return slot; +}

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coreboot-gerrit August 2016