coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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1551 discussions

New patch to review for coreboot: mainboard/google/reef: add pen connections
by Aaron Durbin 31 Aug '16

31 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16376 -gerrit commit 6d7d4b25164a4259b4d393b0448b395582c38bc5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 30 17:23:59 2016 -0500 mainboard/google/reef: add pen connections A pen interface was added. Prepare for possibly testing it by plumbing in the gpio configuration. It's very possible these changes need to be tweaked, but no driver code has been seen yet nor a datasheet detailing how some of these signals actually function. BUG=chrome-os-partner:56739 Change-Id: I208ff3e151ce55d62e5fcc33a1e39cc87e229970 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/gpio.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index bf43d3e..d3b1e91 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -112,9 +112,11 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* LPSS_I2C4_SDA */ PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* LPSS_I2C4_SCL */ - /* I2C5-7 -- unused. */ - PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* LPSS_I2C5_SDA */ - PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* LPSS_I2C5_SCL */ + /* I2C5 -- pen with external pulls */ + PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1), /* LPSS_I2C5_SDA */ + PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1), /* LPSS_I2C5_SCL */ + + /* I2C6-7 -- unused. */ PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ @@ -289,7 +291,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ @@ -299,7 +301,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */ PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* unused */ + PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* PEN_PDCT_ODL */ PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */ @@ -310,7 +312,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */ PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */ PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_35, UP_20K, DEEP), /* unused */ + PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */ PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */ PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */

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New patch to review for coreboot: mainboard/google/reef: fix polarity of FP_INT
by Aaron Durbin 31 Aug '16

31 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16375 -gerrit commit 9ac94d9b17c9d7e317b89863b3949859338f5255 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 30 17:05:31 2016 -0500 mainboard/google/reef: fix polarity of FP_INT The formerly name FP_INT_L net is actually active high and is push-pull. Therefore adjust for the new net name, FP_INT, and polarity. The pulldowns are there because the device is on another board that isn't always available. BUG=chrome-os-partner:56740 Change-Id: I6706fd2c2bd164cf3b5f1457aef69f5675f2112d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 09c1ee9..bf43d3e 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -290,7 +290,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_14, UP_20K, DEEP), /* FP IRQ */ + PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ @@ -378,7 +378,7 @@ static const struct pad_config proto_diff_table[] = { /* Wake peripheral signals post proto. */ static const struct pad_config nonproto_diff_table[] = { - PAD_CFG_GPI_SCI_LOW(GPIO_3, UP_20K, DEEP, LEVEL), /* FP_INT_L */ + PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL), /* FP_INT */ PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */

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New patch to review for coreboot: mainboard/google/reef: add new memory SKUs
by Aaron Durbin 31 Aug '16

31 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16374 -gerrit commit 01858a0a0e5f12c97903af282ba518db77d1229b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 30 16:57:37 2016 -0500 mainboard/google/reef: add new memory SKUs Two new SKUs are being utilized for reef DVT. Add the following: Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100 Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101 BUG=chrome-os-partner:56738 Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/romstage.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index e8d8e16..098fe31 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -111,6 +111,26 @@ static const struct lpddr4_sku skus[] = { .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "MT53B256M32D1NP", }, + /* + * H9HCNNNBPUMLHR-NLE - both logical channels. While the parts + * are listed at 16Gb there are 2 ranks per channel so indicate the + * density as 8Gb per rank. + */ + [4] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "H9HCNNNBPUMLHR", + }, + /* H9HCNNN8KUMLHR-NLE - both logical channels */ + [5] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "H9HCNNN8KUMLHR", + }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { .speed = LP4_SPEED_2400,

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New patch to review for coreboot: mainboard/google/reef: support WLAN_PE_RST
by Aaron Durbin 31 Aug '16

31 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16373 -gerrit commit bba9f21f26ba534f3697703048cde8a4a3cc2550 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 30 16:36:46 2016 -0500 mainboard/google/reef: support WLAN_PE_RST The reef DVT build added another way to assert the wifi module's reset line. Ensure it's deasserted by default. For previous boards this GPIO doesn't matter because it wasn't routed anyway. BUG=chrome-os-partner:56737 Change-Id: I63e97b091ca0a278682c883303b1d7e052d8e677 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/gpio.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index dbe7062..09c1ee9 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -271,7 +271,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */ PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */ PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */ - PAD_CFG_GPI(GPIO_122, UP_20K, DEEP), /* SIO_SPI_2_RXD */ + /* WLAN_PE_RST - default to deasserted. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */ /* Debug tracing. */ @@ -348,6 +349,8 @@ static const struct pad_config early_gpio_table[] = { /* I2C2 - TPM */ PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ + /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ }; /* GPIO settings before entering sleep. */

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Patch set updated for coreboot: [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 30 Aug '16

30 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit 962ade9cca4570946be0e81206970f638bbef931 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN), 19 (BKLT_CTRL_SEL), 17 (DGFX_PWRGD_GPIO) were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 5 ++++ src/drivers/lenovo/hybrid_graphics.c | 52 +++++++++++++++++++++++++++++++++--- src/mainboard/lenovo/t400/Kconfig | 20 ++++++++++++++ 3 files changed, 74 insertions(+), 3 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..4c62de1 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -39,3 +39,8 @@ config HYBRID_GRAPHICS_GPIO_NUM help Set a default GPIO that sets the panel LVDS signal routing to integrated or discrete GPU. + +config ENABLE_DISCRETE_IS_HIGH + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..00ad7df 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -25,6 +25,7 @@ #include <console/console.h> #include <southbridge/intel/common/gpio.h> +#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 /* Hybrid graphics allows to connect LVDS interface to either iGPU * or dGPU depending on GPIO level. * Nvidia is calling this functionality "muxed Optimus". @@ -40,12 +41,37 @@ #define HYBRID_GRAPHICS_INTEGRATED 0 #define HYBRID_GRAPHICS_DISCRETE 1 +#if CONFIG_NORTHBRIDGE_INTEL_GM45 +#define GGC_ADDR 0x52 +#endif + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE +#define GGC_ADDR 0x50 +#endif + +#if CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#define GGC_ADDR 0x50 +#endif + static void hybrid_graphics_disable_peg(struct device *dev) { - struct device *peg_dev; + struct device *peg_dev, *gmch; + u8 disable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; + u32 tmp; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, disable_lvl); + /* configure BKLT_CTL */ + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, disable_lvl); + /* configure DGFX_PWRGD */ + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, disable_lvl); + /* configure GFX_PWR_EN_GPIO */ + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -53,6 +79,11 @@ static void hybrid_graphics_disable_peg(struct device *dev) peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); if (peg_dev) peg_dev->enabled = 0; + /* Enable IGD */ + gmch = dev_find_slot(0, PCI_DEVFN(0, 0)); + tmp = pci_read_config16(gmch, GGC_ADDR); + pci_write_config16(gmch, GGC_ADDR, tmp + & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); printk(BIOS_DEBUG, "Hybrid graphics: Disabled PEG10.\n"); } @@ -61,14 +92,24 @@ static void hybrid_graphics_disable_peg(struct device *dev) * is present. Enable/disable VGA devices here. */ static void hybrid_graphics_enable_peg(struct device *dev) { + struct device *gmch; u8 hybrid_graphics_mode; + u8 enable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; + u32 tmp; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, enable_lvl); + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, enable_lvl); + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, enable_lvl); + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; @@ -77,6 +118,11 @@ static void hybrid_graphics_enable_peg(struct device *dev) if (dev && dev->ops->disable) dev->ops->disable(dev); dev->enabled = 0; + gmch = dev_find_slot(0, PCI_DEVFN(0, 0)); + tmp = pci_read_config16(gmch, GGC_ADDR); + pci_write_config16(gmch, GGC_ADDR, tmp + | HYBRID_GRAPHICS_INT_CLAIM_VGA); + printk(BIOS_DEBUG, "Hybrid graphics: Disabled IGD.\n"); } else diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a444bf8..65bb116 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -56,4 +56,24 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config HYBRID_GRAPHICS_GPIO_NUM + int + default 22 + +config BKLT_CTRL_SEL_GPIO + int + default 19 + +config GFX_PWR_EN_GPIO + int + default 49 + +config DGFX_PWRGD_GPIO + int + default 17 + +config ENABLE_DISCRETE_IS_HIGH + bool + default y + endif # BOARD_LENOVO_T400

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Patch set updated for coreboot: [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 30 Aug '16

30 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit ccc0bf04f556d8f81e77b7d6dde6f1a2911193dd Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN), 19 (BKLT_CTRL_SEL), 17 (DGFX_PWRGD_GPIO) were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 5 ++++ src/drivers/lenovo/hybrid_graphics.c | 52 +++++++++++++++++++++++++++++++++--- src/mainboard/lenovo/t400/Kconfig | 20 ++++++++++++++ 3 files changed, 74 insertions(+), 3 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..4c62de1 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -39,3 +39,8 @@ config HYBRID_GRAPHICS_GPIO_NUM help Set a default GPIO that sets the panel LVDS signal routing to integrated or discrete GPU. + +config ENABLE_DISCRETE_IS_HIGH + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..05b48ea 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -25,6 +25,7 @@ #include <console/console.h> #include <southbridge/intel/common/gpio.h> +#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 /* Hybrid graphics allows to connect LVDS interface to either iGPU * or dGPU depending on GPIO level. * Nvidia is calling this functionality "muxed Optimus". @@ -40,12 +41,37 @@ #define HYBRID_GRAPHICS_INTEGRATED 0 #define HYBRID_GRAPHICS_DISCRETE 1 +#if CONFIG_NORTHBRIDGE_INTEL_GM45 +#define GGC_ADDR 0x52 +#endif + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE +#define GGC_ADDR 0x50 +#endif + +#if CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#define GCC_ADDR 0x50 +#endif + static void hybrid_graphics_disable_peg(struct device *dev) { - struct device *peg_dev; + struct device *peg_dev, *gmch; + u8 disable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; + u32 tmp; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, disable_lvl); + /* configure BKLT_CTL */ + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, disable_lvl); + /* configure DGFX_PWRGD */ + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, disable_lvl); + /* configure GFX_PWR_EN_GPIO */ + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -53,6 +79,11 @@ static void hybrid_graphics_disable_peg(struct device *dev) peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); if (peg_dev) peg_dev->enabled = 0; + /* Enable IGD */ + gmch = dev_find_slot(0, PCI_DEVFN(0, 0)); + tmp = pci_read_config16(gmch, GGC_ADDR); + pci_write_config16(gmch, GGC_ADDR, tmp + & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); printk(BIOS_DEBUG, "Hybrid graphics: Disabled PEG10.\n"); } @@ -61,14 +92,24 @@ static void hybrid_graphics_disable_peg(struct device *dev) * is present. Enable/disable VGA devices here. */ static void hybrid_graphics_enable_peg(struct device *dev) { + struct device *gmch; u8 hybrid_graphics_mode; + u8 enable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; + u32 tmp; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, enable_lvl); + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, enable_lvl); + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, enable_lvl); + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; @@ -77,6 +118,11 @@ static void hybrid_graphics_enable_peg(struct device *dev) if (dev && dev->ops->disable) dev->ops->disable(dev); dev->enabled = 0; + gmch = dev_find_slot(0, PCI_DEVFN(0, 0)); + tmp = pci_read_config16(gmch, GGC_ADDR); + pci_write_config16(gmch, GGC_ADDR, tmp + | HYBRID_GRAPHICS_INT_CLAIM_VGA); + printk(BIOS_DEBUG, "Hybrid graphics: Disabled IGD.\n"); } else diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a444bf8..65bb116 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -56,4 +56,24 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config HYBRID_GRAPHICS_GPIO_NUM + int + default 22 + +config BKLT_CTRL_SEL_GPIO + int + default 19 + +config GFX_PWR_EN_GPIO + int + default 49 + +config DGFX_PWRGD_GPIO + int + default 17 + +config ENABLE_DISCRETE_IS_HIGH + bool + default y + endif # BOARD_LENOVO_T400

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New patch to review for coreboot: lenovo/x60: transition to device_t
by Antonello Dettori 30 Aug '16

30 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16372 -gerrit commit 5ca0692f533ea603eb50c699d6ff6c07c39acdeb Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:15:49 2016 +0200 lenovo/x60: transition to device_t Replace the use of the old device_t definition inside mainboard/lenovo/x60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/lenovo/x60/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index aabbf65..c735ce2 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -102,7 +102,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0x06);

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New patch to review for coreboot: northbridge/intel/i945: transition to device_t
by Antonello Dettori 30 Aug '16

30 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16371 -gerrit commit d16858e219d6032b32e3e71b66965e3fd22a0711 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:11:24 2016 +0200 northbridge/intel/i945: transition to device_t Replace the use of the old device_t definition inside northbridge/intel/i945. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/i945/debug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index d26e84e..65189bd 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -23,7 +23,7 @@ void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -61,7 +61,7 @@ void dump_pci_device(unsigned dev) void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) {

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New patch to review for coreboot: southbridge/intel/i82801gx: transition to device_t
by Antonello Dettori 30 Aug '16

30 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16370 -gerrit commit 309d19b4e87690aba735f0f98868a6be79c38c1f Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:05:32 2016 +0200 southbridge/intel/i82801gx: transition to device_t Replace the use of the old device_t definition inside southbridge/intel/i82801gx. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ia257318a7068b54739f319bfbba35f2a07826940 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/i82801gx/early_smbus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 2f9cdeb..47fe5f6 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3);

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New patch to review for coreboot: device/pci.h: change #ifdef argument to __SIMPLE_DEVICE__
by Antonello Dettori 30 Aug '16

30 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16369 -gerrit commit bb1e5eec215ebda12a5ed1093a8b517579624c06 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:18:06 2016 +0200 device/pci.h: change #ifdef argument to __SIMPLE_DEVICE__ Change the argument to #ifdef from __PRE_RAM__ to __SIMPLE_DEVICE__ in order to account for the coreboot stages that do not define device_t and are not __PRE_RAM__ (i.e. smm) device_t Change-Id: Ic6e9b504803622b60b5217c9432ce57caefc5065 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/include/device/pci.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 9ef3614..e167752 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -108,13 +108,13 @@ static inline const struct pci_operations *ops_pci(device_t dev) #endif /* ! __SIMPLE_DEVICE__ */ -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); -#else /* !__PRE_RAM__ */ +#else /* !__SIMPLE_DEVICE__ */ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ void pci_early_bridge_init(void); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base);

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coreboot-gerrit August 2016