coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/skylake: Use postcar functions for setting up new stack
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16332 -gerrit commit b45967119e2201c08a206e1baaf040ae05b9d52b Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Aug 26 21:16:01 2016 +0530 soc/intel/skylake: Use postcar functions for setting up new stack Setup stack and MTRRs using the postcar funtions provided in postcar_loader.c. Change-Id: Ia5771e70386dbae9fa181e3635021dd187345123 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/romstage/romstage_fsp20.c | 50 +++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 57b2a52..0d827ab 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -24,16 +24,24 @@ #include <console/console.h> #include <device/pci_def.h> #include <fsp/util.h> +#include <fsp/memmap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <timestamp.h> #include <vboot/vboot_common.h> +/* + * Romstage needs some stack for decompressing ramstage images, since the lzma + * lib keeps its state on the stack during romstage. + */ +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + asmlinkage void *car_stage_c_entry(void) { bool s3wake; - void *top_of_stack; + struct postcar_frame pcf; + uintptr_t top_of_ram; struct chipset_power_state *ps; console_init(); @@ -46,8 +54,44 @@ asmlinkage void *car_stage_c_entry(void) s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); - top_of_stack = setup_stack_and_mtrrs(); - return top_of_stack; + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + assert(ALIGN_DOWN(top_of_ram, 1*MiB) == top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, + MTRR_TYPE_WRBACK); + } + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, + CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + return postcar_commit_mtrrs(&pcf); } static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)

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Patch set updated for coreboot: kunimitsu: Add initial FSP2.0 support
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16301 -gerrit commit a779af6035ef798569b9091b4fe79c494ca09471 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Aug 23 13:38:19 2016 +0530 kunimitsu: Add initial FSP2.0 support Add placeholders for functions required when skylake uses FSP2.0 driver, keeping the fsp1.1 flow intact. Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/intel/kunimitsu/Makefile.inc | 4 ++++ src/mainboard/intel/kunimitsu/ramstage.c | 2 +- src/mainboard/intel/kunimitsu/romstage_fsp20.c | 21 +++++++++++++++++++++ src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +- 4 files changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index cafa12c..86be420 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -34,3 +34,7 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs)) +endif diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 563c715..44fb9cd 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -16,7 +16,7 @@ #include <soc/ramstage.h> #include "gpio.h" -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +void mainboard_silicon_init_params(FSP_SIL_UPD *params) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c new file mode 100644 index 0000000..10bdd21 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> + +void mainboard_memory_init_params(struct FSPM_UPD *mupd) +{ + /* TODO: Read and copy SPD and fill up Rcomp and DQ param */ +} diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 62d6fd4..0a9cb0f 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -14,7 +14,7 @@ ## GNU General Public License for more details. ## -romstage-y += spd.c +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c SPD_BIN = $(obj)/spd.bin

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Patch set updated for coreboot: kunimitsu: Add FSP 2.0 support in romstage
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16316 -gerrit commit caf57c79d6e020f984d96c647a3682a48aa9df98 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Wed Aug 24 20:50:54 2016 +0530 kunimitsu: Add FSP 2.0 support in romstage Populate mainboard related Memory Init Params i.e, SPD Rcomp values, DQ and DQs values. Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kunimitsu/devicetree.cb | 3 + src/mainboard/intel/kunimitsu/pei_data.c | 6 +- src/mainboard/intel/kunimitsu/romstage.c | 11 +--- src/mainboard/intel/kunimitsu/romstage_fsp20.c | 82 +++++++++++++++++++++++++- src/mainboard/intel/kunimitsu/spd/spd.h | 20 +++++++ 5 files changed, 106 insertions(+), 16 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 2aa3d95..a5789b0 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -187,6 +187,9 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + # Enable/Disable VMX feature + register "VmxEnable" = "0" + # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c index 3b0237e..b2e47f8 100644 --- a/src/mainboard/intel/kunimitsu/pei_data.c +++ b/src/mainboard/intel/kunimitsu/pei_data.c @@ -19,11 +19,7 @@ #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include "boardid.h" - -/* PCH_MEM_CFG[3:0] */ -#define MAX_MEMORY_CONFIG 0x10 -#define RCOMP_TARGET_PARAMS 0x5 -#define K4E6E304EE_MEM_ID 0x3 +#include "spd/spd.h" void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 84c2b6f..29ffb61 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -25,16 +25,7 @@ void mainboard_romstage_entry(struct romstage_params *params) { - /* PCH_MEM_CFG[3:0] */ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, - ARRAY_SIZE(spd_gpios)); + params->pei_data->mem_cfg_id = get_spd_index(); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index 10bdd21..ab4ea2b 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -13,9 +13,89 @@ * GNU General Public License for more details. */ +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" #include <soc/romstage.h> +#include <soc/gpio.h> +#include "spd/spd.h" +#include <string.h> void mainboard_memory_init_params(struct FSPM_UPD *mupd) { - /* TODO: Read and copy SPD and fill up Rcomp and DQ param */ + struct FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + char *spd_file; + size_t spd_file_len; + int spd_index, spd_span; + + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 6, 5, 4, 7 }, + { 2, 3, 0, 1, 6, 7, 4, 5 } }; + + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/ + static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 21, 40 }; + + spd_index = get_spd_index(); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + memcpy(mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(RcompResistor)); + + if (spd_index == K4E6E304EE_MEM_ID) { + memcpy(mem_cfg->RcompTarget, StrengthendRcompTarget, + sizeof(StrengthendRcompTarget)); + } else { + memcpy(mem_cfg->RcompTarget, RcompTarget, + sizeof(RcompTarget)); + } + + mem_cfg->DqPinsInterleaved = 0; + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + /* Assume same memory in both channels */ + spd_span = spd_index * SPD_LEN; + + mem_cfg->MemorySpdPtr00 = ( uint32_t )spd_file + spd_span; + mem_cfg->MemorySpdDataLen = SPD_LEN; + + if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN + && spd_index != MIC_SINGLE_CHAN) { + mem_cfg->MemorySpdPtr10 = (uint32_t)spd_file + spd_span; + printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n"); + } } diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index cdff9ce..c541c79 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -15,6 +15,10 @@ */ #ifndef MAINBOARD_SPD_H + +#include <gpio.h> +#include "../gpio.h" + #define MAINBOARD_SPD_H #define SPD_LEN 256 @@ -33,4 +37,20 @@ #define HYNIX_SINGLE_CHAN 0x1 #define SAMSUNG_SINGLE_CHAN 0x4 #define MIC_SINGLE_CHAN 0x5 + +/* PCH_MEM_CFG[3:0] */ +#define MAX_MEMORY_CONFIG 0x10 +#define RCOMP_TARGET_PARAMS 0x5 +#define K4E6E304EE_MEM_ID 0x3 + +inline int get_spd_index(void){ + /* PCH_MEM_CFG[3:0] */ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + return(gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); +} #endif

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Patch set updated for coreboot: arch/x86: Make postcar library available irrespective of CONFIG_POSTCAR_STAGE
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16331 -gerrit commit 2c8da704edbcc97c1ee3c76f70e1e249369d5f2f Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Aug 26 21:08:50 2016 +0530 arch/x86: Make postcar library available irrespective of CONFIG_POSTCAR_STAGE postcar_loader.c has a useful library of funtions for setting up stack and MTRRs. Make it available in romstage irrespective of CONFIG_POSTCAR_STAGE for use in stack setup after Dram init. The final step of moving the used and max MTRRs on to stack is moved to a new function, that can be used outside of postcar phase. Change-Id: I322b12577d74268d03fe42a9744648763693cddd Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/include/arch/cpu.h | 6 ++++++ src/arch/x86/postcar_loader.c | 18 ++++++++++++------ 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9b16add..38a2a8c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -213,7 +213,7 @@ romstage-y += memcpy.c romstage-y += memmove.c romstage-y += memset.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c -romstage-$(CONFIG_POSTCAR_STAGE) += postcar_loader.c +romstage-y += postcar_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ifneq ($(CONFIG_ROMCC),y) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 5c26bcf..faa2375 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -274,6 +274,12 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type); /* + * Push used MTRR and Max MTRRs on to the stack + * and return pointer to stack top. + */ +void *postcar_commit_mtrrs(struct postcar_frame *pcf); + +/* * Load and run a program that takes control of execution that * tears down CAR and loads ramstage. The postcar_frame object * indicates how to set up the frame. If caching is enabled at diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index cc1d460..b5d8db0 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -84,6 +84,17 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf, pcf->num_var_mttrs++; } +void *postcar_commit_mtrrs(struct postcar_frame *pcf) +{ + /* + * Place the number of used variable MTRRs on stack then max number + * of variable MTRRs supported in the system. + */ + stack_push(pcf, pcf->num_var_mttrs); + stack_push(pcf, pcf->max_var_mttrs); + return (void *) pcf->stack; +} + void run_postcar_phase(struct postcar_frame *pcf) { struct prog prog = @@ -93,12 +104,7 @@ void run_postcar_phase(struct postcar_frame *pcf) .prog = &prog, }; - /* - * Place the number of used variable MTRRs on stack then max number - * of variable MTRRs supported in the system. - */ - stack_push(pcf, pcf->num_var_mttrs); - stack_push(pcf, pcf->max_var_mttrs); + postcar_commit_mtrrs(pcf); if (prog_locate(&prog)) die("Failed to locate after CAR program.\n");

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Patch set updated for coreboot: mainboard/intel/kunimitsu:[WIP] Add FSP 2.0 support in ramstage
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16356 -gerrit commit c1d9a4c08ae42f56e8a5db583798f39c9631b742 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Aug 30 20:50:03 2016 +0530 mainboard/intel/kunimitsu:[WIP] Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Change-Id: I8a9ef156a4dea89b80757f2a186d7181526b805a --- src/mainboard/intel/kunimitsu/devicetree.cb | 3 +++ src/mainboard/intel/kunimitsu/ramstage.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index a5789b0..ee3dcf6 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -193,6 +193,9 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" + # Enable/Disable VMX + register "VmxEnable" = "0" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 44fb9cd..c67bf79 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -13,11 +13,13 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <soc/ramstage.h> #include "gpio.h" void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + printk(BIOS_DEBUG, "Configure Gpio...\n"); /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));

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Patch set updated for coreboot: soc/intel/skylake:[WIP] Add FSP 2.0 support in ramstage
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16355 -gerrit commit 4a10a5a5c7989663b735f1e1a02a73d98313d31c Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Aug 30 20:47:13 2016 +0530 soc/intel/skylake:[WIP] Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Implement lb_framebuffer for pre OS screens. Change-Id: Ia3c1dd741fb657ec14e305a1ef7cebc2befff188 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 26 +- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/chip.h | 13 + src/soc/intel/skylake/chip_fsp20.c | 514 ++++++++++++++++++++- src/soc/intel/skylake/igd.c | 6 +- src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 3 +- src/soc/intel/skylake/lb_framebuffer.c | 47 ++ 7 files changed, 602 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index edf5db3..7cb963a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -35,14 +35,13 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE - select PLATFORM_USES_FSP1_1 + select PLATFORM_USES_FSP2_0 select REG_SCRIPT select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select RTC select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET @@ -54,6 +53,25 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC +config PLATFORM_USES_FSP2_0 + select ADD_VBT_DATA_FILE + select SOC_INTEL_COMMON_GFX_OPREGION + +config PLATFORM_USES_FSP1_1 + select GOP_SUPPORT + select DISPLAY_FSP_ENTRY_POINTS + select HAVE_FSP_BIN + +config FSP_FILE + string + depends on PLATFORM_USES_FSP1_1 + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/fsp/FSP.fd" + +config FSP_IMAGE_ID_STRING + string + depends on PLATFORM_USES_FSP1_1 + default "$SKLFSP$" + config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC @@ -213,4 +231,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config VBT_FILE + string "VBT binary path and filename" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 80562e4..15b7634 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -58,6 +58,7 @@ ramstage-y += flash_controller.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += igd.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += lb_framebuffer.c ramstage-y += lpc.c ramstage-y += me_status.c ramstage-y += memmap.c diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 62e28e6..85f6054 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -273,6 +273,19 @@ struct soc_intel_skylake_config { u16 PchConfigSubSystemVendorId; /* Subsystem ID of the PCH devices*/ u16 PchConfigSubSystemId; + + /* + * Determine if WLAN wake from Sx, corresponds to the + * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanEnable; + + /* + * Determine if WLAN wake from DeepSx, corresponds to + * the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanDeepSxEnable; + /* * Corresponds to the "WOL Enable Override" bit in the General PM * Configuration B (GEN_PMCON_B) register diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 215530c..7a403e4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify @@ -18,13 +17,524 @@ #include <bootstate.h> #include <device/pci.h> #include <fsp/api.h> +#include <arch/acpi.h> +#include <chip.h> +#include <bootstate.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <soc/acpi.h> +#include <soc/interrupt.h> +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <string.h> + +static const struct SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { + /* + * cAVS(Audio, Voice, Speach), INTA is default, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + /* + * SMBus Controller, no default value, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + /* TraceHub, INTA is default, RO register */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ), + /* + * SerialIo: UART #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[7] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), + /* + * SerialIo: UART #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[8] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), + /* + * SerialIo: SPI #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[10] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), + /* + * SerialIo: SPI #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[11] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + /* SCS: eMMC (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + /* SCS: SDIO (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + /* SCS: SDCard (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + /* PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), + /* PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), + /* PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), + /* PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + /* + * PCI Express Port 1, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + /* + * PCI Express Port 2, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + /* + * PCI Express Port 3, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + /* + * PCI Express Port 4, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + /* + * PCI Express Port 5, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + /* + * PCI Express Port 6, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + /* + * PCI Express Port 7, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + /* + * PCI Express Port 8, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + /* + * SerialIo UART Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[9] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + /* + * SerialIo UART Controller #5, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[6] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + /* + * SerialIo UART Controller #4, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[5] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + /* + * SATA Controller, INTA is default, + * programmed in PciCfgSpace + 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, + PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + /* CSME: HECI #1 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME), int_A, HECI_1_IRQ), + /* CSME: HECI #2 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_2), int_B, HECI_2_IRQ), + /* CSME: IDE-Redirection (IDE-R) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_IDER), int_C, IDER_IRQ), + /* CSME: Keyboard and Text (KT) Redirection */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_KT), int_D, KT_IRQ), + /* CSME: HECI #3 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_3), int_A, HECI_3_IRQ), + /* + * SerialIo I2C Controller #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[1] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + /* + * SerialIo I2C Controller #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[2] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + /* + * SerialIo I2C Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[3] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + /* + * SerialIo I2C Controller #3, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[4] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + /* + * USB 3.0 xHCI Controller, no default value, + * programmed in PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + /* USB Device Controller (OTG) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + /* Thermal Subsystem */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THRMAL_IRQ), + /* Camera IO Host Controller */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + /* Integrated Sensor Hub */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, + PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) +}; + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +const char *soc_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_IGD: return "GFX0"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_USBOTG: return "XDCI"; + case PCH_DEVFN_THERMAL: return "THRM"; + case PCH_DEVFN_CIO: return "ICIO"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_ME: return "MEI1"; + case PCH_DEVFN_ME_2: return "MEI2"; + case PCH_DEVFN_ME_IDER: return "MEID"; + case PCH_DEVFN_ME_KT: return "MEKT"; + case PCH_DEVFN_ME_3: return "MEI3"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_EMMC: return "EMMC"; + case PCH_DEVFN_SDIO: return "SDIO"; + case PCH_DEVFN_SDCARD: return "SDXC"; + case PCH_DEVFN_LPC: return "LPCB"; + case PCH_DEVFN_P2SB: return "P2SB"; + case PCH_DEVFN_PMC: return "PMC_"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_SPI: return "FSPI"; + case PCH_DEVFN_GBE: return "IGBE"; + case PCH_DEVFN_TRACEHUB:return "THUB"; + } + + return NULL; +} +#endif + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .ops_pci_bus = &pci_bus_default_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = &soc_init_cpus, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = generate_cpu_entries, +#endif +}; + +static void soc_enable(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle PCH device enable */ + if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD && + (dev->ops == NULL || dev->ops->enable == NULL)) { + pch_enable_dev(dev); + } + } +} + +struct chip_operations soc_intel_skylake_ops = { + CHIP_NAME("Intel 6th Gen") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, +}; /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd) { + struct FSP_S_CONFIG *params = &supd->FspsConfig; + struct FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; + static struct soc_intel_skylake_config *config; + int i, intdeventry; + uintptr_t *vbt_data = NULL; + u8 irq_config[PCH_MAX_IRQ_CONFIG]; + + int is_s3_wakeup = acpi_is_wakeup_s3(); + + struct device *dev = SA_DEV_ROOT; + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + mainboard_silicon_init_params(params); + + /* Load VBT */ + if (!is_s3_wakeup) { + vbt_data = (uintptr_t *) fsp_load_vbt(); + } + + params->GraphicsConfigPtr = (u32) vbt_data; + + /* Get Device Int Count */ + intdeventry = ARRAY_SIZE(devintconfig); + + /*update irq table */ + memcpy((struct SI_PCH_DEVICE_INTERRUPT_CONFIG *) + (params->DevIntConfigPtr), devintconfig, intdeventry * + sizeof(struct SI_PCH_DEVICE_INTERRUPT_CONFIG)); + + params->NumOfDevIntConfig = intdeventry; + /* PxRC to IRQ programing */ + for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) { + switch (i) { + case PCH_PARC: + case PCH_PCRC: + case PCH_PDRC: + case PCH_PERC: + case PCH_PFRC: + case PCH_PGRC: + case PCH_PHRC: + irq_config[i] = PCH_IRQ11; + break; + case PCH_PBRC: + irq_config[PCH_PBRC] = PCH_IRQ10; + break; + } + } + + memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); + + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = + config->usb2_ports[i].enable; + params->Usb2AfePetxiset[i] = + config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = + config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = + config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = + config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = + config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + for (i = 0; i < ARRAY_SIZE(config->i2c); i++) + params->SerialIoI2cVoltage[i] = config->i2c[i].voltage; + + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(params, i, &config->domain_vr_config[i]); + + /* GPIO IRQ Route The valid values is 14 or 15 */ + if (config->GpioIrqSelect == 0) + params->GpioIrqRoute = GPIO_IRQ14; + else + params->GpioIrqRoute = config->GpioIrqSelect; + + /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23 */ + if (config->SciIrqSelect == 0) + params->SciIrqSelect = SCI_IRQ9; + else + params->SciIrqSelect = config->SciIrqSelect; + /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23 */ + if (config->TcoIrqSelect == 0) + params->TcoIrqSelect = TCO_IRQ9; + else + params->TcoIrqSelect = config->TcoIrqSelect; + /* TCO Irq enable/disable */ + params->TcoIrqEnable = config->TcoIrqEnable; + + params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; + params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; + params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + params->PchPmDeepSxPol = config->PmConfigDeepSxPol; + params->PchLanEnable = config->EnableLan; + + params->SataEnable = config->EnableSata; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + + params->PchHdaEnable = config->EnableAzalia; + params->PchHdaDspEnable = config->DspEnable; + params->PchHdaIoBufferOwnership = config->IoBufferOwnership; + + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(params->PcieRpClkReqSupport)); + memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(params->PcieRpClkReqNumber)); + + params->XdciEnable = config->XdciEnable; + params->SsicPortEnable = config->SsicPortEnable; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, + sizeof(params->SerialIoDevMode)); + params->PchCio2Enable = config->Cio2Enable; + + params->ScsEmmcEnabled = config->ScsEmmcEnabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->ScsSdCardEnabled = config->ScsSdCardEnabled; + + params->PchIshEnable = config->IshEnable; + params->Heci3Enabled = config->Heci3Enabled; + params->LogoPtr = config->LogoPtr; + params->LogoSize = config->LogoSize; + params->Device4Enable = config->Device4Enable; + + params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; + params->PchSubSystemId = config->PchConfigSubSystemId; + params->PchLockDownSpiEiss = config->LockDownConfigSpiEiss; + params->PchLockDownBiosLock = config->LockDownConfigBiosLock; + params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; + params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; + params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; + params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; + params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; + params->PchPmLpcClockRun = config->PmConfigPciClockRun; + params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; + params->PchPmPwrBtnOverridePeriod = + config->PmConfigPwrBtnOverridePeriod; + params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + params->PchSirqEnable = config->SerialIrqConfigSirqEnable; + params->PchSirqMode = config->SerialIrqConfigSirqMode; + + params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit; + params->CpuConfig.Bits.VmxEnable = config->VmxEnable; + params->SendVrMbxCmd = config->SendVrMbxCmd; + + /* Show SPI controller if enabled in devicetree.cb */ + dev = dev_find_slot(0, PCH_DEVFN_SPI); + params->ShowSpiController = dev->enabled; + + params->PchCio2Enable = config->Cio2Enable; + + tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; + tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; + tconfig->PchLockDownBiosInterface = config->LockDownConfigBiosInterface; + params->PchLockDownBiosLock = config->LockDownConfigBiosLock; +} + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + else + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + (device << 16) | vendor); } struct pci_operations soc_pci_ops = { - /* TODO: Add set subsystem id function */ + .set_subsystem = &pci_set_subsystem }; +/* Mainboard GPIO Configuration */ +__attribute__((weak)) void mainboard_silicon_init_params(struct FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index 93f05cc..42463ee 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -79,7 +79,8 @@ static void igd_init(struct device *dev) gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); } - if (IS_ENABLED(CONFIG_GOP_SUPPORT)) + if (IS_ENABLED(CONFIG_GOP_SUPPORT) || + IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE)) return; /* IGD needs to be Bus Master */ @@ -153,7 +154,8 @@ static unsigned long write_acpi_igd_opregion(device_t device, igd_opregion_t *opregion; /* If GOP is not used, exit here */ - if (!IS_ENABLED(CONFIG_GOP_SUPPORT)) + if ((!IS_ENABLED(CONFIG_GOP_SUPPORT)) && + (!IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE))) return current; /* If IGD is disabled, exit here */ diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index 3a9d96b..fb6ac46 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -19,7 +19,6 @@ #include <chip.h> #include <device/device.h> - #include <fsp/api.h> #include <fsp/util.h> #include <soc/intel/common/opregion.h> @@ -27,7 +26,7 @@ #define FSP_SIL_UPD struct FSP_S_CONFIG #define FSP_MEM_UPD struct FSP_M_CONFIG -void intel_silicon_init(void); +inline void intel_silicon_init(void) { fsp_silicon_init(); } void mainboard_silicon_init_params(struct FSP_S_CONFIG *params); void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/skylake/lb_framebuffer.c b/src/soc/intel/skylake/lb_framebuffer.c new file mode 100644 index 0000000..b9a3cca --- /dev/null +++ b/src/soc/intel/skylake/lb_framebuffer.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> + +static uintptr_t framebuffer_bar = (uintptr_t)NULL; + +void lb_framebuffer(struct lb_header *header) +{ + enum cb_err ret; + struct lb_framebuffer *framebuffer; + + framebuffer = (void *)lb_new_record(header); + ret = fsp_fill_lb_framebuffer(framebuffer); + if (ret != CB_SUCCESS) { + printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); + return; + } + + if (!framebuffer_bar) { + printk(BIOS_ALERT, "Framebuffer BAR 0x%x \n", + (uint32_t)framebuffer->physical_address); + printk(BIOS_ALERT, "Framebuffer BAR invalid (00:02.0 BAR2)\n"); + return; + } + + /* + * Resource allocator can move the BAR + * around after FSP configures it + */ + framebuffer->physical_address = framebuffer_bar; + printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", + framebuffer->physical_address); +}

1 0

New patch to review for coreboot: Makefile.inc: lint: Update to run lint-server scripts
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16362 -gerrit commit b4b642558dc24fa3a0ae57db9091f691ef21d445 Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 30 09:39:48 2016 -0600 Makefile.inc: lint: Update to run lint-server scripts - Add junit-amend command so that junit.xml doesn't get overwritten - Add lint-server as a valid option - Call lint with lint-server --junit-amend from what-jenkins-does - Add final newlines check as lint-server script Change-Id: I7e4156844b8c60790e03a0e43564610bb0c8f386 Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 1 + util/lint/lint | 8 ++++++-- util/lint/lint-server-015-final-newlines | 17 +++++++++++++++++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6225152..084ba56 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -997,6 +997,7 @@ JENKINS_PAYLOAD?=none CPUS?=4 what-jenkins-does: util/lint/lint lint-stable --junit + util/lint/lint lint-server --junit-amend util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) (cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml) diff --git a/util/lint/lint b/util/lint/lint index 826685d..db24c7d 100755 --- a/util/lint/lint +++ b/util/lint/lint @@ -14,7 +14,7 @@ #set -x # uncomment for debug usage () { - printf "Usage: %s <lint|lint-stable> [--junit]\n" "$0" + printf "Usage: %s <lint|lint-stable|lint-server> [--junit]\n" "$0" } #write to the junit xml file if --junit was specified @@ -25,7 +25,8 @@ junit_write () { } #verify the first command line parameter -if [ -z "$1" ] || [ "$1" != "lint" ] && [ "$1" != "lint-stable" ]; then +if [ -z "$1" ] || [ "$1" != "lint" ] && [ "$1" != "lint-stable" ] && \ + [ "$1" != "lint-server" ]; then usage exit 1 fi @@ -40,6 +41,9 @@ if [ "$2" = "--junit" ]; then JUNIT=1 echo '<?xml version="1.0" encoding="utf-8"?>' > "$XMLFILE" junit_write '<testsuite>' +elif [ "$2" = "--junit-amend" ]; then + JUNIT=1 + junit_write '<testsuite>' else JUNIT=0 fi diff --git a/util/lint/lint-server-015-final-newlines b/util/lint/lint-server-015-final-newlines new file mode 100755 index 0000000..c3f66c0 --- /dev/null +++ b/util/lint/lint-server-015-final-newlines @@ -0,0 +1,17 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: Check that files end with a single newline + +lint-015-final-newlines

1 0

New patch to review for coreboot: Fix newlines at the end of files
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16361 -gerrit commit ccdc16eff353dd7e9ea6316e16217ae9da71874b Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 29 15:55:06 2016 -0600 Fix newlines at the end of files All but ga-g41m-es2l/cmos.default had multiple final newlines. ga-g41m-es2l/cmos.default had no final newline. Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/libpayload/drivers/timer/Kconfig | 1 - payloads/libpayload/drivers/usb/Kconfig | 1 - src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +- src/soc/intel/apollolake/meminit.c | 1 - src/soc/intel/skylake/bootblock/smbus.c | 1 - src/superio/nuvoton/nct6791d/superio.c | 1 - util/crossgcc/patches/binutils-2.26.1_aarch.patch | 1 - 7 files changed, 1 insertion(+), 7 deletions(-) diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig index 8f047fa..0b981b0 100644 --- a/payloads/libpayload/drivers/timer/Kconfig +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -126,4 +126,3 @@ config TIMER_MTK_ADDRESS default 0x10008048 help Address of GPT4's counter register to read the FREERUN-mode timer value. - diff --git a/payloads/libpayload/drivers/usb/Kconfig b/payloads/libpayload/drivers/usb/Kconfig index e1b68f7..5ef8068 100644 --- a/payloads/libpayload/drivers/usb/Kconfig +++ b/payloads/libpayload/drivers/usb/Kconfig @@ -126,4 +126,3 @@ config UDC_DWC2 help Select this option to add the driver for Designware USB device controller. - diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default index c6ce45f..303c4c2 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default @@ -3,4 +3,4 @@ baud_rate=115200 debug_level=Spew power_on_after_fail=Enable nmi=Enable -gfx_uma_size=64M \ No newline at end of file +gfx_uma_size=64M diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 03e9ac4..8158c5f 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -337,4 +337,3 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku) mem_info->dimm_cnt = index; printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } - diff --git a/src/soc/intel/skylake/bootblock/smbus.c b/src/soc/intel/skylake/bootblock/smbus.c index bb305d5..14a9666 100644 --- a/src/soc/intel/skylake/bootblock/smbus.c +++ b/src/soc/intel/skylake/bootblock/smbus.c @@ -44,4 +44,3 @@ void enable_smbus(void) { reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); } - diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index 0a0f0be..f0da0367 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -99,4 +99,3 @@ struct chip_operations superio_nuvoton_nct6791d_ops = { CHIP_NAME("NUVOTON NCT6791D Super I/O") .enable_dev = enable_dev, }; - diff --git a/util/crossgcc/patches/binutils-2.26.1_aarch.patch b/util/crossgcc/patches/binutils-2.26.1_aarch.patch index 1e709d1..4a04418 100644 --- a/util/crossgcc/patches/binutils-2.26.1_aarch.patch +++ b/util/crossgcc/patches/binutils-2.26.1_aarch.patch @@ -90,4 +90,3 @@ index 0000000..594ad7c + -- 1.7.1 -

1 0

New patch to review for coreboot: util/lint: add stable checkpatch for jenkins
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16360 -gerrit commit 60091f62cc9ec4ebe992fbffd27b16e106da8f30 Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 29 15:49:02 2016 -0600 util/lint: add stable checkpatch for jenkins The checkpatch script takes a while to run, so don't add it to the lint-stable checks which run pre-commit. Change-Id: I907176c21c057564495b75133ba10b0761c9fe7b Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-server-007-checkpatch | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/util/lint/lint-server-007-checkpatch b/util/lint/lint-server-007-checkpatch new file mode 100755 index 0000000..5fbed01 --- /dev/null +++ b/util/lint/lint-server-007-checkpatch @@ -0,0 +1,44 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# +# DESCR: Run checkpatch on directories that are known good + +# Top level +util/lint/lint-007-checkpatch "src/acpi" + +#src/cpu +util/lint/lint-007-checkpatch "src/cpu/armltd src/cpu/qemu-power8 \ +src/cpu/qemu-x86" + +#src/drivers +util/lint/lint-007-checkpatch "src/drivers/dec src/drivers/gic \ +src/drivers/ti" + +#src/ec +util/lint/lint-007-checkpatch "src/ec/purism" + +#src/include +util/lint/lint-007-checkpatch "src/include/boot src/include/superio \ +src/include/sys" + +#src/mainboard +util/lint/lint-007-checkpatch "src/mainboard/adlink src/mainboard/linutop \ +src/mainboard/purism src/mainboard/ti" + +# src/soc +util/lint/lint-007-checkpatch "src/soc/rdc" + +# src/superio +util/lint/lint-007-checkpatch "src/superio/acpi src/superio/common"

1 0

New patch to review for coreboot: lint/lint-007-checkpatch: Update lint script
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16359 -gerrit commit 0a60c2cf162186bbc7fcce903ee0ed5fbbe925f7 Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 29 15:40:57 2016 -0600 lint/lint-007-checkpatch: Update lint script - Check Kconfig files as well. - Accept a list of directories to check as a command line argument. - Only look at src & util directories by default. - Skip src/vendorcode. - Remove bypass of payloads/coreinfo/util/kconfig directory, it no longer exists. Change-Id: Ia522d3ddc29914220bdaae36ea23ded7338c48fd Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-007-checkpatch | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/util/lint/lint-007-checkpatch b/util/lint/lint-007-checkpatch index 9d9d96e..ef4feab 100755 --- a/util/lint/lint-007-checkpatch +++ b/util/lint/lint-007-checkpatch @@ -12,12 +12,31 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -# DESCR: Checkpatch on all .c and .h files in the tree +# DESCR: Checkpatch on .c, .h, & Kconfig files in the tree LC_ALL=C export LC_ALL -util/lint/checkpatch.pl --show-types --file $( git ls-files \*.[ch] | \ - grep -v ^payloads/libpayload/util/kconfig | \ - grep -v ^payloads/libpayload/curses/PDCurses-3.4 | \ - grep -v ^payloads/coreinfo/util/kconfig | \ - grep -v ^util/kconfig \ - ) + +# GNU BRE syntax list of files to examine +INCLUDED_FILES='.*\.[ch]\|Kconfig.*$' + +EXCLUDED_DIRS="^payloads/libpayload/util/kconfig\|\ +^payloads/libpayload/curses/PDCurses\|\ +^util/kconfig\|\ +^src/vendorcode" + +#space separated list of directories to test +if [ "$1" = "" ]; then + INCLUDED_DIRS="src util" +else + INCLUDED_DIRS="$1" +fi + +# We want word splitting here, so disable the shellcheck warnings +# shellcheck disable=SC2046,SC2086 +FILELIST=$( git ls-files $INCLUDED_DIRS | \ + grep $INCLUDED_FILES | \ + grep -v $EXCLUDED_DIRS ) + +for FILE in $FILELIST; do + util/lint/checkpatch.pl --show-types --file --quiet "$FILE" +done

1 0

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coreboot-gerrit August 2016