coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: checkpatch.pl: ignore '#define asmlinkage'
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16358 -gerrit commit 10376b39edfd559094d79f0ebd44636f23478ee3 Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 29 15:32:10 2016 -0600 checkpatch.pl: ignore '#define asmlinkage' checkpatch warns that the asmlinkage storage class should be at the beginning of the declaration when we define it to be an empty value. Change-Id: I12292d5b42bf6da9130bb969ebe00fca8efcf049 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/checkpatch.pl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 646cb0f..84574f1 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -5340,7 +5340,8 @@ sub process { } # Check that the storage class is at the beginning of a declaration - if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) { +# coreboot: skip complaint about our '#define asmlinkage' lines + if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/ && $line !~ /^.\s*#\s*define\s+$Storage\b/) { WARN("STORAGE_CLASS", "storage class should be at the beginning of the declaration\n" . $herecurr) }

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New patch to review for coreboot: checkpatch.pl: Force raw_line to return a defined value
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16357 -gerrit commit a5aba673a94b18f310f5b687d7f7874221b08d38 Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 29 15:30:23 2016 -0600 checkpatch.pl: Force raw_line to return a defined value Fixes the warning: Use of uninitialized value in concatenation (.) or string at util/lint/checkpatch.pl line 4739 Change-Id: Idc3c631735a595517d77cb8b8ec67e1ac00b6685 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/checkpatch.pl | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index eb03bc7..646cb0f 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -1495,7 +1495,13 @@ sub raw_line { $cnt--; } - return $line; + # coreboot: This probably shouldn't happen, but it does. + # Return a defined value so we don't get an error. + if (defined $line) { + return $line; + } else { + return ""; + } } sub cat_vet {

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Patch set updated for coreboot: src/lib: Fix checkpatch warnings
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16011 -gerrit commit fcb978f494175228c4ca85946bdb800a6e0afd09 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Aug 1 12:20:40 2016 -0700 src/lib: Fix checkpatch warnings The script checkpatch.pl complains about these files. Fix the warnings. Change-Id: I4271cc35bb101447a316a75273cf8a6e95ed62d5 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/lib/tpm_error_messages.h | 452 +++++++++++++++++++++---------------------- src/lib/trace.c | 4 +- 2 files changed, 228 insertions(+), 228 deletions(-) diff --git a/src/lib/tpm_error_messages.h b/src/lib/tpm_error_messages.h index 279bc2b..f9a968f 100644 --- a/src/lib/tpm_error_messages.h +++ b/src/lib/tpm_error_messages.h @@ -16,235 +16,235 @@ #define TPM_E_NON_FATAL 0x800 typedef struct tpm_error_info { - const char* name; - uint32_t code; - const char* description; + const char *name; + uint32_t code; + const char *description; } tpm_error_info; tpm_error_info tpm_error_table[] = { -{ "TPM_AUTHFAIL", TPM_E_BASE + 1, -"Authentication failed" }, -{ "TPM_BADINDEX", TPM_E_BASE + 2, -"The index to a PCR, DIR or other register is incorrect" }, -{ "TPM_BAD_PARAMETER", TPM_E_BASE + 3, -"One or more parameter is bad" }, -{ "TPM_AUDITFAILURE", TPM_E_BASE + 4, -"An operation completed successfully\n\ -but the auditing of that operation failed" }, -{ "TPM_CLEAR_DISABLED", TPM_E_BASE + 5, -"The clear disable flag is set and all clear operations now require\n\ -physical access" }, -{ "TPM_DEACTIVATED", TPM_E_BASE + 6, -"The TPM is deactivated" }, -{ "TPM_DISABLED", TPM_E_BASE + 7, -"The TPM is disabled" }, -{ "TPM_DISABLED_CMD", TPM_E_BASE + 8, -"The target command has been disabled" }, -{ "TPM_FAIL", TPM_E_BASE + 9, -"The operation failed" }, -{ "TPM_BAD_ORDINAL", TPM_E_BASE + 10, -"The ordinal was unknown or inconsistent" }, -{ "TPM_INSTALL_DISABLED", TPM_E_BASE + 11, -"The ability to install an owner is disabled" }, -{ "TPM_INVALID_KEYHANDLE", TPM_E_BASE + 12, -"The key handle can not be interpreted" }, -{ "TPM_KEYNOTFOUND", TPM_E_BASE + 13, -"The key handle points to an invalid key" }, -{ "TPM_INAPPROPRIATE_ENC", TPM_E_BASE + 14, -"Unacceptable encryption scheme" }, -{ "TPM_MIGRATEFAIL", TPM_E_BASE + 15, -"Migration authorization failed" }, -{ "TPM_INVALID_PCR_INFO", TPM_E_BASE + 16, -"PCR information could not be interpreted" }, -{ "TPM_NOSPACE", TPM_E_BASE + 17, -"No room to load key" }, -{ "TPM_NOSRK", TPM_E_BASE + 18, -"There is no SRK set" }, -{ "TPM_NOTSEALED_BLOB", TPM_E_BASE + 19, -"An encrypted blob is invalid or was not created by this TPM" }, -{ "TPM_OWNER_SET", TPM_E_BASE + 20, -"There is already an Owner" }, -{ "TPM_RESOURCES", TPM_E_BASE + 21, -"The TPM has insufficient internal resources to perform the requested action" }, -{ "TPM_SHORTRANDOM", TPM_E_BASE + 22, -"A random string was too short" }, -{ "TPM_SIZE", TPM_E_BASE + 23, -"The TPM does not have the space to perform the operation" }, -{ "TPM_WRONGPCRVAL", TPM_E_BASE + 24, -"The named PCR value does not match the current PCR value" }, -{ "TPM_BAD_PARAM_SIZE", TPM_E_BASE + 25, -"The paramSize argument to the command has the incorrect value" }, -{ "TPM_SHA_THREAD", TPM_E_BASE + 26, -"There is no existing SHA-1 thread" }, -{ "TPM_SHA_ERROR", TPM_E_BASE + 27, -"The calculation is unable to proceed because the existing SHA-1\n\ -thread has already encountered an error" }, -{ "TPM_FAILEDSELFTEST", TPM_E_BASE + 28, -"Self-test has failed and the TPM has shutdown" }, -{ "TPM_AUTH2FAIL", TPM_E_BASE + 29, -"The authorization for the second key in a 2 key function\n\ -failed authorization" }, -{ "TPM_BADTAG", TPM_E_BASE + 30, -"The tag value sent to for a command is invalid" }, -{ "TPM_IOERROR", TPM_E_BASE + 31, -"An IO error occurred transmitting information to the TPM" }, -{ "TPM_ENCRYPT_ERROR", TPM_E_BASE + 32, -"The encryption process had a problem" }, -{ "TPM_DECRYPT_ERROR", TPM_E_BASE + 33, -"The decryption process did not complete" }, -{ "TPM_INVALID_AUTHHANDLE", TPM_E_BASE + 34, -"An invalid handle was used" }, -{ "TPM_NO_ENDORSEMENT", TPM_E_BASE + 35, -"The TPM does not a EK installed" }, -{ "TPM_INVALID_KEYUSAGE", TPM_E_BASE + 36, -"The usage of a key is not allowed" }, -{ "TPM_WRONG_ENTITYTYPE", TPM_E_BASE + 37, -"The submitted entity type is not allowed" }, -{ "TPM_INVALID_POSTINIT", TPM_E_BASE + 38, -"The command was received in the wrong sequence relative to TPM_Init\n\ -and a subsequent TPM_Startup" }, -{ "TPM_INAPPROPRIATE_SIG", TPM_E_BASE + 39, -"Signed data cannot include additional DER information" }, -{ "TPM_BAD_KEY_PROPERTY", TPM_E_BASE + 40, -"The key properties in TPM_KEY_PARMs are not supported by this TPM" }, -{ "TPM_BAD_MIGRATION", TPM_E_BASE + 41, -"The migration properties of this key are incorrect" }, -{ "TPM_BAD_SCHEME", TPM_E_BASE + 42, -"The signature or encryption scheme for this key is incorrect or not\n\ -permitted in this situation" }, -{ "TPM_BAD_DATASIZE", TPM_E_BASE + 43, -"The size of the data (or blob) parameter is bad or inconsistent\n\ -with the referenced key" }, -{ "TPM_BAD_MODE", TPM_E_BASE + 44, -"A mode parameter is bad, such as capArea or subCapArea for\n\ + {"TPM_AUTHFAIL", TPM_E_BASE + 1, + "Authentication failed"}, + {"TPM_BADINDEX", TPM_E_BASE + 2, + "The index to a PCR, DIR or other register is incorrect"}, + {"TPM_BAD_PARAMETER", TPM_E_BASE + 3, + "One or more parameter is bad"}, + {"TPM_AUDITFAILURE", TPM_E_BASE + 4, + "An operation completed successfully\n\ +but the auditing of that operation failed"}, + {"TPM_CLEAR_DISABLED", TPM_E_BASE + 5, + "The clear disable flag is set and all clear operations now require\n\ +physical access"}, + {"TPM_DEACTIVATED", TPM_E_BASE + 6, + "The TPM is deactivated"}, + {"TPM_DISABLED", TPM_E_BASE + 7, + "The TPM is disabled"}, + {"TPM_DISABLED_CMD", TPM_E_BASE + 8, + "The target command has been disabled"}, + {"TPM_FAIL", TPM_E_BASE + 9, + "The operation failed"}, + {"TPM_BAD_ORDINAL", TPM_E_BASE + 10, + "The ordinal was unknown or inconsistent"}, + {"TPM_INSTALL_DISABLED", TPM_E_BASE + 11, + "The ability to install an owner is disabled"}, + {"TPM_INVALID_KEYHANDLE", TPM_E_BASE + 12, + "The key handle can not be interpreted"}, + {"TPM_KEYNOTFOUND", TPM_E_BASE + 13, + "The key handle points to an invalid key"}, + {"TPM_INAPPROPRIATE_ENC", TPM_E_BASE + 14, + "Unacceptable encryption scheme"}, + {"TPM_MIGRATEFAIL", TPM_E_BASE + 15, + "Migration authorization failed"}, + {"TPM_INVALID_PCR_INFO", TPM_E_BASE + 16, + "PCR information could not be interpreted"}, + {"TPM_NOSPACE", TPM_E_BASE + 17, + "No room to load key"}, + {"TPM_NOSRK", TPM_E_BASE + 18, + "There is no SRK set"}, + {"TPM_NOTSEALED_BLOB", TPM_E_BASE + 19, + "An encrypted blob is invalid or was not created by this TPM"}, + {"TPM_OWNER_SET", TPM_E_BASE + 20, + "There is already an Owner"}, + {"TPM_RESOURCES", TPM_E_BASE + 21, + "The TPM has insufficient internal resources to perform the requested action"}, + {"TPM_SHORTRANDOM", TPM_E_BASE + 22, + "A random string was too short"}, + {"TPM_SIZE", TPM_E_BASE + 23, + "The TPM does not have the space to perform the operation"}, + {"TPM_WRONGPCRVAL", TPM_E_BASE + 24, + "The named PCR value does not match the current PCR value"}, + {"TPM_BAD_PARAM_SIZE", TPM_E_BASE + 25, + "The paramSize argument to the command has the incorrect value"}, + {"TPM_SHA_THREAD", TPM_E_BASE + 26, + "There is no existing SHA-1 thread"}, + {"TPM_SHA_ERROR", TPM_E_BASE + 27, + "The calculation is unable to proceed because the existing SHA-1\n\ +thread has already encountered an error"}, + {"TPM_FAILEDSELFTEST", TPM_E_BASE + 28, + "Self-test has failed and the TPM has shutdown"}, + {"TPM_AUTH2FAIL", TPM_E_BASE + 29, + "The authorization for the second key in a 2 key function\n\ +failed authorization"}, + {"TPM_BADTAG", TPM_E_BASE + 30, + "The tag value sent to for a command is invalid"}, + {"TPM_IOERROR", TPM_E_BASE + 31, + "An IO error occurred transmitting information to the TPM"}, + {"TPM_ENCRYPT_ERROR", TPM_E_BASE + 32, + "The encryption process had a problem"}, + {"TPM_DECRYPT_ERROR", TPM_E_BASE + 33, + "The decryption process did not complete"}, + {"TPM_INVALID_AUTHHANDLE", TPM_E_BASE + 34, + "An invalid handle was used"}, + {"TPM_NO_ENDORSEMENT", TPM_E_BASE + 35, + "The TPM does not a EK installed"}, + {"TPM_INVALID_KEYUSAGE", TPM_E_BASE + 36, + "The usage of a key is not allowed"}, + {"TPM_WRONG_ENTITYTYPE", TPM_E_BASE + 37, + "The submitted entity type is not allowed"}, + {"TPM_INVALID_POSTINIT", TPM_E_BASE + 38, + "The command was received in the wrong sequence relative to TPM_Init\n\ +and a subsequent TPM_Startup"}, + {"TPM_INAPPROPRIATE_SIG", TPM_E_BASE + 39, + "Signed data cannot include additional DER information"}, + {"TPM_BAD_KEY_PROPERTY", TPM_E_BASE + 40, + "The key properties in TPM_KEY_PARMs are not supported by this TPM"}, + {"TPM_BAD_MIGRATION", TPM_E_BASE + 41, + "The migration properties of this key are incorrect"}, + {"TPM_BAD_SCHEME", TPM_E_BASE + 42, + "The signature or encryption scheme for this key is incorrect or not\n\ +permitted in this situation"}, + {"TPM_BAD_DATASIZE", TPM_E_BASE + 43, + "The size of the data (or blob) parameter is bad or inconsistent\n\ +with the referenced key"}, + {"TPM_BAD_MODE", TPM_E_BASE + 44, + "A mode parameter is bad, such as capArea or subCapArea for\n\ TPM_GetCapability, physicalPresence parameter for TPM_PhysicalPresence,\n\ -or migrationType for, TPM_CreateMigrationBlob" }, -{ "TPM_BAD_PRESENCE", TPM_E_BASE + 45, -"Either the physicalPresence or physicalPresenceLock bits\n\ -have the wrong value" }, -{ "TPM_BAD_VERSION", TPM_E_BASE + 46, -"The TPM cannot perform this version of the capability" }, -{ "TPM_NO_WRAP_TRANSPORT", TPM_E_BASE + 47, -"The TPM does not allow for wrapped transport sessions" }, -{ "TPM_AUDITFAIL_UNSUCCESSFUL", TPM_E_BASE + 48, -"TPM audit construction failed and the underlying command\n\ -was returning a failure code also" }, -{ "TPM_AUDITFAIL_SUCCESSFUL", TPM_E_BASE + 49, -"TPM audit construction failed and the underlying command\n\ -was returning success" }, -{ "TPM_NOTRESETABLE", TPM_E_BASE + 50, -"Attempt to reset a PCR register that does not have the resettable attribute" }, -{ "TPM_NOTLOCAL", TPM_E_BASE + 51, -"Attempt to reset a PCR register that requires locality\n\ -and locality modifier not part of command transport" }, -{ "TPM_BAD_TYPE", TPM_E_BASE + 52, -"Make identity blob not properly typed" }, -{ "TPM_INVALID_RESOURCE", TPM_E_BASE + 53, -"When saving context identified resource type does not match actual resource" }, -{ "TPM_NOTFIPS", TPM_E_BASE + 54, -"The TPM is attempting to execute a command only available when in FIPS mode" }, -{ "TPM_INVALID_FAMILY", TPM_E_BASE + 55, -"The command is attempting to use an invalid family ID" }, -{ "TPM_NO_NV_PERMISSION", TPM_E_BASE + 56, -"The permission to manipulate the NV storage is not available" }, -{ "TPM_REQUIRES_SIGN", TPM_E_BASE + 57, -"The operation requires a signed command" }, -{ "TPM_KEY_NOTSUPPORTED", TPM_E_BASE + 58, -"Wrong operation to load an NV key" }, -{ "TPM_AUTH_CONFLICT", TPM_E_BASE + 59, -"NV_LoadKey blob requires both owner and blob authorization" }, -{ "TPM_AREA_LOCKED", TPM_E_BASE + 60, -"The NV area is locked and not writable" }, -{ "TPM_BAD_LOCALITY", TPM_E_BASE + 61, -"The locality is incorrect for the attempted operation" }, -{ "TPM_READ_ONLY", TPM_E_BASE + 62, -"The NV area is read only and can't be written to" }, -{ "TPM_PER_NOWRITE", TPM_E_BASE + 63, -"There is no protection on the write to the NV area" }, -{ "TPM_FAMILYCOUNT", TPM_E_BASE + 64, -"The family count value does not match" }, -{ "TPM_WRITE_LOCKED", TPM_E_BASE + 65, -"The NV area has already been written to" }, -{ "TPM_BAD_ATTRIBUTES", TPM_E_BASE + 66, -"The NV area attributes conflict" }, -{ "TPM_INVALID_STRUCTURE", TPM_E_BASE + 67, -"The structure tag and version are invalid or inconsistent" }, -{ "TPM_KEY_OWNER_CONTROL", TPM_E_BASE + 68, -"The key is under control of the TPM Owner and can only be evicted\n\ -by the TPM Owner" }, -{ "TPM_BAD_COUNTER", TPM_E_BASE + 69, -"The counter handle is incorrect" }, -{ "TPM_NOT_FULLWRITE", TPM_E_BASE + 70, -"The write is not a complete write of the area" }, -{ "TPM_CONTEXT_GAP", TPM_E_BASE + 71, -"The gap between saved context counts is too large" }, -{ "TPM_MAXNVWRITES", TPM_E_BASE + 72, -"The maximum number of NV writes without an owner has been exceeded" }, -{ "TPM_NOOPERATOR", TPM_E_BASE + 73, -"No operator AuthData value is set" }, -{ "TPM_RESOURCEMISSING", TPM_E_BASE + 74, -"The resource pointed to by context is not loaded" }, -{ "TPM_DELEGATE_LOCK", TPM_E_BASE + 75, -"The delegate administration is locked" }, -{ "TPM_DELEGATE_FAMILY", TPM_E_BASE + 76, -"Attempt to manage a family other then the delegated family" }, -{ "TPM_DELEGATE_ADMIN", TPM_E_BASE + 77, -"Delegation table management not enabled" }, -{ "TPM_TRANSPORT_NOTEXCLUSIVE", TPM_E_BASE + 78, -"There was a command executed outside of an exclusive transport session" }, -{ "TPM_OWNER_CONTROL", TPM_E_BASE + 79, -"Attempt to context save a owner evict controlled key" }, -{ "TPM_DAA_RESOURCES", TPM_E_BASE + 80, -"The DAA command has no resources available to execute the command" }, -{ "TPM_DAA_INPUT_DATA0", TPM_E_BASE + 81, -"The consistency check on DAA parameter inputData0 has failed" }, -{ "TPM_DAA_INPUT_DATA1", TPM_E_BASE + 82, -"The consistency check on DAA parameter inputData1 has failed" }, -{ "TPM_DAA_ISSUER_SETTINGS", TPM_E_BASE + 83, -"The consistency check on DAA_issuerSettings has failed" }, -{ "TPM_DAA_TPM_SETTINGS", TPM_E_BASE + 84, -"The consistency check on DAA_tpmSpecific has failed" }, -{ "TPM_DAA_STAGE", TPM_E_BASE + 85, -"The atomic process indicated by the submitted DAA command is not\n\ -the expected process" }, -{ "TPM_DAA_ISSUER_VALIDITY", TPM_E_BASE + 86, -"The issuer's validity check has detected an inconsistency" }, -{ "TPM_DAA_WRONG_W", TPM_E_BASE + 87, -"The consistency check on w has failed" }, -{ "TPM_BAD_HANDLE", TPM_E_BASE + 88, -"The handle is incorrect" }, -{ "TPM_BAD_DELEGATE", TPM_E_BASE + 89, -"Delegation is not correct" }, -{ "TPM_BADCONTEXT", TPM_E_BASE + 90, -"The context blob is invalid" }, -{ "TPM_TOOMANYCONTEXTS", TPM_E_BASE + 91, -"Too many contexts held by the TPM" }, -{ "TPM_MA_TICKET_SIGNATURE", TPM_E_BASE + 92, -"Migration authority signature validation failure" }, -{ "TPM_MA_DESTINATION", TPM_E_BASE + 93, -"Migration destination not authenticated" }, -{ "TPM_MA_SOURCE", TPM_E_BASE + 94, -"Migration source incorrect" }, -{ "TPM_MA_AUTHORITY", TPM_E_BASE + 95, -"Incorrect migration authority" }, -{ "TPM_PERMANENTEK", TPM_E_BASE + 97, -"Attempt to revoke the EK and the EK is not revocable" }, -{ "TPM_BAD_SIGNATURE", TPM_E_BASE + 98, -"Bad signature of CMK ticket" }, -{ "TPM_NOCONTEXTSPACE", TPM_E_BASE + 99, -"There is no room in the context list for additional contexts" }, -{ "TPM_RETRY", TPM_E_BASE + TPM_E_NON_FATAL, -"The TPM is too busy to respond to the command immediately, but\n\ +or migrationType for, TPM_CreateMigrationBlob"}, + {"TPM_BAD_PRESENCE", TPM_E_BASE + 45, + "Either the physicalPresence or physicalPresenceLock bits\n\ +have the wrong value"}, + {"TPM_BAD_VERSION", TPM_E_BASE + 46, + "The TPM cannot perform this version of the capability"}, + {"TPM_NO_WRAP_TRANSPORT", TPM_E_BASE + 47, + "The TPM does not allow for wrapped transport sessions"}, + {"TPM_AUDITFAIL_UNSUCCESSFUL", TPM_E_BASE + 48, + "TPM audit construction failed and the underlying command\n\ +was returning a failure code also"}, + {"TPM_AUDITFAIL_SUCCESSFUL", TPM_E_BASE + 49, + "TPM audit construction failed and the underlying command\n\ +was returning success"}, + {"TPM_NOTRESETABLE", TPM_E_BASE + 50, + "Attempt to reset a PCR register that does not have the resettable attribute"}, + {"TPM_NOTLOCAL", TPM_E_BASE + 51, + "Attempt to reset a PCR register that requires locality\n\ +and locality modifier not part of command transport"}, + {"TPM_BAD_TYPE", TPM_E_BASE + 52, + "Make identity blob not properly typed"}, + {"TPM_INVALID_RESOURCE", TPM_E_BASE + 53, + "When saving context identified resource type does not match actual resource"}, + {"TPM_NOTFIPS", TPM_E_BASE + 54, + "The TPM is attempting to execute a command only available when in FIPS mode"}, + {"TPM_INVALID_FAMILY", TPM_E_BASE + 55, + "The command is attempting to use an invalid family ID"}, + {"TPM_NO_NV_PERMISSION", TPM_E_BASE + 56, + "The permission to manipulate the NV storage is not available"}, + {"TPM_REQUIRES_SIGN", TPM_E_BASE + 57, + "The operation requires a signed command"}, + {"TPM_KEY_NOTSUPPORTED", TPM_E_BASE + 58, + "Wrong operation to load an NV key"}, + {"TPM_AUTH_CONFLICT", TPM_E_BASE + 59, + "NV_LoadKey blob requires both owner and blob authorization"}, + {"TPM_AREA_LOCKED", TPM_E_BASE + 60, + "The NV area is locked and not writable"}, + {"TPM_BAD_LOCALITY", TPM_E_BASE + 61, + "The locality is incorrect for the attempted operation"}, + {"TPM_READ_ONLY", TPM_E_BASE + 62, + "The NV area is read only and can't be written to"}, + {"TPM_PER_NOWRITE", TPM_E_BASE + 63, + "There is no protection on the write to the NV area"}, + {"TPM_FAMILYCOUNT", TPM_E_BASE + 64, + "The family count value does not match"}, + {"TPM_WRITE_LOCKED", TPM_E_BASE + 65, + "The NV area has already been written to"}, + {"TPM_BAD_ATTRIBUTES", TPM_E_BASE + 66, + "The NV area attributes conflict"}, + {"TPM_INVALID_STRUCTURE", TPM_E_BASE + 67, + "The structure tag and version are invalid or inconsistent"}, + {"TPM_KEY_OWNER_CONTROL", TPM_E_BASE + 68, + "The key is under control of the TPM Owner and can only be evicted\n\ +by the TPM Owner"}, + {"TPM_BAD_COUNTER", TPM_E_BASE + 69, + "The counter handle is incorrect"}, + {"TPM_NOT_FULLWRITE", TPM_E_BASE + 70, + "The write is not a complete write of the area"}, + {"TPM_CONTEXT_GAP", TPM_E_BASE + 71, + "The gap between saved context counts is too large"}, + {"TPM_MAXNVWRITES", TPM_E_BASE + 72, + "The maximum number of NV writes without an owner has been exceeded"}, + {"TPM_NOOPERATOR", TPM_E_BASE + 73, + "No operator AuthData value is set"}, + {"TPM_RESOURCEMISSING", TPM_E_BASE + 74, + "The resource pointed to by context is not loaded"}, + {"TPM_DELEGATE_LOCK", TPM_E_BASE + 75, + "The delegate administration is locked"}, + {"TPM_DELEGATE_FAMILY", TPM_E_BASE + 76, + "Attempt to manage a family other then the delegated family"}, + {"TPM_DELEGATE_ADMIN", TPM_E_BASE + 77, + "Delegation table management not enabled"}, + {"TPM_TRANSPORT_NOTEXCLUSIVE", TPM_E_BASE + 78, + "There was a command executed outside of an exclusive transport session"}, + {"TPM_OWNER_CONTROL", TPM_E_BASE + 79, + "Attempt to context save a owner evict controlled key"}, + {"TPM_DAA_RESOURCES", TPM_E_BASE + 80, + "The DAA command has no resources available to execute the command"}, + {"TPM_DAA_INPUT_DATA0", TPM_E_BASE + 81, + "The consistency check on DAA parameter inputData0 has failed"}, + {"TPM_DAA_INPUT_DATA1", TPM_E_BASE + 82, + "The consistency check on DAA parameter inputData1 has failed"}, + {"TPM_DAA_ISSUER_SETTINGS", TPM_E_BASE + 83, + "The consistency check on DAA_issuerSettings has failed"}, + {"TPM_DAA_TPM_SETTINGS", TPM_E_BASE + 84, + "The consistency check on DAA_tpmSpecific has failed"}, + {"TPM_DAA_STAGE", TPM_E_BASE + 85, + "The atomic process indicated by the submitted DAA command is not\n\ +the expected process"}, + {"TPM_DAA_ISSUER_VALIDITY", TPM_E_BASE + 86, + "The issuer's validity check has detected an inconsistency"}, + {"TPM_DAA_WRONG_W", TPM_E_BASE + 87, + "The consistency check on w has failed"}, + {"TPM_BAD_HANDLE", TPM_E_BASE + 88, + "The handle is incorrect"}, + {"TPM_BAD_DELEGATE", TPM_E_BASE + 89, + "Delegation is not correct"}, + {"TPM_BADCONTEXT", TPM_E_BASE + 90, + "The context blob is invalid"}, + {"TPM_TOOMANYCONTEXTS", TPM_E_BASE + 91, + "Too many contexts held by the TPM"}, + {"TPM_MA_TICKET_SIGNATURE", TPM_E_BASE + 92, + "Migration authority signature validation failure"}, + {"TPM_MA_DESTINATION", TPM_E_BASE + 93, + "Migration destination not authenticated"}, + {"TPM_MA_SOURCE", TPM_E_BASE + 94, + "Migration source incorrect"}, + {"TPM_MA_AUTHORITY", TPM_E_BASE + 95, + "Incorrect migration authority"}, + {"TPM_PERMANENTEK", TPM_E_BASE + 97, + "Attempt to revoke the EK and the EK is not revocable"}, + {"TPM_BAD_SIGNATURE", TPM_E_BASE + 98, + "Bad signature of CMK ticket"}, + {"TPM_NOCONTEXTSPACE", TPM_E_BASE + 99, + "There is no room in the context list for additional contexts"}, + {"TPM_RETRY", TPM_E_BASE + TPM_E_NON_FATAL, + "The TPM is too busy to respond to the command immediately, but\n\ the command could be resubmitted at a later time. The TPM MAY\n\ -return TPM_RETRY for any command at any time" }, -{ "TPM_NEEDS_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 1, -"TPM_ContinueSelfTest has not been run" }, -{ "TPM_DOING_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 2, -"The TPM is currently executing the actions of TPM_ContinueSelfTest\n\ -because the ordinal required resources that have not been tested" }, -{ "TPM_DEFEND_LOCK_RUNNING", TPM_E_BASE + TPM_E_NON_FATAL + 3, -"The TPM is defending against dictionary attacks and is in some\n\ -time-out period" }, - }; +return TPM_RETRY for any command at any time"}, + {"TPM_NEEDS_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 1, + "TPM_ContinueSelfTest has not been run"}, + {"TPM_DOING_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 2, + "The TPM is currently executing the actions of TPM_ContinueSelfTest\n\ +because the ordinal required resources that have not been tested"}, + {"TPM_DEFEND_LOCK_RUNNING", TPM_E_BASE + TPM_E_NON_FATAL + 3, + "The TPM is defending against dictionary attacks and is in some\n\ +time-out period"}, +}; -#endif /* TPM_ERROR_MESSAGES_H */ +#endif /* TPM_ERROR_MESSAGES_H */ diff --git a/src/lib/trace.c b/src/lib/trace.c index 8f52331..b118817 100644 --- a/src/lib/trace.c +++ b/src/lib/trace.c @@ -19,7 +19,7 @@ int volatile trace_dis = 0; -void __cyg_profile_func_enter( void *func, void *callsite) +void __cyg_profile_func_enter(void *func, void *callsite) { if (trace_dis) @@ -30,6 +30,6 @@ void __cyg_profile_func_enter( void *func, void *callsite) ENABLE_TRACE } -void __cyg_profile_func_exit( void *func, void *callsite ) +void __cyg_profile_func_exit(void *func, void *callsite) { }

1 0

Patch set updated for coreboot: lint/checkpatch.pl: Pull in coreboot fixes
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16348 -gerrit commit 2c275e635bd00d160ef3c614d7daba061676fa46 Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 29 10:39:30 2016 -0600 lint/checkpatch.pl: Pull in coreboot fixes This pulls in two fixes that were added to coreboot's checkpatch.pl script: - commit 82ef8ada (src/commonlib/lz4_wrapper: Correct inline asm for unaligned 64-bit copy): modify checkpatch.pl to ignore spaces before opening brackets when used in inline assembly. - commit ebef00fa (lint/checkpatch.pl: escape \{ in perl regex to fix warnings): Unescaped left brace in regex is deprecated, passed through in regex; Change-Id: Ia2c712c5b1bb5f67953a9098b5a076e31e3bd8d3 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/checkpatch.pl | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 6750595..eb03bc7 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -3836,11 +3836,12 @@ sub process { # 1. with a type on the left -- int [] a; # 2. at the beginning of a line for slice initialisers -- [0...10] = 5, # 3. inside a curly brace -- = { [0...10] = 5 } +# 4. in an extended asm instruction -- : [r0]"r"(r0) while ($line =~ /(.*?\s)\[/g) { my ($where, $prefix) = ($-[1], $1); if ($prefix !~ /$Type\s+$/ && ($where != 0 || $prefix !~ /^.\s+$/) && - $prefix !~ /[{,]\s+$/) { + $prefix !~ /[{,:]\s+$/) { if (ERROR("BRACKET_SPACE", "space prohibited before open square bracket '['\n" . $herecurr) && $fix) { @@ -4709,7 +4710,7 @@ sub process { $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) $dstat !~ /^for\s*$Constant$/ && # for (...) $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() - $dstat !~ /^do\s*{/ && # do {... + $dstat !~ /^do\s*\{/ && # do {... $dstat !~ /^\(\{/ && # ({... $ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/) {

1 0

Patch set updated for coreboot: Update .checkpatch.conf
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16010 -gerrit commit c9aa1efe8ca1f389ed307f66adad889773867304 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Aug 1 12:21:30 2016 -0700 Update .checkpatch.conf - Don't require a description of every config statement in the Kconfig changes - Don't complain about externs in .c files - Don't complain about the use of the volatile keyword. The kernel may not want it, but we definitely need it. - Disable checks that seem to be broken. Change-Id: Ic419b81cd36852a91e887e610d4a04984ab5fbd7 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Martin Roth <martinroth(a)google.com> --- .checkpatch.conf | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/.checkpatch.conf b/.checkpatch.conf index f7b9b32..f194ced 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -1,9 +1,6 @@ # Not Linux, so don't expect a Linux tree. --no-tree -# Require every Kconfig symbol to have at least two lines in their description. ---min-conf-desc-length=2 - # Ignore aspects we don't follow here. --ignore C99_COMMENTS --ignore GLOBAL_INITIALISERS @@ -15,3 +12,15 @@ --ignore PREFER_PRINTF --ignore SPLIT_STRING --ignore BLOCK_COMMENT_STYLE +--ignore AVOID_EXTERNS +--ignore VOLATILE +--ignore CONFIG_DESCRIPTION + +# FILE_PATH_CHANGES seems to not be working correctly. It will +# choke on added / deleted files even if the MAINTAINERS file +# is touched. +--ignore FILE_PATH_CHANGES + +# This one has a linux path hard coded, so it would choke on +# some commits unnecessarily. +--ignore EXECUTE_PERMISSIONS

1 0

New patch to review for coreboot: mainboard/intel/kunimitsu:[WIP] Add FSP 2.0 support in ramstage
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16356 -gerrit commit 4a5061aefedb0bff4b440447875066a195268523 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Aug 30 20:50:03 2016 +0530 mainboard/intel/kunimitsu:[WIP] Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Change-Id: I8a9ef156a4dea89b80757f2a186d7181526b805a --- src/mainboard/intel/kunimitsu/devicetree.cb | 3 +++ src/mainboard/intel/kunimitsu/ramstage.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index a5789b0..ee3dcf6 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -193,6 +193,9 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" + # Enable/Disable VMX + register "VmxEnable" = "0" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 44fb9cd..c67bf79 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -13,11 +13,13 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <soc/ramstage.h> #include "gpio.h" void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + printk(BIOS_DEBUG, "Configure Gpio...\n"); /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));

1 0

New patch to review for coreboot: soc/intel/skylake:[WIP] Add FSP 2.0 support in ramstage
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16355 -gerrit commit e4f847f8b90e695b22a2fd0a443b15adc50885fe Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Aug 30 20:47:13 2016 +0530 soc/intel/skylake:[WIP] Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Implement lb_framebuffer for pre OS screens. Change-Id: Ia3c1dd741fb657ec14e305a1ef7cebc2befff188 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 26 +- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/chip.h | 13 + src/soc/intel/skylake/chip_fsp20.c | 514 ++++++++++++++++++++- src/soc/intel/skylake/igd.c | 6 +- src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 3 +- src/soc/intel/skylake/lb_framebuffer.c | 47 ++ 7 files changed, 602 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index edf5db3..7cb963a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -35,14 +35,13 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE - select PLATFORM_USES_FSP1_1 + select PLATFORM_USES_FSP2_0 select REG_SCRIPT select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select RTC select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET @@ -54,6 +53,25 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC +config PLATFORM_USES_FSP2_0 + select ADD_VBT_DATA_FILE + select SOC_INTEL_COMMON_GFX_OPREGION + +config PLATFORM_USES_FSP1_1 + select GOP_SUPPORT + select DISPLAY_FSP_ENTRY_POINTS + select HAVE_FSP_BIN + +config FSP_FILE + string + depends on PLATFORM_USES_FSP1_1 + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/fsp/FSP.fd" + +config FSP_IMAGE_ID_STRING + string + depends on PLATFORM_USES_FSP1_1 + default "$SKLFSP$" + config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC @@ -213,4 +231,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n +config VBT_FILE + string "VBT binary path and filename" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 80562e4..15b7634 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -58,6 +58,7 @@ ramstage-y += flash_controller.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += igd.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += lb_framebuffer.c ramstage-y += lpc.c ramstage-y += me_status.c ramstage-y += memmap.c diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 62e28e6..85f6054 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -273,6 +273,19 @@ struct soc_intel_skylake_config { u16 PchConfigSubSystemVendorId; /* Subsystem ID of the PCH devices*/ u16 PchConfigSubSystemId; + + /* + * Determine if WLAN wake from Sx, corresponds to the + * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanEnable; + + /* + * Determine if WLAN wake from DeepSx, corresponds to + * the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanDeepSxEnable; + /* * Corresponds to the "WOL Enable Override" bit in the General PM * Configuration B (GEN_PMCON_B) register diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 215530c..7a403e4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify @@ -18,13 +17,524 @@ #include <bootstate.h> #include <device/pci.h> #include <fsp/api.h> +#include <arch/acpi.h> +#include <chip.h> +#include <bootstate.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <soc/acpi.h> +#include <soc/interrupt.h> +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <string.h> + +static const struct SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { + /* + * cAVS(Audio, Voice, Speach), INTA is default, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + /* + * SMBus Controller, no default value, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + /* TraceHub, INTA is default, RO register */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ), + /* + * SerialIo: UART #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[7] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), + /* + * SerialIo: UART #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[8] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), + /* + * SerialIo: SPI #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[10] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), + /* + * SerialIo: SPI #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[11] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + /* SCS: eMMC (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + /* SCS: SDIO (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + /* SCS: SDCard (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + /* PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), + /* PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), + /* PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), + /* PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + /* + * PCI Express Port 1, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + /* + * PCI Express Port 2, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + /* + * PCI Express Port 3, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + /* + * PCI Express Port 4, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + /* + * PCI Express Port 5, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + /* + * PCI Express Port 6, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + /* + * PCI Express Port 7, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + /* + * PCI Express Port 8, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + /* + * SerialIo UART Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[9] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + /* + * SerialIo UART Controller #5, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[6] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + /* + * SerialIo UART Controller #4, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[5] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + /* + * SATA Controller, INTA is default, + * programmed in PciCfgSpace + 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, + PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + /* CSME: HECI #1 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME), int_A, HECI_1_IRQ), + /* CSME: HECI #2 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_2), int_B, HECI_2_IRQ), + /* CSME: IDE-Redirection (IDE-R) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_IDER), int_C, IDER_IRQ), + /* CSME: Keyboard and Text (KT) Redirection */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_KT), int_D, KT_IRQ), + /* CSME: HECI #3 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_3), int_A, HECI_3_IRQ), + /* + * SerialIo I2C Controller #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[1] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + /* + * SerialIo I2C Controller #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[2] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + /* + * SerialIo I2C Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[3] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + /* + * SerialIo I2C Controller #3, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[4] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + /* + * USB 3.0 xHCI Controller, no default value, + * programmed in PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + /* USB Device Controller (OTG) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + /* Thermal Subsystem */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THRMAL_IRQ), + /* Camera IO Host Controller */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + /* Integrated Sensor Hub */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, + PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) +}; + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +const char *soc_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_IGD: return "GFX0"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_USBOTG: return "XDCI"; + case PCH_DEVFN_THERMAL: return "THRM"; + case PCH_DEVFN_CIO: return "ICIO"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_ME: return "MEI1"; + case PCH_DEVFN_ME_2: return "MEI2"; + case PCH_DEVFN_ME_IDER: return "MEID"; + case PCH_DEVFN_ME_KT: return "MEKT"; + case PCH_DEVFN_ME_3: return "MEI3"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_EMMC: return "EMMC"; + case PCH_DEVFN_SDIO: return "SDIO"; + case PCH_DEVFN_SDCARD: return "SDXC"; + case PCH_DEVFN_LPC: return "LPCB"; + case PCH_DEVFN_P2SB: return "P2SB"; + case PCH_DEVFN_PMC: return "PMC_"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_SPI: return "FSPI"; + case PCH_DEVFN_GBE: return "IGBE"; + case PCH_DEVFN_TRACEHUB:return "THUB"; + } + + return NULL; +} +#endif + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .ops_pci_bus = &pci_bus_default_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = &soc_init_cpus, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = generate_cpu_entries, +#endif +}; + +static void soc_enable(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle PCH device enable */ + if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD && + (dev->ops == NULL || dev->ops->enable == NULL)) { + pch_enable_dev(dev); + } + } +} + +struct chip_operations soc_intel_skylake_ops = { + CHIP_NAME("Intel 6th Gen") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, +}; /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd) { + struct FSP_S_CONFIG *params = &supd->FspsConfig; + struct FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; + static struct soc_intel_skylake_config *config; + int i, intdeventry; + uintptr_t *vbt_data = NULL; + u8 irq_config[PCH_MAX_IRQ_CONFIG]; + + int is_s3_wakeup = acpi_is_wakeup_s3(); + + struct device *dev = SA_DEV_ROOT; + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + mainboard_silicon_init_params(params); + + /* Load VBT */ + if (!is_s3_wakeup) { + vbt_data = (uintptr_t *) fsp_load_vbt(); + } + + params->GraphicsConfigPtr = (u32) vbt_data; + + /* Get Device Int Count */ + intdeventry = ARRAY_SIZE(devintconfig); + + /*update irq table */ + memcpy((struct SI_PCH_DEVICE_INTERRUPT_CONFIG *) + (params->DevIntConfigPtr), devintconfig, intdeventry * + sizeof(struct SI_PCH_DEVICE_INTERRUPT_CONFIG)); + + params->NumOfDevIntConfig = intdeventry; + /* PxRC to IRQ programing */ + for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) { + switch (i) { + case PCH_PARC: + case PCH_PCRC: + case PCH_PDRC: + case PCH_PERC: + case PCH_PFRC: + case PCH_PGRC: + case PCH_PHRC: + irq_config[i] = PCH_IRQ11; + break; + case PCH_PBRC: + irq_config[PCH_PBRC] = PCH_IRQ10; + break; + } + } + + memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); + + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = + config->usb2_ports[i].enable; + params->Usb2AfePetxiset[i] = + config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = + config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = + config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = + config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = + config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + for (i = 0; i < ARRAY_SIZE(config->i2c); i++) + params->SerialIoI2cVoltage[i] = config->i2c[i].voltage; + + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(params, i, &config->domain_vr_config[i]); + + /* GPIO IRQ Route The valid values is 14 or 15 */ + if (config->GpioIrqSelect == 0) + params->GpioIrqRoute = GPIO_IRQ14; + else + params->GpioIrqRoute = config->GpioIrqSelect; + + /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23 */ + if (config->SciIrqSelect == 0) + params->SciIrqSelect = SCI_IRQ9; + else + params->SciIrqSelect = config->SciIrqSelect; + /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23 */ + if (config->TcoIrqSelect == 0) + params->TcoIrqSelect = TCO_IRQ9; + else + params->TcoIrqSelect = config->TcoIrqSelect; + /* TCO Irq enable/disable */ + params->TcoIrqEnable = config->TcoIrqEnable; + + params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; + params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; + params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + params->PchPmDeepSxPol = config->PmConfigDeepSxPol; + params->PchLanEnable = config->EnableLan; + + params->SataEnable = config->EnableSata; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + + params->PchHdaEnable = config->EnableAzalia; + params->PchHdaDspEnable = config->DspEnable; + params->PchHdaIoBufferOwnership = config->IoBufferOwnership; + + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(params->PcieRpClkReqSupport)); + memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(params->PcieRpClkReqNumber)); + + params->XdciEnable = config->XdciEnable; + params->SsicPortEnable = config->SsicPortEnable; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, + sizeof(params->SerialIoDevMode)); + params->PchCio2Enable = config->Cio2Enable; + + params->ScsEmmcEnabled = config->ScsEmmcEnabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->ScsSdCardEnabled = config->ScsSdCardEnabled; + + params->PchIshEnable = config->IshEnable; + params->Heci3Enabled = config->Heci3Enabled; + params->LogoPtr = config->LogoPtr; + params->LogoSize = config->LogoSize; + params->Device4Enable = config->Device4Enable; + + params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; + params->PchSubSystemId = config->PchConfigSubSystemId; + params->PchLockDownSpiEiss = config->LockDownConfigSpiEiss; + params->PchLockDownBiosLock = config->LockDownConfigBiosLock; + params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; + params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; + params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; + params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; + params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; + params->PchPmLpcClockRun = config->PmConfigPciClockRun; + params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; + params->PchPmPwrBtnOverridePeriod = + config->PmConfigPwrBtnOverridePeriod; + params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + params->PchSirqEnable = config->SerialIrqConfigSirqEnable; + params->PchSirqMode = config->SerialIrqConfigSirqMode; + + params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit; + params->CpuConfig.Bits.VmxEnable = config->VmxEnable; + params->SendVrMbxCmd = config->SendVrMbxCmd; + + /* Show SPI controller if enabled in devicetree.cb */ + dev = dev_find_slot(0, PCH_DEVFN_SPI); + params->ShowSpiController = dev->enabled; + + params->PchCio2Enable = config->Cio2Enable; + + tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; + tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; + tconfig->PchLockDownBiosInterface = config->LockDownConfigBiosInterface; + params->PchLockDownBiosLock = config->LockDownConfigBiosLock; +} + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + else + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + (device << 16) | vendor); } struct pci_operations soc_pci_ops = { - /* TODO: Add set subsystem id function */ + .set_subsystem = &pci_set_subsystem }; +/* Mainboard GPIO Configuration */ +__attribute__((weak)) void mainboard_silicon_init_params(struct FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index 969f386..09c8b76 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -79,7 +79,8 @@ static void igd_init(struct device *dev) gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); } - if (IS_ENABLED(CONFIG_GOP_SUPPORT)) + if (IS_ENABLED(CONFIG_GOP_SUPPORT) || + IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE)) return; /* IGD needs to be Bus Master */ @@ -153,7 +154,8 @@ static unsigned long write_acpi_igd_opregion(device_t device, igd_opregion_t *opregion; /* If GOP is not used, exit here */ - if (!IS_ENABLED(CONFIG_GOP_SUPPORT)) + if ((!IS_ENABLED(CONFIG_GOP_SUPPORT)) && + (!IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE))) return current; /* If IGD is disabled, exit here */ diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index 3a9d96b..fb6ac46 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -19,7 +19,6 @@ #include <chip.h> #include <device/device.h> - #include <fsp/api.h> #include <fsp/util.h> #include <soc/intel/common/opregion.h> @@ -27,7 +26,7 @@ #define FSP_SIL_UPD struct FSP_S_CONFIG #define FSP_MEM_UPD struct FSP_M_CONFIG -void intel_silicon_init(void); +inline void intel_silicon_init(void) { fsp_silicon_init(); } void mainboard_silicon_init_params(struct FSP_S_CONFIG *params); void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/skylake/lb_framebuffer.c b/src/soc/intel/skylake/lb_framebuffer.c new file mode 100644 index 0000000..b9a3cca --- /dev/null +++ b/src/soc/intel/skylake/lb_framebuffer.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> + +static uintptr_t framebuffer_bar = (uintptr_t)NULL; + +void lb_framebuffer(struct lb_header *header) +{ + enum cb_err ret; + struct lb_framebuffer *framebuffer; + + framebuffer = (void *)lb_new_record(header); + ret = fsp_fill_lb_framebuffer(framebuffer); + if (ret != CB_SUCCESS) { + printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); + return; + } + + if (!framebuffer_bar) { + printk(BIOS_ALERT, "Framebuffer BAR 0x%x \n", + (uint32_t)framebuffer->physical_address); + printk(BIOS_ALERT, "Framebuffer BAR invalid (00:02.0 BAR2)\n"); + return; + } + + /* + * Resource allocator can move the BAR + * around after FSP configures it + */ + framebuffer->physical_address = framebuffer_bar; + printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", + framebuffer->physical_address); +}

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Patch set updated for coreboot: soc/intel/skylake: Use postcar functions for setting up new stack
by Rizwan Qureshi 30 Aug '16

30 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16332 -gerrit commit 25949aa66caa145b60b062d09df151d9cd318c80 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Aug 26 21:16:01 2016 +0530 soc/intel/skylake: Use postcar functions for setting up new stack Setup stack and MTRRs using the postcar funtions provided in postcar_loader.c. Change-Id: Ia5771e70386dbae9fa181e3635021dd187345123 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/romstage/romstage_fsp20.c | 50 +++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 57b2a52..0d827ab 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -24,16 +24,24 @@ #include <console/console.h> #include <device/pci_def.h> #include <fsp/util.h> +#include <fsp/memmap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <timestamp.h> #include <vboot/vboot_common.h> +/* + * Romstage needs some stack for decompressing ramstage images, since the lzma + * lib keeps its state on the stack during romstage. + */ +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + asmlinkage void *car_stage_c_entry(void) { bool s3wake; - void *top_of_stack; + struct postcar_frame pcf; + uintptr_t top_of_ram; struct chipset_power_state *ps; console_init(); @@ -46,8 +54,44 @@ asmlinkage void *car_stage_c_entry(void) s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); - top_of_stack = setup_stack_and_mtrrs(); - return top_of_stack; + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + assert(ALIGN_DOWN(top_of_ram, 1*MiB) == top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, + MTRR_TYPE_WRBACK); + } + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, + CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + return postcar_commit_mtrrs(&pcf); } static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)

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Patch merged into coreboot/master: soc/intel/skylake: Include Kabylake specific IGD Device IDs
by gerrit＠coreboot.org 30 Aug '16

30 Aug '16

the following patch was just integrated into master: commit 99123101815074322a55332c0344100d1e8193cd Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Fri Aug 26 14:48:46 2016 +0530 soc/intel/skylake: Include Kabylake specific IGD Device IDs Add Kabylake specific Graphics IDs in report_platform.c and igd.c. BUG=none BRANCH=none TEST=Built and boot kunimitsu Change-Id: I3b810d0ff51eb51d396b783e282779aefb2dcb8c Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Reviewed-on: https://review.coreboot.org/16329 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16329 for details. -gerrit

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Patch merged into coreboot/master: nyan-blaze: Correct indentation for sdram configs
by gerrit＠coreboot.org 30 Aug '16

30 Aug '16

the following patch was just integrated into master: commit fe349392a4b56524fe137e73803e753a7ae74c00 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Sun Aug 28 17:39:11 2016 +0200 nyan-blaze: Correct indentation for sdram configs This corrects indentation for sdram configs in nyan_blaze. Change-Id: Ia9ad2a37c6e3b79e1260f490db893244c32685b6 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: https://review.coreboot.org/16342 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16342 for details. -gerrit

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coreboot-gerrit August 2016