coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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1551 discussions

Patch set updated for coreboot: nvramcui: remove undeclared variable
by Antonello Dettori 30 Aug '16

30 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16333 -gerrit commit 69f0c61f9a0a165f4541ba1535e73c5fd6c4740e Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Aug 18 10:32:27 2016 +0200 nvramcui: remove undeclared variable Remove an undeclared variable that was accidentally left over, nvramcui is currently unable to compile and operate because of this. Regression introduced in: 904dd303cbe99541025cbea008855f807a5d9f5c (nvramcui: refactor code) Fixes: https://ticket.coreboot.org/issues/70 Change-Id: Ieaba615838d7593546ab5696baf1b8f9828da345 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/nvramcui/nvramcui.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index 991303e..84e5536 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -179,8 +179,8 @@ int main(void) struct cb_cmos_option_table *opttbl = get_system_option_table(); - if (opttbl == NULL && cmos_default == NULL) { - printf("Could not find coreboot option table/cmos.default.\n"); + if (opttbl == NULL) { + printf("Could not find coreboot option table.\n"); halt(); }

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Patch set updated for coreboot: [UNTESTED] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 30 Aug '16

30 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit 2ad79277540545a6ab37995d72c3a578d77f5f13 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [UNTESTED] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN) and 19 (BKLT_CTRL_SEL), were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 5 +++++ src/drivers/lenovo/hybrid_graphics.c | 19 +++++++++++++++++-- src/mainboard/lenovo/t400/Kconfig | 16 ++++++++++++++++ 3 files changed, 38 insertions(+), 2 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..4c62de1 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -39,3 +39,8 @@ config HYBRID_GRAPHICS_GPIO_NUM help Set a default GPIO that sets the panel LVDS signal routing to integrated or discrete GPU. + +config ENABLE_DISCRETE_IS_HIGH + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..1560eb7 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -43,9 +43,18 @@ static void hybrid_graphics_disable_peg(struct device *dev) { struct device *peg_dev; + u8 disable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, disable_lvl); + /* configure BKLT_CTL */ + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, disable_lvl); + /* configure GFX_PWR_EN_GPIO */ + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -62,13 +71,19 @@ static void hybrid_graphics_disable_peg(struct device *dev) static void hybrid_graphics_enable_peg(struct device *dev) { u8 hybrid_graphics_mode; + u8 enable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, enable_lvl); + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, enable_lvl); + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a444bf8..a136dd0 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -56,4 +56,20 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config HYBRID_GRAPHICS_GPIO_NUM + int + default 22 + +config BKLT_CTRL_SEL_GPIO + int + default 19 + +config GFX_PWR_EN_GPIO + int + default 49 + +config ENABLE_DISCRETE_IS_HIGH + bool + default y + endif # BOARD_LENOVO_T400

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Patch set updated for coreboot: [UNTESTED] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 30 Aug '16

30 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit e58ea6f425d3d81ff3eb4fdb222dca3fc82275d1 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [UNTESTED] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN) and 19 (BKLT_CTRL_SEL), were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 5 +++++ src/drivers/lenovo/hybrid_graphics.c | 19 +++++++++++++++++-- src/mainboard/lenovo/t400/Kconfig | 20 ++++++++++++++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..4c62de1 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -39,3 +39,8 @@ config HYBRID_GRAPHICS_GPIO_NUM help Set a default GPIO that sets the panel LVDS signal routing to integrated or discrete GPU. + +config ENABLE_DISCRETE_IS_HIGH + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..1560eb7 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -43,9 +43,18 @@ static void hybrid_graphics_disable_peg(struct device *dev) { struct device *peg_dev; + u8 disable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, disable_lvl); + /* configure BKLT_CTL */ + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, disable_lvl); + /* configure GFX_PWR_EN_GPIO */ + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -62,13 +71,19 @@ static void hybrid_graphics_disable_peg(struct device *dev) static void hybrid_graphics_enable_peg(struct device *dev) { u8 hybrid_graphics_mode; + u8 enable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, enable_lvl); + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, enable_lvl); + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a444bf8..2fbe403 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -56,4 +56,24 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config HYBRID_GRAPHICS_GPIO_NUM + int + default 22 + +config BKLT_CTRL_SEL_GPIO + int + default 19 + +config DGFX_PWRGD_GPIO + int + default 17 + +config GFX_PWR_EN_GPIO + int + default 49 + +config ENABLE_DISCRETE_IS_HIGH + bool + default y + endif # BOARD_LENOVO_T400

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Patch set updated for coreboot: soc/intel/apollolake: Disable Periodic Retraining per-SKU
by Andrey Petrov 30 Aug '16

30 Aug '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16320 -gerrit commit 11ea95cfceb7b7a6e2ee6deac54d3afc0465907c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Aug 25 11:06:08 2016 -0700 soc/intel/apollolake: Disable Periodic Retraining per-SKU Certain LPDDR4 models have some HW issues that can be worked around by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU. BUG=chrome-os-partner:55466 TEST=not tested yet Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/google/reef/romstage.c | 2 ++ src/soc/intel/apollolake/include/soc/meminit.h | 1 + src/soc/intel/apollolake/meminit.c | 2 ++ 3 files changed, 5 insertions(+) diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index e8d8e16..964dee4 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -103,6 +103,7 @@ static const struct lpddr4_sku skus[] = { .ch0_dual_rank = 1, .ch1_dual_rank = 1, .part_num = "MT53B512M32D2NP", + .disable_periodic_retraining = 1, }, /* MT53B256M32D1NP-062 WT:C - both logical channels */ [3] = { @@ -110,6 +111,7 @@ static const struct lpddr4_sku skus[] = { .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "MT53B256M32D1NP", + .disable_periodic_retraining = 1, }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index c115c4a..06d2b58 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -102,6 +102,7 @@ struct lpddr4_sku { int ch0_dual_rank; int ch1_dual_rank; const char *part_num; + bool disable_periodic_retraining; }; struct lpddr4_cfg { diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 03e9ac4..d0e7683 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -254,6 +254,8 @@ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, sku->ch1_dual_rank, lpcfg->swizzle_config); } + + cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining; } void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)

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Patch set updated for coreboot: soc/intel/apollolake: Disable Periodic Retraining per-SKU
by Andrey Petrov 30 Aug '16

30 Aug '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16320 -gerrit commit a1ad2a08e446953893c0e7b9591c27236334077f Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Aug 25 11:06:08 2016 -0700 soc/intel/apollolake: Disable Periodic Retraining per-SKU Certain LPDDR4 models have some HW issues that can be worked around by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU. BUG=chrome-os-partner:55466 TEST=not tested yet Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/google/reef/romstage.c | 2 ++ src/soc/intel/apollolake/include/soc/meminit.h | 1 + src/soc/intel/apollolake/meminit.c | 2 ++ 3 files changed, 5 insertions(+) diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index e8d8e16..964dee4 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -103,6 +103,7 @@ static const struct lpddr4_sku skus[] = { .ch0_dual_rank = 1, .ch1_dual_rank = 1, .part_num = "MT53B512M32D2NP", + .disable_periodic_retraining = 1, }, /* MT53B256M32D1NP-062 WT:C - both logical channels */ [3] = { @@ -110,6 +111,7 @@ static const struct lpddr4_sku skus[] = { .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "MT53B256M32D1NP", + .disable_periodic_retraining = 1, }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index c115c4a..06d2b58 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -102,6 +102,7 @@ struct lpddr4_sku { int ch0_dual_rank; int ch1_dual_rank; const char *part_num; + bool disable_periodic_retraining; }; struct lpddr4_cfg { diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 03e9ac4..d0e7683 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -254,6 +254,8 @@ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, sku->ch1_dual_rank, lpcfg->swizzle_config); } + + cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining; } void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)

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Patch set updated for coreboot: soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3
by Brandon Breitenstein 30 Aug '16

30 Aug '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16352 -gerrit commit 5b927d46d6175611e484fce16e64d9d231d377d5 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Aug 29 16:24:24 2016 -0700 soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3 Update FSP Header files to provide UPD for periodic training disable. This is for the SIC 1.1.3/150_11 FSP release. BUG=chrome-os-partner:54100 BRANCH=none TEST=built coreboot image with new headers for reef Change-Id: I2ba11aa3d2d664c1d34e39c4c8144fb1c4f2149a Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 34 +++++++++++++--------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index bb53497..88d4c42 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -595,28 +595,28 @@ struct FSP_M_CONFIG { **/ uint8_t RecoverDump; -/** Offset 0x013A - Memory Region 0 Buffer Size +/** Offset 0x013A - Memory Region 0 Buffer WrapAround + Memory Region 0 Buffer WrapAround. 0-n0-wrap, 1-warp(Default). +**/ + uint8_t Msc0Wrap; + +/** Offset 0x013B - Memory Region 1 Buffer WrapAround + Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + uint8_t Msc1Wrap; + +/** Offset 0x013C - Memory Region 0 Buffer Size Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ uint32_t Msc0Size; -/** Offset 0x013E - Memory Region 0 Buffer WrapAround - Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - uint8_t Msc0Wrap; - -/** Offset 0x013F - Memory Region 1 Buffer Size +/** Offset 0x0140 - Memory Region 1 Buffer Size Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ uint32_t Msc1Size; -/** Offset 0x0143 - Memory Region 1 Buffer WrapAround - Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - uint8_t Msc1Wrap; - /** Offset 0x0144 - PTI Mode PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. **/ @@ -648,9 +648,15 @@ struct FSP_M_CONFIG { **/ uint8_t SwTraceEn; -/** Offset 0x014A +/** Offset 0x014A - Periodic Retraining Disable + Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t PeriodicRetrainingDisable; + +/** Offset 0x014B **/ - uint8_t ReservedFspmUpd[6]; + uint8_t ReservedFspmUpd[5]; } __attribute__((packed)); /** Fsp M Test Configuration

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Patch set updated for coreboot: [UNTESTED] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 30 Aug '16

30 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit 4801c13515ec004c32e35effe43ed6b8247a02b0 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [UNTESTED] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN), 19 (BKLT_CTRL_SEL), 17 (DGFX_PWRGD) were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 5 +++++ src/drivers/lenovo/hybrid_graphics.c | 24 ++++++++++++++++++++++-- src/mainboard/lenovo/t400/Kconfig | 20 ++++++++++++++++++++ 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..4c62de1 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -39,3 +39,8 @@ config HYBRID_GRAPHICS_GPIO_NUM help Set a default GPIO that sets the panel LVDS signal routing to integrated or discrete GPU. + +config ENABLE_DISCRETE_IS_HIGH + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..f5153f1 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -43,9 +43,21 @@ static void hybrid_graphics_disable_peg(struct device *dev) { struct device *peg_dev; + u8 disable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, disable_lvl); + /* configure BKLT_CTL */ + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, disable_lvl); + /* configure DGFX_PWRGD */ + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, disable_lvl); + /* configure GFX_PWR_EN_GPIO */ + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -62,13 +74,21 @@ static void hybrid_graphics_disable_peg(struct device *dev) static void hybrid_graphics_enable_peg(struct device *dev) { u8 hybrid_graphics_mode; + u8 enable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, enable_lvl); + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, enable_lvl); + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, enable_lvl); + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a444bf8..2fbe403 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -56,4 +56,24 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config HYBRID_GRAPHICS_GPIO_NUM + int + default 22 + +config BKLT_CTRL_SEL_GPIO + int + default 19 + +config DGFX_PWRGD_GPIO + int + default 17 + +config GFX_PWR_EN_GPIO + int + default 49 + +config ENABLE_DISCRETE_IS_HIGH + bool + default y + endif # BOARD_LENOVO_T400

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Patch set updated for coreboot: gru: Add USB 2.0 PHY tuning for Kevin
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16265 -gerrit commit 0725c23619f6cfd44e0820f2039b58f4587fbc0e Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 15 17:58:05 2016 -0700 gru: Add USB 2.0 PHY tuning for Kevin This patch sets some magic number in magic undocumented registers that are rumored to make USB 2.0 signal integrity better on Kevin. I don't see any difference (unfortunately it doesn't solve the problems with long cables on my board), but I guess it doesn't hurt either way. BRANCH=None BUG=chrome-os-partner:56108,chrome-os-partner:54788 TEST=Booted Kevin with USB connected through Servo. Seems to have roughly the same failure rate as before. Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84 Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/370900 Original-Reviewed-by: Guenter Roeck <groeck(a)chromium.org> Original-Reviewed-by: David Schneider <dnschneid(a)chromium.org> --- src/mainboard/google/gru/mainboard.c | 9 +++++++++ src/soc/rockchip/rk3399/include/soc/grf.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 8a6cda2..a2b74ba 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -158,6 +158,15 @@ static void configure_display(void) static void setup_usb(void) { + /* A few magic PHY tuning values that improve eye diagram amplitude + * and make it extra sure we get reliable communication in firmware. */ + /* Set max ODT compensation voltage and current tuning reference. */ + write32(&rk3399_grf->usbphy0_ctrl[3], 0x0fff02e3); + write32(&rk3399_grf->usbphy1_ctrl[3], 0x0fff02e3); + /* Set max pre-emphasis level, only on Kevin PHY0. */ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) + write32(&rk3399_grf->usbphy0_ctrl[12], 0xffff00a7); + setup_usb_otg0(); setup_usb_otg1(); } diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h index d76b827..c1fd690 100644 --- a/src/soc/rockchip/rk3399/include/soc/grf.h +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -73,7 +73,7 @@ struct rk3399_grf_regs { u32 reserved11[3]; u32 usbphy0_ctrl[26]; u32 reserved12[6]; - u32 usbphy1[26]; + u32 usbphy1_ctrl[26]; u32 reserved13[0x72f]; u32 soc_con9; u32 reserved14[0x0a];

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New patch to review for coreboot: rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpu
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16368 -gerrit commit c3883d9706820bf1cceb60a7cf392b3f45a65017 Author: Eric Gao <eric.gao(a)rock-chips.com> Date: Fri Jul 29 12:34:32 2016 +0800 rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpu Before, we calculate the pwm duties for cpu cores and centerlogic by hand, adding pwm_regulator.c to handle this. The default pwm design min/max voltage may be different between revs. With the pwm regulator, this patch changes the little cpu frequency from 600M to 1512M, and raises CPU voltage to 1.2V correspondingly. This also means we decide to drop the ES1 because it may fail to bootup with 1.5G ~ 1.2v. BRANCH=none BUG=chrome-os-partner:54376,chrome-os-partner:54862 TEST=Bootup on kevin board Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9 Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b Original-Signed-off-by: Eric Gao <eric.gao(a)rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364410 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/Makefile.inc | 3 ++ src/mainboard/google/gru/bootblock.c | 17 +++++- src/mainboard/google/gru/pwm_regulator.c | 82 +++++++++++++++++++++++++++++ src/mainboard/google/gru/pwm_regulator.h | 28 ++++++++++ src/mainboard/google/gru/romstage.c | 72 ++----------------------- src/soc/rockchip/rk3399/Makefile.inc | 2 + src/soc/rockchip/rk3399/bootblock.c | 1 - src/soc/rockchip/rk3399/clock.c | 6 +-- src/soc/rockchip/rk3399/include/soc/clock.h | 2 +- 9 files changed, 140 insertions(+), 73 deletions(-) diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index e1ba56a..9e07a6c 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -18,6 +18,8 @@ subdirs-y += sdram_params/ bootblock-y += bootblock.c bootblock-y += chromeos.c bootblock-y += memlayout.ld +bootblock-y += pwm_regulator.c +bootblock-y += boardid.c verstage-y += chromeos.c verstage-y += memlayout.ld @@ -26,6 +28,7 @@ verstage-y += reset.c romstage-y += boardid.c romstage-y += chromeos.c romstage-y += memlayout.ld +romstage-y += pwm_regulator.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index e80f4a3..ff91e1a 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -16,13 +16,17 @@ #include <arch/io.h> #include <bootblock_common.h> +#include <console/console.h> +#include <delay.h> #include <soc/grf.h> #include <gpio.h> +#include <soc/clock.h> #include <soc/i2c.h> +#include <soc/pwm.h> #include <soc/spi.h> -#include <console/console.h> #include "board.h" +#include "pwm_regulator.h" void bootblock_mainboard_early_init(void) { @@ -58,8 +62,19 @@ void bootblock_mainboard_early_init(void) #endif } +static void speed_up_boot_cpu(void) +{ + pwm_regulator_configure(PWM_REGULATOR_LIT, 1200); + + udelay(200); + + rkclk_configure_cpu(APLL_1512_MHZ, false); +} + void bootblock_mainboard_init(void) { + speed_up_boot_cpu(); + /* Set pinmux and configure spi flashrom. */ write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX); write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c new file mode 100644 index 0000000..f382b2b --- /dev/null +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <assert.h> +#include <boardid.h> +#include <console/console.h> +#include <soc/grf.h> +#include <soc/pwm.h> + +#include "pwm_regulator.h" + +/* + * Apparently a period of 3333 is determined by EEs to be ideal for our + * board design / resistors / capacitors / regulators but due to + * clock dividers we actually get 3337. + */ +#define PWM_PERIOD 3337 +#define PWM_DESIGN_VOLTAGE_MIN 8000 +#define PWM_DESIGN_VOLTAGE_MAX 15000 + +/* The min & max design voltages are different after kevin-r6 */ +int kevin_voltage_min_max_r6[][2] = { + [PWM_REGULATOR_GPU] = {7910, 12139}, + [PWM_REGULATOR_BIG] = {7986, 13057}, + [PWM_REGULATOR_LIT] = {7997, 13002}, + [PWM_REGULATOR_CENTERLOG] = {7996, 10507} +}; + +void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) +{ + int duty_ns, voltage_max, voltage_min; + int voltage = millivolt * 10; /* for higer calculation accuracy */ + + switch (pwm) { + case PWM_REGULATOR_GPU: + write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); + break; + case PWM_REGULATOR_BIG: + write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); + break; + case PWM_REGULATOR_LIT: + write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); + break; + case PWM_REGULATOR_CENTERLOG: + write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); + break; + } + + voltage_min = PWM_DESIGN_VOLTAGE_MIN; + voltage_max = PWM_DESIGN_VOLTAGE_MAX; + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6) { + voltage_min = kevin_voltage_min_max_r6[pwm][0]; + voltage_max = kevin_voltage_min_max_r6[pwm][1]; + } + + assert(voltage <= voltage_max && voltage >= voltage_min); + + /* + * Intentionally round down (higher volt) to be safe. + * eg, for the default min & max design voltage: + * period = 3337, volt = 1.1: 1906 + * period = 3337, volt = 1.0: 2383 + * period = 3337, volt = 0.9: 2860 + */ + duty_ns = PWM_PERIOD * (voltage_max - voltage) + / (voltage_max - voltage_min); + + pwm_init(pwm, PWM_PERIOD, duty_ns); +} diff --git a/src/mainboard/google/gru/pwm_regulator.h b/src/mainboard/google/gru/pwm_regulator.h new file mode 100644 index 0000000..6ef0c59 --- /dev/null +++ b/src/mainboard/google/gru/pwm_regulator.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_PWM_REGULATOR_H +#define __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_PWM_REGULATOR_H + +enum pwm_regulator { + PWM_REGULATOR_GPU = 0, + PWM_REGULATOR_BIG, + PWM_REGULATOR_LIT, + PWM_REGULATOR_CENTERLOG +}; + +void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt); + +#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_PWM_REGULATOR_H */ diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index ccf42b9..1e2507a 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -17,90 +17,28 @@ #include <arch/cache.h> #include <arch/cpu.h> #include <arch/exception.h> -#include <arch/io.h> #include <arch/mmu.h> -#include <boardid.h> #include <cbfs.h> #include <console/console.h> -#include <delay.h> #include <program_loading.h> #include <romstage_handoff.h> #include <soc/addressmap.h> -#include <soc/grf.h> #include <soc/mmu_operations.h> -#include <soc/pwm.h> #include <soc/tsadc.h> #include <soc/sdram.h> #include <symbols.h> #include <soc/usb.h> +#include "pwm_regulator.h" + static const uint64_t dram_size = (uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS); static void init_dvs_outputs(void) { - int duty_ns; - uint32_t i; - uint32_t id; - - write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); /* GPU */ - write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); /* Big */ - write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); /* Little */ - write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); /* Centerlog */ - - /* - * Set up voltages for all DVS rails. - * - * LITTLE CPU: At the speed we're running at right now and on the - * early silicon, .9V is sane. If/when we run faster, let's bump this. - * - * CENTER LOGIC: There are some claims that this should simply always - * be .9 V. There are other claims that say that we need to adjust this - * dynamically depending on the memory frequency. Until this is sorted - * out, it appears that .9 V works for the 800 MHz. - * - * BIG CPU / GPU: These aren't used in coreboot. Init to .9V which is - * supposed to be a good default. - * - * Details: - * design_min = 0.8 - * design_max = 1.5 - * period = 3337 # 300 kHz - * volt = 1.1 - * # Intentionally round down (higher volt) to be safe. - * int((period / (design_max - design_min)) * (design_max - volt)) - * - * Apparently a period of 3333 is determined by EEs to be ideal for our - * board design / resistors / capacitors / regulators but due to - * clock dividers we actually get 3337. Solving, we get: - * period = 3337, volt = 1.1: 1906 - * period = 3337, volt = 1.0: 2383 - * period = 3337, volt = 0.9: 2860 - */ - duty_ns = 2860; /* 0.9v */ - - /* TODO: Clean all this up, implement proper pwm_regulator driver. */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) { - id = board_id(); - if (id <= 2) - duty_ns = 1906; /* 1.1v */ - else if (id == 3) - duty_ns = 2621; /* 0.95v */ - else if (id >= 6) { - /* GPU: 3337 * (12043 - 9000) / (12043 - 7984) = 2501 */ - pwm_init(0, 3337, 2501); - /* BIG: 3337 * (12837 - 9000) / (12837 - 7985) = 2638 */ - pwm_init(1, 3337, 2638); - /* LIT: 3337 * (12807 - 9000) / (12807 - 8009) = 2647 */ - pwm_init(2, 3337, 2647); - /* CTR: 3337 * (10507 - 9500) / (10507 - 7996) = 1338 */ - pwm_init(3, 3337, 1338); - return; - } - } - - for (i = 0; i < 4; i++) - pwm_init(i, 3337, duty_ns); + pwm_regulator_configure(PWM_REGULATOR_GPU, 900); + pwm_regulator_configure(PWM_REGULATOR_BIG, 900); + pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 950); } static void prepare_usb(void) diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 6e75278..ceec7bc 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -23,10 +23,12 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c endif bootblock-y += ../common/gpio.c +bootblock-y += ../common/pwm.c bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += gpio.c bootblock-y += mmu_operations.c +bootblock-y += saradc.c bootblock-y += timer.c verstage-y += ../common/cbmem.c diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index 4f85e94..7b80a75 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -22,7 +22,6 @@ void bootblock_soc_init(void) { rkclk_init(); - rkclk_configure_cpu(APLL_600_MHZ, false); /* all ddr range non-secure */ write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index ed9afda..428a210 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -47,11 +47,11 @@ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); -static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); -static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_1512_cfg = PLL_DIVISORS(1512*MHz, 1, 1, 1); +static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 3, 1); static const struct pll_div *apll_cfgs[] = { - [APLL_1600_MHZ] = &apll_1600_cfg, + [APLL_1512_MHZ] = &apll_1512_cfg, [APLL_600_MHZ] = &apll_600_cfg, }; diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 19e315b..de86ed4 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -97,7 +97,7 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PWM_CLOCK_HZ PMU_PCLK_HZ enum apll_frequencies { - APLL_1600_MHZ, + APLL_1512_MHZ, APLL_600_MHZ, };

1 0

New patch to review for coreboot: rockchip/rk3399: Move romstage.c to mainboard/gru
by Martin Roth 30 Aug '16

30 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16367 -gerrit commit 071caf2e3aa2ef18900d5931e2921c87dcb003d7 Author: Shunqian Zheng <zhengsq(a)rock-chips.com> Date: Thu Aug 25 02:28:19 2016 +0800 rockchip/rk3399: Move romstage.c to mainboard/gru The romstage.c is more board related than soc specific, like setting the pwm regulators, so moving it to mainboard/gru. BRANCH=none BUG=chrome-os-partner:54819 TEST=Bootup on kevin board Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474 Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443 Original-Signed-off-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/375398 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/Makefile.inc | 1 + src/mainboard/google/gru/romstage.c | 133 ++++++++++++++++++++++++++++++++++ src/soc/rockchip/rk3399/Makefile.inc | 1 - src/soc/rockchip/rk3399/romstage.c | 133 ---------------------------------- 4 files changed, 134 insertions(+), 134 deletions(-) diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index 07b27a7..e1ba56a 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -26,6 +26,7 @@ verstage-y += reset.c romstage-y += boardid.c romstage-y += chromeos.c romstage-y += memlayout.ld +romstage-y += romstage.c romstage-y += sdram_configs.c ramstage-y += boardid.c diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c new file mode 100644 index 0000000..ccf42b9 --- /dev/null +++ b/src/mainboard/google/gru/romstage.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/cache.h> +#include <arch/cpu.h> +#include <arch/exception.h> +#include <arch/io.h> +#include <arch/mmu.h> +#include <boardid.h> +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <program_loading.h> +#include <romstage_handoff.h> +#include <soc/addressmap.h> +#include <soc/grf.h> +#include <soc/mmu_operations.h> +#include <soc/pwm.h> +#include <soc/tsadc.h> +#include <soc/sdram.h> +#include <symbols.h> +#include <soc/usb.h> + +static const uint64_t dram_size = + (uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS); + +static void init_dvs_outputs(void) +{ + int duty_ns; + uint32_t i; + uint32_t id; + + write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); /* GPU */ + write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); /* Big */ + write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); /* Little */ + write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); /* Centerlog */ + + /* + * Set up voltages for all DVS rails. + * + * LITTLE CPU: At the speed we're running at right now and on the + * early silicon, .9V is sane. If/when we run faster, let's bump this. + * + * CENTER LOGIC: There are some claims that this should simply always + * be .9 V. There are other claims that say that we need to adjust this + * dynamically depending on the memory frequency. Until this is sorted + * out, it appears that .9 V works for the 800 MHz. + * + * BIG CPU / GPU: These aren't used in coreboot. Init to .9V which is + * supposed to be a good default. + * + * Details: + * design_min = 0.8 + * design_max = 1.5 + * period = 3337 # 300 kHz + * volt = 1.1 + * # Intentionally round down (higher volt) to be safe. + * int((period / (design_max - design_min)) * (design_max - volt)) + * + * Apparently a period of 3333 is determined by EEs to be ideal for our + * board design / resistors / capacitors / regulators but due to + * clock dividers we actually get 3337. Solving, we get: + * period = 3337, volt = 1.1: 1906 + * period = 3337, volt = 1.0: 2383 + * period = 3337, volt = 0.9: 2860 + */ + duty_ns = 2860; /* 0.9v */ + + /* TODO: Clean all this up, implement proper pwm_regulator driver. */ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) { + id = board_id(); + if (id <= 2) + duty_ns = 1906; /* 1.1v */ + else if (id == 3) + duty_ns = 2621; /* 0.95v */ + else if (id >= 6) { + /* GPU: 3337 * (12043 - 9000) / (12043 - 7984) = 2501 */ + pwm_init(0, 3337, 2501); + /* BIG: 3337 * (12837 - 9000) / (12837 - 7985) = 2638 */ + pwm_init(1, 3337, 2638); + /* LIT: 3337 * (12807 - 9000) / (12807 - 8009) = 2647 */ + pwm_init(2, 3337, 2647); + /* CTR: 3337 * (10507 - 9500) / (10507 - 7996) = 1338 */ + pwm_init(3, 3337, 1338); + return; + } + } + + for (i = 0; i < 4; i++) + pwm_init(i, 3337, duty_ns); +} + +static void prepare_usb(void) +{ + /* + * Do dwc3 core soft reset and phy reset. Kick these resets + * off early so they get at least 100ms to settle. + */ + reset_usb_otg0(); + reset_usb_otg1(); +} + +void main(void) +{ + console_init(); + tsadc_init(TSHUT_POL_HIGH); + exception_init(); + + /* Init DVS to conservative values. */ + init_dvs_outputs(); + + prepare_usb(); + + sdram_init(get_sdram_config()); + + mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM); + mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + cbmem_initialize_empty(); + run_ramstage(); +} diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 3bfc05e..6e75278 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -49,7 +49,6 @@ romstage-y += clock.c romstage-y += mmu_operations.c romstage-y += ../common/pwm.c romstage-y += timer.c -romstage-y += romstage.c romstage-y += tsadc.c romstage-y += usb.c romstage-y += gpio.c diff --git a/src/soc/rockchip/rk3399/romstage.c b/src/soc/rockchip/rk3399/romstage.c deleted file mode 100644 index ccf42b9..0000000 --- a/src/soc/rockchip/rk3399/romstage.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <arch/cache.h> -#include <arch/cpu.h> -#include <arch/exception.h> -#include <arch/io.h> -#include <arch/mmu.h> -#include <boardid.h> -#include <cbfs.h> -#include <console/console.h> -#include <delay.h> -#include <program_loading.h> -#include <romstage_handoff.h> -#include <soc/addressmap.h> -#include <soc/grf.h> -#include <soc/mmu_operations.h> -#include <soc/pwm.h> -#include <soc/tsadc.h> -#include <soc/sdram.h> -#include <symbols.h> -#include <soc/usb.h> - -static const uint64_t dram_size = - (uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS); - -static void init_dvs_outputs(void) -{ - int duty_ns; - uint32_t i; - uint32_t id; - - write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); /* GPU */ - write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); /* Big */ - write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); /* Little */ - write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); /* Centerlog */ - - /* - * Set up voltages for all DVS rails. - * - * LITTLE CPU: At the speed we're running at right now and on the - * early silicon, .9V is sane. If/when we run faster, let's bump this. - * - * CENTER LOGIC: There are some claims that this should simply always - * be .9 V. There are other claims that say that we need to adjust this - * dynamically depending on the memory frequency. Until this is sorted - * out, it appears that .9 V works for the 800 MHz. - * - * BIG CPU / GPU: These aren't used in coreboot. Init to .9V which is - * supposed to be a good default. - * - * Details: - * design_min = 0.8 - * design_max = 1.5 - * period = 3337 # 300 kHz - * volt = 1.1 - * # Intentionally round down (higher volt) to be safe. - * int((period / (design_max - design_min)) * (design_max - volt)) - * - * Apparently a period of 3333 is determined by EEs to be ideal for our - * board design / resistors / capacitors / regulators but due to - * clock dividers we actually get 3337. Solving, we get: - * period = 3337, volt = 1.1: 1906 - * period = 3337, volt = 1.0: 2383 - * period = 3337, volt = 0.9: 2860 - */ - duty_ns = 2860; /* 0.9v */ - - /* TODO: Clean all this up, implement proper pwm_regulator driver. */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) { - id = board_id(); - if (id <= 2) - duty_ns = 1906; /* 1.1v */ - else if (id == 3) - duty_ns = 2621; /* 0.95v */ - else if (id >= 6) { - /* GPU: 3337 * (12043 - 9000) / (12043 - 7984) = 2501 */ - pwm_init(0, 3337, 2501); - /* BIG: 3337 * (12837 - 9000) / (12837 - 7985) = 2638 */ - pwm_init(1, 3337, 2638); - /* LIT: 3337 * (12807 - 9000) / (12807 - 8009) = 2647 */ - pwm_init(2, 3337, 2647); - /* CTR: 3337 * (10507 - 9500) / (10507 - 7996) = 1338 */ - pwm_init(3, 3337, 1338); - return; - } - } - - for (i = 0; i < 4; i++) - pwm_init(i, 3337, duty_ns); -} - -static void prepare_usb(void) -{ - /* - * Do dwc3 core soft reset and phy reset. Kick these resets - * off early so they get at least 100ms to settle. - */ - reset_usb_otg0(); - reset_usb_otg1(); -} - -void main(void) -{ - console_init(); - tsadc_init(TSHUT_POL_HIGH); - exception_init(); - - /* Init DVS to conservative values. */ - init_dvs_outputs(); - - prepare_usb(); - - sdram_init(get_sdram_config()); - - mmu_config_range((void *)0, (uintptr_t)dram_size, CACHED_MEM); - mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); - cbmem_initialize_empty(); - run_ramstage(); -}

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coreboot-gerrit August 2016