coreboot-gerrit August 2016

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New patch to review for coreboot: lenovo/x200, t400: use gpio.h instead of gpio_setup
by Arthur Heymans 31 Aug '16

31 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16379 -gerrit commit d002fc7cb89cda9a714301b6acbea3f15cf2b7da Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Aug 31 12:57:08 2016 +0200 lenovo/x200,t400: use gpio.h instead of gpio_setup Uses gpio.h instead of default_southbridge_gpio_setup to configure southbridge GPIO's. This is more consistent with how GPIO's are configured on newer targets. Change-Id: I6ccd0564b929e958864739b7cde04f5592c58479 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/t400/gpio.h | 301 +++++++++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/romstage.c | 22 +-- src/mainboard/lenovo/x200/gpio.h | 301 +++++++++++++++++++++++++++++++++++ src/mainboard/lenovo/x200/romstage.c | 21 +-- 4 files changed, 606 insertions(+), 39 deletions(-) diff --git a/src/mainboard/lenovo/t400/gpio.h b/src/mainboard/lenovo/t400/gpio.h new file mode 100644 index 0000000..0484bf2 --- /dev/null +++ b/src/mainboard/lenovo/t400/gpio.h @@ -0,0 +1,301 @@ +#ifndef LENOVO_T400_GPIO_H +#define LENOVO_T400_GPIO_H + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_NO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map t400_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; + +#endif diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 1deab65..bba53d1 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -30,29 +30,11 @@ #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> +#include "gpio.h" #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) -static void default_southbridge_gpio_setup(void) -{ - outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); - outl(0xe1a66dfe, DEFAULT_GPIOBASE + GP_IO_SEL); - outl(0xe3faef3f, DEFAULT_GPIOBASE + GP_LVL); - - /* Disable blink [31:0]. */ - outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); - /* Set input inversion [31:0]. */ - outl(0x00000102, DEFAULT_GPIOBASE + GPI_INV); - - /* Enable GPIOs [60:32]. */ - outl(0x030306f6, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); - /* Set input/output mode [60:32] (0 == out, 1 == in). */ - outl(0x1f55f9f1, DEFAULT_GPIOBASE + GP_IO_SEL2); - /* Set gpio levels [60:32]. */ - outl(0x1dffff53, DEFAULT_GPIOBASE + GP_LVL2); -} - static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -93,7 +75,7 @@ void mainboard_romstage_entry(unsigned long bist) gm45_early_reset(); } - default_southbridge_gpio_setup(); + setup_pch_gpios(&t400_gpio_map); /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); diff --git a/src/mainboard/lenovo/x200/gpio.h b/src/mainboard/lenovo/x200/gpio.h new file mode 100644 index 0000000..1407156 --- /dev/null +++ b/src/mainboard/lenovo/x200/gpio.h @@ -0,0 +1,301 @@ +#ifndef LENOVO_X200_GPIO_H +#define LENOVO_X200_GPIO_H + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_NO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_LOW, + .gpio63 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map x200_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; + +#endif diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 1deab65..c1e193a 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -30,28 +30,11 @@ #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> +#include "gpio.h" #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) -static void default_southbridge_gpio_setup(void) -{ - outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); - outl(0xe1a66dfe, DEFAULT_GPIOBASE + GP_IO_SEL); - outl(0xe3faef3f, DEFAULT_GPIOBASE + GP_LVL); - - /* Disable blink [31:0]. */ - outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); - /* Set input inversion [31:0]. */ - outl(0x00000102, DEFAULT_GPIOBASE + GPI_INV); - - /* Enable GPIOs [60:32]. */ - outl(0x030306f6, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); - /* Set input/output mode [60:32] (0 == out, 1 == in). */ - outl(0x1f55f9f1, DEFAULT_GPIOBASE + GP_IO_SEL2); - /* Set gpio levels [60:32]. */ - outl(0x1dffff53, DEFAULT_GPIOBASE + GP_LVL2); -} static void early_lpc_setup(void) { @@ -93,7 +76,7 @@ void mainboard_romstage_entry(unsigned long bist) gm45_early_reset(); } - default_southbridge_gpio_setup(); + setup_pch_gpios(&x200_gpio_map); /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10);

1 0

Patch set updated for coreboot: [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 31 Aug '16

31 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit aa24f527779eb26749deaad7fa3b3944cb4519fb Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN), 19 (BKLT_CTRL_SEL), 17 (DGFX_PWRGD_GPIO) were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. This also adds a IDG disable op, since it is used here to uncleam the VGA from the IGD. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 5 +++++ src/drivers/lenovo/hybrid_graphics.c | 24 ++++++++++++++++++++++-- src/mainboard/lenovo/t400/Kconfig | 20 ++++++++++++++++++++ src/northbridge/intel/gm45/gma.c | 13 +++++++++++++ 4 files changed, 60 insertions(+), 2 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..4c62de1 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -39,3 +39,8 @@ config HYBRID_GRAPHICS_GPIO_NUM help Set a default GPIO that sets the panel LVDS signal routing to integrated or discrete GPU. + +config ENABLE_DISCRETE_IS_HIGH + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..f5153f1 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -43,9 +43,21 @@ static void hybrid_graphics_disable_peg(struct device *dev) { struct device *peg_dev; + u8 disable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, disable_lvl); + /* configure BKLT_CTL */ + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, disable_lvl); + /* configure DGFX_PWRGD */ + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, disable_lvl); + /* configure GFX_PWR_EN_GPIO */ + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -62,13 +74,21 @@ static void hybrid_graphics_disable_peg(struct device *dev) static void hybrid_graphics_enable_peg(struct device *dev) { u8 hybrid_graphics_mode; + u8 enable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, enable_lvl); + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, enable_lvl); + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, enable_lvl); + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a444bf8..65bb116 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -56,4 +56,24 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config HYBRID_GRAPHICS_GPIO_NUM + int + default 22 + +config BKLT_CTRL_SEL_GPIO + int + default 19 + +config GFX_PWR_EN_GPIO + int + default 49 + +config DGFX_PWRGD_GPIO + int + default 17 + +config ENABLE_DISCRETE_IS_HIGH + bool + default y + endif # BOARD_LENOVO_T400 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index a89f9bb..18c770c 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -540,6 +540,18 @@ static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; +static void gma_func0_disable(struct device *dev) +{ + u16 reg16; + device_t dev_host = dev_find_slot(0, PCI_DEVFN(0, 0)); + + reg16 = pci_read_config16(dev_host, D0F0_GGC); + reg16 |= (1 << 1); /* disable VGA decode */ + pci_write_config16(dev_host, D0F0_GGC, reg16); + + dev->enabled = 0; +} + static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -548,6 +560,7 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .scan_bus = 0, .enable = 0, + .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, };

1 0

Patch set updated for coreboot: [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver
by Arthur Heymans 31 Aug '16

31 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16354 -gerrit commit 5f49dbeb8cde702236310da8df5602572f1385d1 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Aug 30 13:42:33 2016 +0200 [NEEDS TESTING] lenovo/T400: correct GPIO for hybrid driver Currently the hybrid driver uses GPIO 52 to configure mux. This is not the right GPIO on the T400 according to the schematics "MALIBU-3 EXT". It should be GPIO22. The polarities on the gpio's are also set differently on Lenovo T400. On the Lenovo T400 HIGH on GPIO22 means enable. Previously also gpio 49 (GFX_PWR_EN), 19 (BKLT_CTRL_SEL), 17 (DGFX_PWRGD_GPIO) were configured for hybrid graphics to work on T400, but this was reverted in 14d1a93e: "Revert mainboard/lenovo/t400: Add initial hybrid graphics support". This patch sets those gpios correctly again for the Lenovo T400. This also adds a IDG disable op, since it is used here to uncleam the VGA from the IGD. Change-Id: I3167303abeb6b3711d53508c61a340d03b1e050a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/lenovo/Kconfig | 5 +++++ src/drivers/lenovo/hybrid_graphics.c | 25 +++++++++++++++++++++++-- src/mainboard/lenovo/t400/Kconfig | 20 ++++++++++++++++++++ src/northbridge/intel/gm45/gma.c | 13 +++++++++++++ 4 files changed, 61 insertions(+), 2 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..4c62de1 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -39,3 +39,8 @@ config HYBRID_GRAPHICS_GPIO_NUM help Set a default GPIO that sets the panel LVDS signal routing to integrated or discrete GPU. + +config ENABLE_DISCRETE_IS_HIGH + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..72651d8 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -43,9 +43,22 @@ static void hybrid_graphics_disable_peg(struct device *dev) { struct device *peg_dev; + u8 disable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_LOW : GPIO_LEVEL_HIGH; + u32 tmp; /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, disable_lvl); + /* configure BKLT_CTL */ + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, disable_lvl); + /* configure DGFX_PWRGD */ + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, disable_lvl); + /* configure GFX_PWR_EN_GPIO */ + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, disable_lvl); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); dev->enabled = 0; @@ -62,13 +75,21 @@ static void hybrid_graphics_disable_peg(struct device *dev) static void hybrid_graphics_enable_peg(struct device *dev) { u8 hybrid_graphics_mode; + u8 enable_lvl = CONFIG_ENABLE_DISCRETE_IS_HIGH ? + GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW; hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, enable_lvl); + if (CONFIG_BKLT_CTRL_SEL_GPIO) + set_gpio(CONFIG_BKLT_CTRL_SEL_GPIO, enable_lvl); + if (CONFIG_DGFX_PWRGD_GPIO) + set_gpio(CONFIG_DGFX_PWRGD_GPIO, enable_lvl); + if (CONFIG_GFX_PWR_EN_GPIO) + set_gpio(CONFIG_GFX_PWR_EN_GPIO, enable_lvl); printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); dev->enabled = 1; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index a444bf8..65bb116 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -56,4 +56,24 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config HYBRID_GRAPHICS_GPIO_NUM + int + default 22 + +config BKLT_CTRL_SEL_GPIO + int + default 19 + +config GFX_PWR_EN_GPIO + int + default 49 + +config DGFX_PWRGD_GPIO + int + default 17 + +config ENABLE_DISCRETE_IS_HIGH + bool + default y + endif # BOARD_LENOVO_T400 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index a89f9bb..18c770c 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -540,6 +540,18 @@ static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; +static void gma_func0_disable(struct device *dev) +{ + u16 reg16; + device_t dev_host = dev_find_slot(0, PCI_DEVFN(0, 0)); + + reg16 = pci_read_config16(dev_host, D0F0_GGC); + reg16 |= (1 << 1); /* disable VGA decode */ + pci_write_config16(dev_host, D0F0_GGC, reg16); + + dev->enabled = 0; +} + static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -548,6 +560,7 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .scan_bus = 0, .enable = 0, + .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, };

1 0

Patch set updated for coreboot: southbridge/intel/i82801gx: transition away from device_t
by Antonello Dettori 31 Aug '16

31 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16370 -gerrit commit 01c8bfac9d944b40605d5a698269424df127b1f4 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:05:32 2016 +0200 southbridge/intel/i82801gx: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/i82801gx. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ia257318a7068b54739f319bfbba35f2a07826940 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/i82801gx/early_smbus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 2f9cdeb..47fe5f6 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3);

1 0

Patch set updated for coreboot: lenovo/x60: transition away from device_t
by Antonello Dettori 31 Aug '16

31 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16372 -gerrit commit 465a1da7616dc847b85f190eae2f82f98e189a00 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:15:49 2016 +0200 lenovo/x60: transition away from device_t Replace the use of the old device_t definition inside mainboard/lenovo/x60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/lenovo/x60/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index aabbf65..c735ce2 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -102,7 +102,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0x06);

1 0

Patch set updated for coreboot: northbridge/intel/i945: transition away from device_t
by Antonello Dettori 31 Aug '16

31 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16371 -gerrit commit 2488e3d000e82ad4f1f1f29080e223154b21d7d4 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:11:24 2016 +0200 northbridge/intel/i945: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/i945. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/i945/debug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index d26e84e..65189bd 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -23,7 +23,7 @@ void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -61,7 +61,7 @@ void dump_pci_device(unsigned dev) void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) {

1 0

Patch set updated for coreboot: northbridge/intel/i945: transition from device_t
by Antonello Dettori 31 Aug '16

31 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16371 -gerrit commit e4b277f18e25358a64a2609f5bf32aa414093160 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:11:24 2016 +0200 northbridge/intel/i945: transition from device_t Replace the use of the old device_t definition inside northbridge/intel/i945. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/i945/debug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index d26e84e..65189bd 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -23,7 +23,7 @@ void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -61,7 +61,7 @@ void dump_pci_device(unsigned dev) void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) {

1 0

Patch set updated for coreboot: soc/intel/apollolake: Use consistent convention for community names
by Furquan Shaikh 31 Aug '16

31 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16353 -gerrit commit 3df67d2ee05b7e7b96ff641180a34bf504478edf Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Aug 29 22:51:41 2016 -0700 soc/intel/apollolake: Use consistent convention for community names Instead of using a mix of _N and _NORTH, _NW and _NORTHWEST for GPIO community names, follow one single convention. This allows for re-using macros easily. Change-Id: Icd9cf9ef70d03576d864688cf5d6946124c259c3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/acpi/gpio.asl | 8 ++++---- src/soc/intel/apollolake/gpio.c | 24 ++++++++++++------------ src/soc/intel/apollolake/include/soc/gpio_defs.h | 10 +++++----- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 030d3eb..03b8edd 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -38,7 +38,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_NORTH, 16, Local0) + ShiftLeft (GPIO_N, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -69,7 +69,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_NORTHWEST, 16, Local0) + ShiftLeft (GPIO_NW, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -100,7 +100,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_WEST, 16, Local0) + ShiftLeft (GPIO_W, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -131,7 +131,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_SOUTHWEST, 16, Local0) + ShiftLeft (GPIO_SW, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index 1073e16..e56f147 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -31,25 +31,25 @@ static const struct pad_community { const char *grp_name; } gpio_communities[] = { { - .port = GPIO_SOUTHWEST, + .port = GPIO_SW, .first_pad = SW_OFFSET, .num_gpi_regs = NUM_SW_GPI_REGS, .gpi_offset = 0, .grp_name = "GPIO_GPE_SW", }, { - .port = GPIO_WEST, + .port = GPIO_W, .first_pad = W_OFFSET, .num_gpi_regs = NUM_W_GPI_REGS, .gpi_offset = NUM_SW_GPI_REGS, .grp_name = "GPIO_GPE_W", }, { - .port = GPIO_NORTHWEST, + .port = GPIO_NW, .first_pad = NW_OFFSET, .num_gpi_regs = NUM_NW_GPI_REGS, .gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS, .grp_name = "GPIO_GPE_NW", }, { - .port = GPIO_NORTH, + .port = GPIO_N, .first_pad = N_OFFSET, .num_gpi_regs = NUM_N_GPI_REGS, .gpi_offset = NUM_NW_GPI_REGS+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS, @@ -229,13 +229,13 @@ const char *gpio_acpi_path(gpio_t gpio_num) const struct pad_community *comm = gpio_get_community(gpio_num); switch (comm->port) { - case GPIO_NORTH: + case GPIO_N: return "\\_SB.GPO0"; - case GPIO_NORTHWEST: + case GPIO_NW: return "\\_SB.GPO1"; - case GPIO_WEST: + case GPIO_W: return "\\_SB.GPO2"; - case GPIO_SOUTHWEST: + case GPIO_SW: return "\\_SB.GPO3"; } @@ -247,13 +247,13 @@ uint16_t gpio_acpi_pin(gpio_t gpio_num) const struct pad_community *comm = gpio_get_community(gpio_num); switch (comm->port) { - case GPIO_NORTH: + case GPIO_N: return PAD_N(gpio_num); - case GPIO_NORTHWEST: + case GPIO_NW: return PAD_NW(gpio_num); - case GPIO_WEST: + case GPIO_W: return PAD_W(gpio_num); - case GPIO_SOUTHWEST: + case GPIO_SW: return PAD_SW(gpio_num); } diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 88fa475..70f86ca 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -130,11 +130,11 @@ #define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8)) /* IOSF port numbers for GPIO comminuties*/ -#define GPIO_SOUTHWEST 0xc0 -#define GPIO_SOUTH 0xc2 -#define GPIO_NORTHWEST 0xc4 -#define GPIO_NORTH 0xc5 -#define GPIO_WEST 0xc7 +#define GPIO_SW 0xc0 +#define GPIO_S 0xc2 +#define GPIO_NW 0xc4 +#define GPIO_N 0xc5 +#define GPIO_W 0xc7 #define GPI_SMI_STS_0 0x140 #define GPI_SMI_EN_0 0x150

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Patch set updated for coreboot: soc/intel/apollolake: Disable Periodic Retraining per-SKU
by Andrey Petrov 31 Aug '16

31 Aug '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16320 -gerrit commit 1fa33e10e1e7ad566924d95085bc7e3242bcf987 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Aug 25 11:06:08 2016 -0700 soc/intel/apollolake: Disable Periodic Retraining per-SKU Certain LPDDR4 models have some HW issues that can be worked around by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU. BUG=chrome-os-partner:55466 TEST=run RMT test, pass Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/google/reef/romstage.c | 2 ++ src/soc/intel/apollolake/include/soc/meminit.h | 1 + src/soc/intel/apollolake/meminit.c | 2 ++ 3 files changed, 5 insertions(+) diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index e8d8e16..964dee4 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -103,6 +103,7 @@ static const struct lpddr4_sku skus[] = { .ch0_dual_rank = 1, .ch1_dual_rank = 1, .part_num = "MT53B512M32D2NP", + .disable_periodic_retraining = 1, }, /* MT53B256M32D1NP-062 WT:C - both logical channels */ [3] = { @@ -110,6 +111,7 @@ static const struct lpddr4_sku skus[] = { .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "MT53B256M32D1NP", + .disable_periodic_retraining = 1, }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index c115c4a..06d2b58 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -102,6 +102,7 @@ struct lpddr4_sku { int ch0_dual_rank; int ch1_dual_rank; const char *part_num; + bool disable_periodic_retraining; }; struct lpddr4_cfg { diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 03e9ac4..d0e7683 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -254,6 +254,8 @@ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, sku->ch1_dual_rank, lpcfg->swizzle_config); } + + cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining; } void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)

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New patch to review for coreboot: mainboard/google/reef: drop proto gpio support
by Aaron Durbin 31 Aug '16

31 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16377 -gerrit commit a9ff6948025de8a1926a4fd385c39da9c8fac491 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 30 17:31:43 2016 -0500 mainboard/google/reef: drop proto gpio support Many changes make proto boards very hard to work with since proto boards were using A stepping processors. Everyone has moved on. Therefore, drop non-proto support. BUG=chrome-os-partner:56791 Change-Id: I2985e3965b1b69445e22506bd664b4cbca13c8ab Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/gpio.h | 19 ++++--------------- src/mainboard/google/reef/mainboard.c | 8 -------- 2 files changed, 4 insertions(+), 23 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index d3b1e91..775d089 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -163,6 +163,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ @@ -281,6 +282,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_0, UP_20K, DEEP), PAD_CFG_GPI(GPIO_1, UP_20K, DEEP), PAD_CFG_GPI(GPIO_2, UP_20K, DEEP), + PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL), /* FP_INT */ PAD_CFG_GPI(GPIO_4, UP_20K, DEEP), PAD_CFG_GPI(GPIO_5, UP_20K, DEEP), PAD_CFG_GPI(GPIO_6, UP_20K, DEEP), @@ -293,6 +295,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ + PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */ @@ -324,6 +327,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */ PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */ + PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ @@ -371,20 +375,5 @@ static const struct pad_config sleep_gpio_table[] = { #define MEM_CONFIG1 GPIO_102 #define MEM_CONFIG0 GPIO_101 -static const struct pad_config proto_diff_table[] = { - PAD_CFG_GPI(GPIO_3, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* unused */ - PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */ - PAD_CFG_GPO(PMU_WAKE_B, 0, DEEP), /* EN_PP3300_EMMC_ODL */ -}; - -/* Wake peripheral signals post proto. */ -static const struct pad_config nonproto_diff_table[] = { - PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL), /* FP_INT */ - PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ - PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ - PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ -}; - #endif /* __ACPI__ */ #endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 0c4ba8d..92e5609 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -33,14 +33,6 @@ static void mainboard_init(void *chip_info) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - /* Apply proto board settings if board matches. */ - if (boardid == 0) - gpio_configure_pads(proto_diff_table, - ARRAY_SIZE(proto_diff_table)); - else - gpio_configure_pads(nonproto_diff_table, - ARRAY_SIZE(nonproto_diff_table)); - mainboard_ec_init(); }

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coreboot-gerrit August 2016