coreboot-gerrit August 2016

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Patch set updated for coreboot: apollolake: relocate fsp header files to vendorcode
by Brandon Breitenstein 31 Aug '16

31 Aug '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16310 -gerrit commit 35ff83196b2fbeb72f947249678d669f0b5be08a Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Tue Aug 23 15:03:50 2016 -0700 apollolake: relocate fsp header files to vendorcode FSP header files should be located in vendorcode, not soc directory. This patch includes changes any references to the old location to the new location. Change-Id: I44270392617418ec1b9dec15ee187863f2503341 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/soc_binding.h | 6 +- src/mainboard/intel/amenia/romstage.c | 2 +- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/fsp/FspUpd.h | 48 - src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 721 --------- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 1541 -------------------- src/soc/intel/apollolake/include/soc/meminit.h | 2 +- src/soc/intel/apollolake/meminit.c | 2 +- .../intel/fsp/fsp2_0/apollolake/FspUpd.h | 48 + .../intel/fsp/fsp2_0/apollolake/FspmUpd.h | 721 +++++++++ .../intel/fsp/fsp2_0/apollolake/FspsUpd.h | 1541 ++++++++++++++++++++ 11 files changed, 2317 insertions(+), 2316 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index cfe5a02..8709cb7 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -18,13 +18,13 @@ #pragma pack(push) /* - * This file is found in the soc / chipset directory. It is + * This file is found in the vendorcode directory. It is * a per implementation specific header. i.e. different FSP implementations * for different chipsets. */ #include <Base.h> -#include <soc/fsp/FspmUpd.h> -#include <soc/fsp/FspsUpd.h> +#include <FspmUpd.h> +#include <FspsUpd.h> #pragma pack(pop) diff --git a/src/mainboard/intel/amenia/romstage.c b/src/mainboard/intel/amenia/romstage.c index 6719472..13e096b 100644 --- a/src/mainboard/intel/amenia/romstage.c +++ b/src/mainboard/intel/amenia/romstage.c @@ -17,7 +17,7 @@ #include <soc/romstage.h> #include <string.h> -#include <soc/fsp/FspmUpd.h> +#include <FspmUpd.h> /* Channel 0 PHY to DUnit DQ mapping */ static const uint8_t swizzling_ch0_amenia[] = { diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1f3c276..3c45cbe 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -93,6 +93,7 @@ verstage-y += reset.c verstage-y += spi.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake # Since FSP-M runs in CAR we need to relocate it to a specific address $(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h deleted file mode 100644 index a7114ce..0000000 --- a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#pragma pack(push, 1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ - -#pragma pack(pop) - -#endif diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h deleted file mode 100644 index 48225e0..0000000 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ /dev/null @@ -1,721 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -#define MAX_CHANNELS_NUM 4 -#define MAX_DIMMS_NUM 1 - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - /** Module part number for DRR3 is 18 bytes - but DRR4 is 20 bytes as per JEDEC Spec, so - reserving 20 bytes **/ - UINT8 ModulePartNum[20]; -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT8 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT16 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Debug Serial Port Base address - Debug serial port base address. This option will be used only when the 'Serial Port - Debug Device' option is set to 'External Device'. 0x00000000(Default). -**/ - UINT32 SerialDebugPortAddress; - -/** Offset 0x0044 - Debug Serial Port Type - 16550 compatible debug serial port resource type. NONE means no serial port support. - 0x02:MMIO(Default). - 0:NONE, 1:I/O, 2:MMIO -**/ - UINT8 SerialDebugPortType; - -/** Offset 0x0045 - Serial Port Debug Device - Select active serial port device for debug. For SOC UART devices,'Debug Serial Port - Base' options will be ignored. 0x02:SOC UART2(Default). - 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device -**/ - UINT8 SerialDebugPortDevice; - -/** Offset 0x0046 - Debug Serial Port Stride Size - Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). - 0:1, 2:4 -**/ - UINT8 SerialDebugPortStrideSize; - -/** Offset 0x0047 - Memory Fast Boot - Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0048 - Integrated Graphics Device - Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video - Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 Igd; - -/** Offset 0x0049 - DVMT Pre-Allocated - Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal - Graphics Device. 0x02:64 MB(Default). - 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 - MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, - 0x0F:480 MB, 0x10:512 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x004A - Aperture Size - Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), - 0x2:256 MB, 0x3:512 MB. - 0x1:128 MB, 0x2:256 MB, 0x3:512 MB -**/ - UINT8 IgdApertureSize; - -/** Offset 0x004B - GTT Size - Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 - MB(Default). - 0x1:2 MB, 0x2:4 MB, 0x3:8 MB -**/ - UINT8 GttSize; - -/** Offset 0x004C - Primary Display - Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), - 0x2:IGD, 0x3:PCI - 0x0:AUTO, 0x2:IGD, 0x3:PCI -**/ - UINT8 PrimaryVideoAdaptor; - -/** Offset 0x004D - Package - NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L - is being used. 0x00(Default). - 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD -**/ - UINT8 Package; - -/** Offset 0x004E - Profile - Profile list. 0x19(Default). - 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, - 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, - 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, - 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, - 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, - 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, - 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, - 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, - 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, - 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, - 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, - 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 -**/ - UINT8 Profile; - -/** Offset 0x004F - MemoryDown - Memory Down. 0x0(Default). - 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 -**/ - UINT8 MemoryDown; - -/** Offset 0x0050 - DDR3LPageSize - NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB. - 0x1:1KB, 0x2:2KB -**/ - UINT8 DDR3LPageSize; - -/** Offset 0x0051 - DDR3LASR - NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported. - 0x0:Not Supported, 0x1:Supported -**/ - UINT8 DDR3LASR; - -/** Offset 0x0052 - ScramblerSupport - Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default). - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x0053 - ChannelHashMask - Channel Hash Mask. 0x00(Default). -**/ - UINT16 ChannelHashMask; - -/** Offset 0x0055 - SliceHashMask - Slice Hash Mask. 0x00(Default). -**/ - UINT16 SliceHashMask; - -/** Offset 0x0057 - InterleavedMode - Interleaved Mode. 0x00:Disable(Default), 0x02:Enable. - 0x0:Disable, 0x2:Enable -**/ - UINT8 InterleavedMode; - -/** Offset 0x0058 - ChannelsSlicesEnable - Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 ChannelsSlicesEnable; - -/** Offset 0x0059 - MinRefRate2xEnable - Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), - 0x01:Enable. - $EN_DIS -**/ - UINT8 MinRefRate2xEnable; - -/** Offset 0x005A - DualRankSupportEnable - Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 DualRankSupportEnable; - -/** Offset 0x005B - RmtMode - Rank Margin Tool Mode. 0x00(Default). - $EN_DIS -**/ - UINT8 RmtMode; - -/** Offset 0x005C - MemorySizeLimit - Memory Size Limit: This value is used to restrict the total amount of memory and - the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, - 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) -**/ - UINT16 MemorySizeLimit; - -/** Offset 0x005E - LowMemoryMaxValue - Low Memory Max Value: This value is used to restrict the amount of memory below - 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 - = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). -**/ - UINT16 LowMemoryMaxValue; - -/** Offset 0x0060 - DisableFastBoot - 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train - of memory. - $EN_DIS -**/ - UINT8 DisableFastBoot; - -/** Offset 0x0061 - HighMemoryMaxValue - High Memory Max Value: This value is used to restrict the amount of memory above - 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, - 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). -**/ - UINT16 HighMemoryMaxValue; - -/** Offset 0x0063 - DIMM0SPDAddress - DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). -**/ - UINT8 DIMM0SPDAddress; - -/** Offset 0x0064 - DIMM1SPDAddress - DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). -**/ - UINT8 DIMM1SPDAddress; - -/** Offset 0x0065 - Ch0_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default). -**/ - UINT8 Ch0_RankEnable; - -/** Offset 0x0066 - Ch0_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch0_DeviceWidth; - -/** Offset 0x0067 - Ch0_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch0_DramDensity; - -/** Offset 0x0068 - Ch0_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank - Address Hashing Enable. See Address Mapping section for full description. 0:Bank - Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] - This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). - 0x03(Default). -**/ - UINT8 Ch0_Option; - -/** Offset 0x0069 - Ch0_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. -**/ - UINT8 Ch0_OdtConfig; - -/** Offset 0x006A - Ch0_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). -**/ - UINT8 Ch0_TristateClk1; - -/** Offset 0x006B - Ch0_Mode2N - 2N Mode. 0x00(Default). -**/ - UINT8 Ch0_Mode2N; - -/** Offset 0x006C - Ch0_OdtLevels - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. - [1] Bank Address Hashing Enable. See Address Mapping section for full description. - 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). -**/ - UINT8 Ch0_OdtLevels; - -/** Offset 0x006D - Ch1_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch1 rank. -**/ - UINT8 Ch1_RankEnable; - -/** Offset 0x006E - Ch1_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch1_DeviceWidth; - -/** Offset 0x006F - Ch1_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default). - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch1_DramDensity; - -/** Offset 0x0070 - Ch1_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB - (B), 0x03(Default). -**/ - UINT8 Ch1_Option; - -/** Offset 0x0071 - Ch1_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. -**/ - UINT8 Ch1_OdtConfig; - -/** Offset 0x0072 - Ch1_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). -**/ - UINT8 Ch1_TristateClk1; - -/** Offset 0x0073 - Ch1_Mode2N - 2N Mode. 0x00(Default). -**/ - UINT8 Ch1_Mode2N; - -/** Offset 0x0074 - Ch1_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. -**/ - UINT8 Ch1_OdtLevels; - -/** Offset 0x0075 - Ch2_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch2 rank. -**/ - UINT8 Ch2_RankEnable; - -/** Offset 0x0076 - Ch2_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch2_DeviceWidth; - -/** Offset 0x0077 - Ch2_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch2_DramDensity; - -/** Offset 0x0078 - Ch2_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description.. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). - 01:2KB (B). -**/ - UINT8 Ch2_Option; - -/** Offset 0x0079 - Ch2_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. -**/ - UINT8 Ch2_OdtConfig; - -/** Offset 0x007A - Ch2_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). -**/ - UINT8 Ch2_TristateClk1; - -/** Offset 0x007B - Ch2_Mode2N - 2N Mode. 0x00(Default). -**/ - UINT8 Ch2_Mode2N; - -/** Offset 0x007C - Ch2_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. -**/ - UINT8 Ch2_OdtLevels; - -/** Offset 0x007D - Ch3_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default). -**/ - UINT8 Ch3_RankEnable; - -/** Offset 0x007E - Ch3_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), - 0x01:x16, 0x02:x32, 0x03:x64. - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch3_DeviceWidth; - -/** Offset 0x007F - Ch3_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), - 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch3_DramDensity; - -/** Offset 0x0080 - Ch3_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description.. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 - - 2KB (B). -**/ - UINT8 Ch3_Option; - -/** Offset 0x0081 - Ch3_OdtConfig - ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG. -**/ - UINT8 Ch3_OdtConfig; - -/** Offset 0x0082 - Ch3_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). -**/ - UINT8 Ch3_TristateClk1; - -/** Offset 0x0083 - Ch3_Mode2N - 2N Mode. 0x00(Default). -**/ - UINT8 Ch3_Mode2N; - -/** Offset 0x0084 - Ch3_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. -**/ - UINT8 Ch3_OdtLevels; - -/** Offset 0x0085 - RmtCheckRun - RmtCheckRun: 0x00(Default). -**/ - UINT8 RmtCheckRun; - -/** Offset 0x0086 - Ch0_Bit_swizzling - Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch0_Bit_swizzling[32]; - -/** Offset 0x00A6 - Ch1_Bit_swizzling - Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch1_Bit_swizzling[32]; - -/** Offset 0x00C6 - Ch2_Bit_swizzling - Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch2_Bit_swizzling[32]; - -/** Offset 0x00E6 - Ch3_Bit_swizzling - Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch3_Bit_swizzling[32]; - -/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold - RmtMarginCheckScaleHighThreshold. 0x0000(Default). -**/ - UINT16 RmtMarginCheckScaleHighThreshold; - -/** Offset 0x0108 - MsgLevelMask - MsgLevelMask. 0x00000000(Default). -**/ - UINT32 MsgLevelMask; - -/** Offset 0x010C -**/ - UINT32 UnusedUpdSpace0; - -/** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4 - Number of Entries in PreMem GPIO Table. 0(Default). -**/ - UINT8 PreMemGpioTableEntryNum; - -/** Offset 0x0111 - PreMem GPIO Pin Number for each table - Number of Pins in each PreMem GPIO Table. 0(Default). -**/ - UINT8 PreMemGpioTablePinNum[4]; - -/** Offset 0x0115 - PreMem GPIO Table Pointer - Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default). -**/ - UINT32 PreMemGpioTablePtr; - -/** Offset 0x0119 - Enhance the port 8xh decoding - Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnhancePort8xhDecoding; - -/** Offset 0x011A - OEM File Loading Address - Determine the memory base address to load a specified file from CSE file system - after memory is available. -**/ - UINT32 OemLoadingBase; - -/** Offset 0x011E - OEM File Name to Load - Specify a file name to load from CSE file system after memory is available. Empty - indicates no file needs to be loaded. -**/ - UINT8 OemFileName[16]; - -/** Offset 0x012E - SPD Data Write - Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 SpdWriteEnable; - -/** Offset 0x012F - MRC Training Data Saving - Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 MrcDataSaving; - -/** Offset 0x0130 - eMMC Trace Length - Select eMMC trace length to load OEM file from when loading OEM file name is specified. - 0x0:Long(Default), 0x1:Short. - 0x0:Long, 0x1:Short -**/ - UINT8 eMMCTraceLen; - -/** Offset 0x0131 -**/ - VOID* MrcBootDataPtr; - -/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB - Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of - CSE. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 SkipCseRbp; - -/** Offset 0x0136 - Npk Enable - Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default). - 0:Disable, 1:Enable, 2:Debugger, 3:Auto -**/ - UINT8 NpkEn; - -/** Offset 0x0137 - FW Trace Enable - Enable/Disable FW Trace. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 FwTraceEn; - -/** Offset 0x0138 - FW Trace Destination - FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB, - 4-NPK_TRACE_TO_PTI(Default). -**/ - UINT8 FwTraceDestination; - -/** Offset 0x0139 - NPK Recovery Dump - Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 RecoverDump; - -/** Offset 0x013A - Memory Region 0 Buffer WrapAround - Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - UINT8 Msc0Wrap; - -/** Offset 0x013B - Memory Region 1 Buffer WrapAround - Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - UINT8 Msc1Wrap; - -/** Offset 0x013C - Memory Region 0 Buffer Size - Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, - 6-512MB, 7-1GB. -**/ - UINT32 Msc0Size; - -/** Offset 0x0140 - Memory Region 1 Buffer Size - Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, - 6-512MB, 7-1GB. -**/ - UINT32 Msc1Size; - -/** Offset 0x0144 - PTI Mode - PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. -**/ - UINT8 PtiMode; - -/** Offset 0x0145 - PTI Training - PTI Training. 0-off(Default), 1-6=1-6. -**/ - UINT8 PtiTraining; - -/** Offset 0x0146 - PTI Speed - PTI Speed. 0-full, 1-half, 2-quarter(Default). -**/ - UINT8 PtiSpeed; - -/** Offset 0x0147 - Punit Message Level - Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. -**/ - UINT8 PunitMlvl; - -/** Offset 0x0148 - PMC Message Level - PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. -**/ - UINT8 PmcMlvl; - -/** Offset 0x0149 - SW Trace Enable - Enable/Disable SW Trace. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SwTraceEn; - -/** Offset 0x014A - Periodic Retraining Disable - Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 PeriodicRetrainingDisable; - -/** Offset 0x014B -**/ - UINT8 ReservedFspmUpd[5]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0150 -**/ - UINT32 Signature; - -/** Offset 0x0154 -**/ - UINT8 ReservedFspmTestUpd[28]; -} FSP_M_TEST_CONFIG; - -/** Fsp M Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0170 -**/ - UINT32 Signature; - -/** Offset 0x0174 -**/ - UINT8 ReservedFspmRestrictedUpd[138]; -} FSP_M_RESTRICTED_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0150 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x0170 -**/ - FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; - -/** Offset 0x01FE -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack(pop) - -#endif diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h deleted file mode 100644 index 553eba3..0000000 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ /dev/null @@ -1,1541 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - ActiveProcessorCores - Number of active cores. 0:Disable(Default), 1:Enable. -**/ - UINT8 ActiveProcessorCores; - -/** Offset 0x0021 - Disable Core1 - Disable/Enable Core1. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore1; - -/** Offset 0x0022 - Disable Core2 - Disable/Enable Core2. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore2; - -/** Offset 0x0023 - Disable Core3 - Disable/Enable Core3. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore3; - -/** Offset 0x0024 - VMX Enable - Enable or Disable VMX. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x0025 - Memory region allocation for Processor Trace - Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to - 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default) -**/ - UINT8 ProcTraceMemSize; - -/** Offset 0x0026 - Enable Processor Trace - Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 ProcTraceEnable; - -/** Offset 0x0027 - Eist - Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0028 - Boot PState - Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. -**/ - UINT8 BootPState; - -/** Offset 0x0029 - CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableCx; - -/** Offset 0x002A - Enhanced C-states - Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x002B - Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x002C - Max Pkg Cstate - Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, - 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x002D -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x002E - C-State auto-demotion - C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 - Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion - to C1 and C3. -**/ - UINT8 CStateAutoDemotion; - -/** Offset 0x002F - C-State un-demotion - C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, - 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. -**/ - UINT8 CStateUnDemotion; - -/** Offset 0x0030 - Max Core C-State - Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). -**/ - UINT8 MaxCoreCState; - -/** Offset 0x0031 - Package C-State Demotion - Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x0032 - Package C-State Un-demotion - Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x0033 - Turbo Mode - Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0034 - SC HDA Verb Table Entry Number - Number of Entries in Verb Table. 0(Default). -**/ - UINT8 HdaVerbTableEntryNum; - -/** Offset 0x0035 - SC HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. 0x00000000(Default). -**/ - UINT32 HdaVerbTablePtr; - -/** Offset 0x0039 - Enable/Disable P2SB device hidden. - Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 P2sbUnhide; - -/** Offset 0x003A - IPU Enable/Disable - Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IpuEn; - -/** Offset 0x003B - IMGU ACPI mode selection - 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. - 0:Disable, 1:IGFX Child device, 2:ACPI device -**/ - UINT8 IpuAcpiMode; - -/** Offset 0x003C - GttMmAdr - GttMmAdr structure for initialization. 0xBF000000(Default). -**/ - UINT32 GttMmAdr; - -/** Offset 0x0040 - GmAdr - GmAdr structure for initialization. 0xA0000000(Default). -**/ - UINT32 GmAdr; - -/** Offset 0x0044 - Enable ForceWake - Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 ForceWake; - -/** Offset 0x0045 - Enable PavpLock - Enable/disable PavpLock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PavpLock; - -/** Offset 0x0046 - Enable GraphicsFreqModify - Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsFreqModify; - -/** Offset 0x0047 - Enable GraphicsFreqReq - Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsFreqReq; - -/** Offset 0x0048 - Enable GraphicsVideoFreq - Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsVideoFreq; - -/** Offset 0x0049 - Enable PmLock - Enable/disable PmLock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PmLock; - -/** Offset 0x004A - Enable DopClockGating - Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DopClockGating; - -/** Offset 0x004B - Enable UnsolicitedAttackOverride - Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UnsolicitedAttackOverride; - -/** Offset 0x004C - Enable WOPCMSupport - Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 WOPCMSupport; - -/** Offset 0x004D - Enable WOPCMSize - Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 WOPCMSize; - -/** Offset 0x004E - Enable PowerGating - Enable/disable PowerGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PowerGating; - -/** Offset 0x004F - Enable UnitLevelClockGating - Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UnitLevelClockGating; - -/** Offset 0x0050 - Enable FastBoot - Enable/disable FastBoot. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 FastBoot; - -/** Offset 0x0051 - Enable DynSR - Enable/disable DynSR. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DynSR; - -/** Offset 0x0052 - Enable SaIpuEnable - Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x0053 - BMP Logo Data Size - BMP logo data buffer size. 0x00000000(Default). -**/ - UINT32 LogoSize; - -/** Offset 0x0057 - BMP Logo Data Pointer - BMP logo data pointer to a BMP format buffer. 0x00000000(Default). -**/ - UINT32 LogoPtr; - -/** Offset 0x005B - Graphics Configuration Data Pointer - Graphics configuration data used for initialization. 0x00000000(Default). -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x005F - GT PM Support - Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x0060 - RC6(Render Standby) - Enable/Disable render standby support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableRenderStandby; - -/** Offset 0x0061 - PAVP Enable - Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0062 - PAVP PR3 - Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PavpPr3; - -/** Offset 0x0063 - CdClock Frequency selection - 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). - 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz -**/ - UINT8 CdClock; - -/** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit - Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0065 - Write Protection Support - Enable/disable Write Protection. 0:Disable, 1:Enable(Default). -**/ - UINT8 WriteProtectionEnable[5]; - -/** Offset 0x006A - Read Protection Support - Enable/disable Read Protection. 0:Disable, 1:Enable(Default). -**/ - UINT8 ReadProtectionEnable[5]; - -/** Offset 0x006F - Protected Range Limitation - The address of the upper limit of protection, 0x0FFFh(Default). -**/ - UINT16 ProtectedRangeLimit[5]; - -/** Offset 0x0079 - Protected Range Base - The base address of the upper limit of protection. 0x0000(Default). -**/ - UINT16 ProtectedRangeBase[5]; - -/** Offset 0x0083 - Enable SC Gaussian Mixture Models - Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Gmm; - -/** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk - Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingPgcbClkTrunk; - -/** Offset 0x0085 - GMM Clock Gating - Sideband - Enable/disable Sideband. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSb; - -/** Offset 0x0086 - GMM Clock Gating - Sideband - Enable/disable Sideband. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSbClkTrunk; - -/** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition - Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSbClkPartition; - -/** Offset 0x0088 - GMM Clock Gating - Core - Enable/disable Core. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingCore; - -/** Offset 0x0089 - GMM Clock Gating - DMA - Enable/disable DMA. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingDma; - -/** Offset 0x008A - GMM Clock Gating - Register Access - Enable/disable Register Access. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingRegAccess; - -/** Offset 0x008B - GMM Clock Gating - Host - Enable/disable Host. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingHost; - -/** Offset 0x008C - GMM Clock Gating - Partition - Enable/disable Partition. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingPartition; - -/** Offset 0x008D - Clock Gating - Trunk - Enable/disable Trunk. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingTrunk; - -/** Offset 0x008E - HD Audio Support - Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 HdaEnable; - -/** Offset 0x008F - HD Audio DSP Support - Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DspEnable; - -/** Offset 0x0090 - Azalia wake-on-ring - Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 Pme; - -/** Offset 0x0091 - HD-Audio I/O Buffer Ownership - Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default) - 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and - I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers -**/ - UINT8 HdAudioIoBufferOwnership; - -/** Offset 0x0092 - HD-Audio I/O Buffer Voltage - HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. - 0: 3.3V, 1: 1.8V -**/ - UINT8 HdAudioIoBufferVoltage; - -/** Offset 0x0093 - HD-Audio Virtual Channel Type - HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. - 0: VC0, 1: VC1 -**/ - UINT8 HdAudioVcType; - -/** Offset 0x0094 - HD-Audio Link Frequency - HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, - 4:96MHz, 5:Invalid. - 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid -**/ - UINT8 HdAudioLinkFrequency; - -/** Offset 0x0095 - HD-Audio iDisp-Link Frequency - HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, - 4:96MHz, 5:Invalid. - 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid -**/ - UINT8 HdAudioIDispLinkFrequency; - -/** Offset 0x0096 - HD-Audio iDisp-Link T-Mode - HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. - 0: 2T, 1: 1T -**/ - UINT8 HdAudioIDispLinkTmode; - -/** Offset 0x0097 - HD-Audio Disp DMIC - HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. - 0: Disable, 1: 2ch array, 2: 4ch array -**/ - UINT8 DspEndpointDmic; - -/** Offset 0x0098 - HD-Audio Bluetooth - Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DspEndpointBluetooth; - -/** Offset 0x0099 - HD-Audio I2S SHK - Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DspEndpointI2sSkp; - -/** Offset 0x009A - HD-Audio I2S HP - Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DspEndpointI2sHp; - -/** Offset 0x009B - HD-Audio Controller Power Gating - Enable/Disable HD-Audio Controller Power Gating. This option is deprecated. - $EN_DIS -**/ - UINT8 AudioCtlPwrGate; - -/** Offset 0x009C - HD-Audio ADSP Power Gating - Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated. - $EN_DIS -**/ - UINT8 AudioDspPwrGate; - -/** Offset 0x009D - HD-Audio CSME Memory Transfers - Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. - 0: VC0, 1: VC2 -**/ - UINT8 Mmt; - -/** Offset 0x009E - HD-Audio Host Memory Transfers - Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. - 0: VC0, 1: VC2 -**/ - UINT8 Hmt; - -/** Offset 0x009F - HD-Audio BIOS Configuration Lock Down - Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 BiosCfgLockDown; - -/** Offset 0x00A0 - HD-Audio Power Gating - Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HDAudioPwrGate; - -/** Offset 0x00A1 - HD-Audio Clock Gatingn - Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HDAudioClkGate; - -/** Offset 0x00A2 - Bitmask of DSP Feature - Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: - Intel WoV, 1: Windows Voice Activation -**/ - UINT32 DspFeatureMask; - -/** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules - Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: - Intel WoV, 1: Windows Voice Activation -**/ - UINT32 DspPpModuleMask; - -/** Offset 0x00AA - Enable High Precision Timer - Enable/Disable Hpet. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Hpet; - -/** Offset 0x00AB - Hpet Valid BDF Value - Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HpetBdfValid; - -/** Offset 0x00AC - Bus Number of Hpet - Completer ID of Bus Number of Hpet. Default = 0xFA(Default). -**/ - UINT8 HpetBusNumber; - -/** Offset 0x00AD - Device Number of Hpet - Completer ID of Device Number of Hpet. 0x1F(Default). -**/ - UINT8 HpetDeviceNumber; - -/** Offset 0x00AE - Function Number of Hpet - Completer ID of Function Number of Hpet. 0x00(Default). -**/ - UINT8 HpetFunctionNumber; - -/** Offset 0x00AF -**/ - UINT32 UnusedUpdSpace1; - -/** Offset 0x00B3 - IoApic Valid BDF Value - Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 IoApicBdfValid; - -/** Offset 0x00B4 - Bus Number of IoApic - Completer ID of Bus Number of IoApic. 0xFA(Default). -**/ - UINT8 IoApicBusNumber; - -/** Offset 0x00B5 - Device Number of IoApic - Completer ID of Device Number of IoApic. 0x0F(Default). -**/ - UINT8 IoApicDeviceNumber; - -/** Offset 0x00B6 - Function Number of IoApic - Completer ID of Function Number of IoApic. 0x00(Default). -**/ - UINT8 IoApicFunctionNumber; - -/** Offset 0x00B7 - IOAPIC Entry 24-119 - Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IoApicEntry24_119; - -/** Offset 0x00B8 - IO APIC ID - This member determines IOAPIC ID. 0x01(Default). -**/ - UINT8 IoApicId; - -/** Offset 0x00B9 - IoApic Range - Define address bits 19:12 for the IOxAPIC range. 0x00(Default). -**/ - UINT8 IoApicRangeSelect; - -/** Offset 0x00BA - ISH Controller - Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IshEnable; - -/** Offset 0x00BB - BIOS Interface Lock Down - Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control - Register. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 BiosInterface; - -/** Offset 0x00BC - Bios LockDown Enable - Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 BiosLock; - -/** Offset 0x00BD - SPI EISS Status - Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SpiEiss; - -/** Offset 0x00BE - BiosLock SWSMI Number - This member describes the SwSmi value for Bios Lock. 0xA9(Default). -**/ - UINT8 BiosLockSwSmiNumber; - -/** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable - Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 LPSS_S0ixEnable; - -/** Offset 0x00C0 - LPSS I2C Clock Gating Configuration - Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 I2cClkGateCfg[8]; - -/** Offset 0x00C8 - PSS HSUART Clock Gating Configuration - Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 HsuartClkGateCfg[4]; - -/** Offset 0x00CC - LPSS SPI Clock Gating Configuration - Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 SpiClkGateCfg[3]; - -/** Offset 0x00CF - I2C Device 0 - Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c0Enable; - -/** Offset 0x00D0 - I2C Device 1 - Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c1Enable; - -/** Offset 0x00D1 - I2C Device 2 - Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c2Enable; - -/** Offset 0x00D2 - I2C Device 3 - Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c3Enable; - -/** Offset 0x00D3 - I2C Device 4 - Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c4Enable; - -/** Offset 0x00D4 - I2C Device 5 - Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c5Enable; - -/** Offset 0x00D5 - I2C Device 6 - Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c6Enable; - -/** Offset 0x00D6 - I2C Device 7 - Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c7Enable; - -/** Offset 0x00D7 - UART Device 0 - Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart0Enable; - -/** Offset 0x00D8 - UART Device 1 - Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart1Enable; - -/** Offset 0x00D9 - UART Device 2 - Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart2Enable; - -/** Offset 0x00DA - UART Device 3 - Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart3Enable; - -/** Offset 0x00DB - SPI UART Device 0 - Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi0Enable; - -/** Offset 0x00DC - SPI UART Device 1 - Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi1Enable; - -/** Offset 0x00DD - SPI UART Device 2 - Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi2Enable; - -/** Offset 0x00DE - UART Debug Base Address - UART Debug Base Address. 0x00000000(Default). -**/ - UINT32 Uart2KernelDebugBaseAddress; - -/** Offset 0x00E2 - OS Debug Feature - Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. - $EN_DIS -**/ - UINT8 OsDbgEnable; - -/** Offset 0x00E3 - DCI Feature - Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable. - $EN_DIS -**/ - UINT8 DciEn; - -/** Offset 0x00E4 - Enable PCIE Clock Gating - Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). - 0:Enable, 1:Disable -**/ - UINT8 PcieClockGatingDisabled; - -/** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode - Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PcieRootPort8xhDecode; - -/** Offset 0x00E6 - PCIE 8xh Decode Port Index - PCIE 8xh Decode Port Index. 0x00(Default). -**/ - UINT8 Pcie8xhDecodePortIndex; - -/** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write - Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PcieRootPortPeerMemoryWriteEnable; - -/** Offset 0x00E8 - PCIE SWSMI Number - This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). -**/ - UINT8 PcieAspmSwSmiNumber; - -/** Offset 0x00E9 - PCI Express Root Port - Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRootPortEn[6]; - -/** Offset 0x00EF - Hide PCIE Root Port Configuration Space - Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpHide[6]; - -/** Offset 0x00F5 - PCIE Root Port Slot Implement - Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpSlotImplemented[6]; - -/** Offset 0x00FB - Hot Plug - PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpHotPlug[6]; - -/** Offset 0x0101 - PCIE PM SCI - Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpPmSci[6]; - -/** Offset 0x0107 - PCIE Root Port Extended Sync - Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpExtSync[6]; - -/** Offset 0x010D - Transmitter Half Swing - Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpTransmitterHalfSwing[6]; - -/** Offset 0x0113 - ACS - Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpAcsEnabled[6]; - -/** Offset 0x0119 - Clock Request Support - Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpClkReqSupported[6]; - -/** Offset 0x011F - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, - 0x01, 0x02, 0x03. -**/ - UINT8 PcieRpClkReqNumber[6]; - -/** Offset 0x0125 - CLKREQ# Detection - Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. -**/ - UINT8 PcieRpClkReqDetect[6]; - -/** Offset 0x012B - Advanced Error Reporting - Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. -**/ - UINT8 AdvancedErrorReporting[6]; - -/** Offset 0x0131 - PME Interrupt - Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. -**/ - UINT8 PmeInterrupt[6]; - -/** Offset 0x0137 - URR - PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 UnsupportedRequestReport[6]; - -/** Offset 0x013D - FER - PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 FatalErrorReport[6]; - -/** Offset 0x0143 - NFER - PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 NoFatalErrorReport[6]; - -/** Offset 0x0149 - CER - PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 CorrectableErrorReport[6]; - -/** Offset 0x014F - SEFE - Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnFatalError[6]; - -/** Offset 0x0155 - SENFE - Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnNonFatalError[6]; - -/** Offset 0x015B - SECE - Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnCorrectableError[6]; - -/** Offset 0x0161 - PCIe Speed - Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. -**/ - UINT8 PcieRpSpeed[6]; - -/** Offset 0x0167 - Physical Slot Number - Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. -**/ - UINT8 PhysicalSlotNumber[6]; - -/** Offset 0x016D - CTO - Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpCompletionTimeout[6]; - -/** Offset 0x0173 - PTM Support - Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. -**/ - UINT8 PtmEnable[6]; - -/** Offset 0x0179 - ASPM - PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, - 4:Auto(Default). -**/ - UINT8 PcieRpAspm[6]; - -/** Offset 0x017F - L1 Substates - PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). -**/ - UINT8 PcieRpL1Substates[6]; - -/** Offset 0x0185 - PCH PCIe LTR - PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpLtrEnable[6]; - -/** Offset 0x018B - PCIE LTR Lock - PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpLtrConfigLock[6]; - -/** Offset 0x0191 - PME_B0_S5 Disable bit - PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PmeB0S5Dis; - -/** Offset 0x0192 - PCI Clock Run - This member describes whether or not the PCI ClockRun feature of SC should be enabled. - 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PciClockRun; - -/** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting - Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 Timer8254ClkSetting; - -/** Offset 0x0194 - Chipset SATA - Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports - the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableSata; - -/** Offset 0x0195 - SATA Mode Selection - Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x0196 - Aggressive LPM Support - Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x0197 - SATA Power Optimization - Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x0198 - eSATA Speed Limit - Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 eSATASpeedLimit; - -/** Offset 0x0199 - SATA Speed Limit - SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). - 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) -**/ - UINT8 SpeedLimit; - -/** Offset 0x019A - SATA Port - Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). -**/ - UINT8 SataPortsEnable[2]; - -/** Offset 0x019C - SATA Port DevSlp - Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsDevSlp[2]; - -/** Offset 0x019E - SATA Port HotPlug - Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsHotPlug[2]; - -/** Offset 0x01A0 - Mechanical Presence Switch - Controls reporting if this port has an Mechanical Presence Switch.\n - Note:Requires hardware support. 0:Disable, 1:Enable(Default). -**/ - UINT8 SataPortsInterlockSw[2]; - -/** Offset 0x01A2 - External SATA Ports - Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsExternal[2]; - -/** Offset 0x01A4 - Spin Up Device - Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsSpinUp[2]; - -/** Offset 0x01A6 - SATA Solid State - Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard - Disk Drive(Default), 1:Solid State Drive. -**/ - UINT8 SataPortsSolidStateDrive[2]; - -/** Offset 0x01A8 - DITO Configuration - Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsEnableDitoConfig[2]; - -/** Offset 0x01AA - DM Value - DM Value. 0:Minimum, 0x0F:Maximum(Default). -**/ - UINT8 SataPortsDmVal[2]; - -/** Offset 0x01AC - DITO Value - DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). -**/ - UINT16 SataPortsDitoVal[2]; - -/** Offset 0x01B0 - Subsystem Vendor ID - Subsystem Vendor ID. 0x8086(Default). -**/ - UINT16 SubSystemVendorId; - -/** Offset 0x01B2 - Subsystem ID - Subsystem ID. 0x7270(Default). -**/ - UINT16 SubSystemId; - -/** Offset 0x01B4 -**/ - UINT8 UnusedUpdSpace2[10]; - -/** Offset 0x01BE - CRIDSettings - PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. -**/ - UINT8 CRIDSettings; - -/** Offset 0x01BF - ResetSelect - ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. -**/ - UINT8 ResetSelect; - -/** Offset 0x01C0 - SD Card Support (D27:F0) - Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SdcardEnabled; - -/** Offset 0x01C1 - SeMMC Support (D28:F0) - Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 eMMCEnabled; - -/** Offset 0x01C2 - eMMC Max Speed - Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. - 0:HS400, 1: HS200, 2:DDR50 -**/ - UINT8 eMMCHostMaxSpeed; - -/** Offset 0x01C3 - UFS Support (D29:F0) - Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 UfsEnabled; - -/** Offset 0x01C4 - SDIO Support (D30:F0) - Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SdioEnabled; - -/** Offset 0x01C5 - GPP Lock Feature - Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GppLock; - -/** Offset 0x01C6 - Serial IRQ - Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SirqEnable; - -/** Offset 0x01C7 - Serial IRQ Mode - Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. - $EN_DIS -**/ - UINT8 SirqMode; - -/** Offset 0x01C8 - Start Frame Pulse Width - Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. - 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk -**/ - UINT8 StartFramePulse; - -/** Offset 0x01C9 - Enable SMBus - Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x01CA - SMBus ARP Support - Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ArpEnable; - -/** Offset 0x01CB -**/ - UINT16 UnusedUpdSpace3; - -/** Offset 0x01CD - SMBus Table Elements - The number of elements in the Reserved SMBus Address Table. 0x0080(Default). -**/ - UINT16 NumRsvdSmbusAddresses; - -/** Offset 0x01CF - Reserved SMBus Address Table - Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). -**/ - UINT8 RsvdSmbusAddressTable[128]; - -/** Offset 0x024F - XHCI Disable Compliance Mode - Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance - Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. - $EN_DIS -**/ - UINT8 DisableComplianceMode; - -/** Offset 0x0250 - USB Per-Port Control - Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UsbPerPortCtl; - -/** Offset 0x0251 - xHCI Mode - Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Usb30Mode; - -/** Offset 0x0252 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. 0x01(Default). -**/ - UINT8 PortUsb20Enable[8]; - -/** Offset 0x025A - USB20 Over Current Pin - Over Current Pin number of USB 2.0 Port. 0x00(Default). -**/ - UINT8 PortUs20bOverCurrentPin[8]; - -/** Offset 0x0262 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. 0x01(Default). -**/ - UINT8 PortUsb30Enable[6]; - -/** Offset 0x0268 - USB20 Over Current Pin - Over Current Pin number of USB 3.0 Port. 0x01(Default). -**/ - UINT8 PortUs30bOverCurrentPin[6]; - -/** Offset 0x026E - XDCI Support - Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. - 0:Disable, 1:PCI_Mode, 2:ACPI_mode -**/ - UINT8 UsbOtg; - -/** Offset 0x026F - Enable XHCI HSIC Support - Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HsicSupportEnable; - -/** Offset 0x0270 - Enable XHCI SSIC Support - Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for - port1. 0x00(Default). -**/ - UINT8 SsicPortEnable[2]; - -/** Offset 0x0272 - SSIC Dlane PowerGating - Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT16 DlanePwrGating; - -/** Offset 0x0274 - VT-d - Enable/Disable VT-d. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 VtdEnable; - -/** Offset 0x0275 - HDAudio Delay Timer - The delay timer after Azalia reset. 0x012C(Default). -**/ - UINT16 ResetWaitTimer; - -/** Offset 0x0277 - SMI Lock bit - Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, - 1:Enable(Default). - $EN_DIS -**/ - UINT8 LockDownGlobalSmi; - -/** Offset 0x0278 - RTC Lock Bits - Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 RtcLock; - -/** Offset 0x0279 - XHCI SSIC RATE - Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. -**/ - UINT8 SsicRate[2]; - -/** Offset 0x027B - SATA Test Mode Selection - Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x027C - SMBus Dynamic Power Gating - Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT16 DynamicPowerGating; - -/** Offset 0x027E - Max Snoop Latency - Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). -**/ - UINT16 PcieRpLtrMaxSnoopLatency[6]; - -/** Offset 0x028A - Snoop Latency Override - Snoop Latency Override for PCH PCIE. \n - Disabled:Disable override.\n - Manual:Manually enter override values.\n - Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[6]; - -/** Offset 0x0290 - Snoop Latency Value - LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[6]; - -/** Offset 0x029C - Snoop Latency Multiplier - LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, - 4:1048576ns, 5:33554432ns. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[6]; - -/** Offset 0x02A2 - Max Non-Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). -**/ - UINT16 PcieRpLtrMaxNonSnoopLatency[6]; - -/** Offset 0x02AE - Non Snoop Latency Override - Non Snoop Latency Override for PCH PCIE. \n - Disabled:Disable override.\n - Manual:Manually enter override values.\n - Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[6]; - -/** Offset 0x02B4 - Non Snoop Latency Value - LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[6]; - -/** Offset 0x02C0 - Non Snoop Latency Multiplier - LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), - 3:32768ns, 4:1048576ns, 5:33554432ns. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6]; - -/** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale - Specifies scale used for slot power limit value. 0x00(Default). -**/ - UINT8 PcieRpSlotPowerLimitScale[6]; - -/** Offset 0x02CC - PCIE Root Port Slot Power Limit Value - Specifies upper limit on power supplie by slot. 0x00(Default). -**/ - UINT8 PcieRpSlotPowerLimitValue[6]; - -/** Offset 0x02D2 - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize(Default), 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x02D3 - DCI Auto Detect - Enable/disable DCI AUTO mode. Enabled(Default). - $EN_DIS -**/ - UINT8 DciAutoDetect; - -/** Offset 0x02D4 - Halt and Lock TCO Timer - Halt and Lock the TCO Timer (Watchdog). - 0:No, 1:Yes (default) -**/ - UINT8 TcoTimerHaltLock; - -/** Offset 0x02D5 - Power Button Override Period - specifies how long will PMC wait before initiating a global reset. 000b-4s(default), - 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) - 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s -**/ - UINT8 PwrBtnOverridePeriod; - -/** Offset 0x02D6 - Power Button Native Mode Disable - Disable power button native mode, when 1, this will result in the PMC logic constantly - seeing the power button as de-asserted. 0 (default)) - $EN_DIS -**/ - UINT8 DisableNativePowerButton; - -/** Offset 0x02D7 - Power Button Debounce Mode - Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default) - $EN_DIS -**/ - UINT8 PowerButterDebounceMode; - -/** Offset 0x02D8 - SDIO_TX_CMD_DLL_CNTL - SDIO_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 SdioTxCmdCntl; - -/** Offset 0x02DC - SDIO_TX_DATA_DLL_CNTL1 - SDIO_TX_DATA_DLL_CNTL1. 0xE(Default). -**/ - UINT32 SdioTxDataCntl1; - -/** Offset 0x02E0 - SDIO_TX_DATA_DLL_CNTL2 - SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default). -**/ - UINT32 SdioTxDataCntl2; - -/** Offset 0x02E4 - SDIO_RX_CMD_DATA_DLL_CNTL1 - SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default). -**/ - UINT32 SdioRxCmdDataCntl1; - -/** Offset 0x02E8 - SDIO_RX_CMD_DATA_DLL_CNTL2 - SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). -**/ - UINT32 SdioRxCmdDataCntl2; - -/** Offset 0x02EC - SDCARD_TX_CMD_DLL_CNTL - SDCARD_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 SdcardTxCmdCntl; - -/** Offset 0x02F0 - SDCARD_TX_DATA_DLL_CNTL1 - SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default). -**/ - UINT32 SdcardTxDataCntl1; - -/** Offset 0x02F4 - SDCARD_TX_DATA_DLL_CNTL2 - SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default). -**/ - UINT32 SdcardTxDataCntl2; - -/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL1 - SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default). -**/ - UINT32 SdcardRxCmdDataCntl1; - -/** Offset 0x02FC - SDCARD_RX_STROBE_DLL_CNTL - SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default). -**/ - UINT32 SdcardRxStrobeCntl; - -/** Offset 0x0300 - SDCARD_RX_CMD_DATA_DLL_CNTL2 - SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). -**/ - UINT32 SdcardRxCmdDataCntl2; - -/** Offset 0x0304 - EMMC_TX_CMD_DLL_CNTL - EMMC_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 EmmcTxCmdCntl; - -/** Offset 0x0308 - EMMC_TX_DATA_DLL_CNTL1 - EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default). -**/ - UINT32 EmmcTxDataCntl1; - -/** Offset 0x030C - EMMC_TX_DATA_DLL_CNTL2 - EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default). -**/ - UINT32 EmmcTxDataCntl2; - -/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL1 - EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default). -**/ - UINT32 EmmcRxCmdDataCntl1; - -/** Offset 0x0314 - EMMC_RX_STROBE_DLL_CNTL - EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default). -**/ - UINT32 EmmcRxStrobeCntl; - -/** Offset 0x0318 - EMMC_RX_CMD_DATA_DLL_CNTL2 - EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default). -**/ - UINT32 EmmcRxCmdDataCntl2; - -/** Offset 0x031C - EMMC_MASTER_DLL_CNTL - EMMC_MASTER_DLL_CNTL. 0x001(Default). -**/ - UINT32 EmmcMasterSwCntl; - -/** Offset 0x0320 - PCIe Selectable De-emphasis - When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis - for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpSelectableDeemphasis[6]; - -/** Offset 0x0326 -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x0327 - Monitor Mwait Enable - Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux - based OS, this should be Disabled. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x0328 -**/ - UINT8 ReservedFspsUpd[8]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x0330 -**/ - UINT32 Signature; - -/** Offset 0x0334 -**/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; - -/** Fsp S Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0340 -**/ - UINT32 Signature; - -/** Offset 0x0344 -**/ - UINT8 ReservedFspsRestrictedUpd[12]; -} FSP_S_RESTRICTED_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x0330 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0340 -**/ - FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; - -/** Offset 0x0350 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack(pop) - -#endif diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 5561363..f7a68d7 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -18,7 +18,7 @@ #include <stddef.h> #include <stdint.h> -#include <soc/fsp/FspmUpd.h> +#include <FspmUpd.h> /* * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 7a19e69..7f31247 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -19,7 +19,7 @@ #include <smbios.h> #include <soc/meminit.h> #include <stddef.h> /* required for FspmUpd.h */ -#include <soc/fsp/FspmUpd.h> +#include <FspmUpd.h> #include <string.h> static void set_lpddr4_defaults(FSP_M_CONFIG *cfg) diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h new file mode 100644 index 0000000..a7114ce --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(push, 1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h new file mode 100644 index 0000000..48225e0 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h @@ -0,0 +1,721 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +#define MAX_CHANNELS_NUM 4 +#define MAX_DIMMS_NUM 1 + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + UINT8 ModulePartNum[20]; +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT8 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT16 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Debug Serial Port Base address + Debug serial port base address. This option will be used only when the 'Serial Port + Debug Device' option is set to 'External Device'. 0x00000000(Default). +**/ + UINT32 SerialDebugPortAddress; + +/** Offset 0x0044 - Debug Serial Port Type + 16550 compatible debug serial port resource type. NONE means no serial port support. + 0x02:MMIO(Default). + 0:NONE, 1:I/O, 2:MMIO +**/ + UINT8 SerialDebugPortType; + +/** Offset 0x0045 - Serial Port Debug Device + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port + Base' options will be ignored. 0x02:SOC UART2(Default). + 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device +**/ + UINT8 SerialDebugPortDevice; + +/** Offset 0x0046 - Debug Serial Port Stride Size + Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). + 0:1, 2:4 +**/ + UINT8 SerialDebugPortStrideSize; + +/** Offset 0x0047 - Memory Fast Boot + Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x0048 - Integrated Graphics Device + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video + Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). + $EN_DIS +**/ + UINT8 Igd; + +/** Offset 0x0049 - DVMT Pre-Allocated + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal + Graphics Device. 0x02:64 MB(Default). + 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 + MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, + 0x0F:480 MB, 0x10:512 MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x004A - Aperture Size + Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), + 0x2:256 MB, 0x3:512 MB. + 0x1:128 MB, 0x2:256 MB, 0x3:512 MB +**/ + UINT8 IgdApertureSize; + +/** Offset 0x004B - GTT Size + Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 + MB(Default). + 0x1:2 MB, 0x2:4 MB, 0x3:8 MB +**/ + UINT8 GttSize; + +/** Offset 0x004C - Primary Display + Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), + 0x2:IGD, 0x3:PCI + 0x0:AUTO, 0x2:IGD, 0x3:PCI +**/ + UINT8 PrimaryVideoAdaptor; + +/** Offset 0x004D - Package + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L + is being used. 0x00(Default). + 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD +**/ + UINT8 Package; + +/** Offset 0x004E - Profile + Profile list. 0x19(Default). + 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, + 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, + 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, + 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, + 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, + 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, + 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, + 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, + 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, + 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, + 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, + 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 +**/ + UINT8 Profile; + +/** Offset 0x004F - MemoryDown + Memory Down. 0x0(Default). + 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 +**/ + UINT8 MemoryDown; + +/** Offset 0x0050 - DDR3LPageSize + NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB. + 0x1:1KB, 0x2:2KB +**/ + UINT8 DDR3LPageSize; + +/** Offset 0x0051 - DDR3LASR + NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported. + 0x0:Not Supported, 0x1:Supported +**/ + UINT8 DDR3LASR; + +/** Offset 0x0052 - ScramblerSupport + Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default). + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x0053 - ChannelHashMask + Channel Hash Mask. 0x00(Default). +**/ + UINT16 ChannelHashMask; + +/** Offset 0x0055 - SliceHashMask + Slice Hash Mask. 0x00(Default). +**/ + UINT16 SliceHashMask; + +/** Offset 0x0057 - InterleavedMode + Interleaved Mode. 0x00:Disable(Default), 0x02:Enable. + 0x0:Disable, 0x2:Enable +**/ + UINT8 InterleavedMode; + +/** Offset 0x0058 - ChannelsSlicesEnable + Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 ChannelsSlicesEnable; + +/** Offset 0x0059 - MinRefRate2xEnable + Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), + 0x01:Enable. + $EN_DIS +**/ + UINT8 MinRefRate2xEnable; + +/** Offset 0x005A - DualRankSupportEnable + Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). + $EN_DIS +**/ + UINT8 DualRankSupportEnable; + +/** Offset 0x005B - RmtMode + Rank Margin Tool Mode. 0x00(Default). + $EN_DIS +**/ + UINT8 RmtMode; + +/** Offset 0x005C - MemorySizeLimit + Memory Size Limit: This value is used to restrict the total amount of memory and + the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, + 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) +**/ + UINT16 MemorySizeLimit; + +/** Offset 0x005E - LowMemoryMaxValue + Low Memory Max Value: This value is used to restrict the amount of memory below + 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 + = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). +**/ + UINT16 LowMemoryMaxValue; + +/** Offset 0x0060 - DisableFastBoot + 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train + of memory. + $EN_DIS +**/ + UINT8 DisableFastBoot; + +/** Offset 0x0061 - HighMemoryMaxValue + High Memory Max Value: This value is used to restrict the amount of memory above + 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, + 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). +**/ + UINT16 HighMemoryMaxValue; + +/** Offset 0x0063 - DIMM0SPDAddress + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). +**/ + UINT8 DIMM0SPDAddress; + +/** Offset 0x0064 - DIMM1SPDAddress + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). +**/ + UINT8 DIMM1SPDAddress; + +/** Offset 0x0065 - Ch0_RankEnable + NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default). +**/ + UINT8 Ch0_RankEnable; + +/** Offset 0x0066 - Ch0_DeviceWidth + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + UINT8 Ch0_DeviceWidth; + +/** Offset 0x0067 - Ch0_DramDensity + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + UINT8 Ch0_DramDensity; + +/** Offset 0x0068 - Ch0_Option + Rank Select Interleaving Enable. See Address Mapping section for full description. + 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank + Address Hashing Enable. See Address Mapping section for full description. 0:Bank + Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] + This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). + 0x03(Default). +**/ + UINT8 Ch0_Option; + +/** Offset 0x0069 - Ch0_OdtConfig + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. +**/ + UINT8 Ch0_OdtConfig; + +/** Offset 0x006A - Ch0_TristateClk1 + Parameter used to determine whether to tristate CLK1. 0x00(Default). +**/ + UINT8 Ch0_TristateClk1; + +/** Offset 0x006B - Ch0_Mode2N + 2N Mode. 0x00(Default). +**/ + UINT8 Ch0_Mode2N; + +/** Offset 0x006C - Ch0_OdtLevels + Rank Select Interleaving Enable. See Address Mapping section for full description. + 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. + [1] Bank Address Hashing Enable. See Address Mapping section for full description. + 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). +**/ + UINT8 Ch0_OdtLevels; + +/** Offset 0x006D - Ch1_RankEnable + NOTE: Only for memory down. Set to 1 to enable Ch1 rank. +**/ + UINT8 Ch1_RankEnable; + +/** Offset 0x006E - Ch1_DeviceWidth + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + UINT8 Ch1_DeviceWidth; + +/** Offset 0x006F - Ch1_DramDensity + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default). + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + UINT8 Ch1_DramDensity; + +/** Offset 0x0070 - Ch1_Option + Rank Select Interleaving Enable. See Address Mapping section for full description. + 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] + Bank Address Hashing Enable. See Address Mapping section for full description. + 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB + (B), 0x03(Default). +**/ + UINT8 Ch1_Option; + +/** Offset 0x0071 - Ch1_OdtConfig + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. +**/ + UINT8 Ch1_OdtConfig; + +/** Offset 0x0072 - Ch1_TristateClk1 + Parameter used to determine whether to tristate CLK1. 0x00(Default). +**/ + UINT8 Ch1_TristateClk1; + +/** Offset 0x0073 - Ch1_Mode2N + 2N Mode. 0x00(Default). +**/ + UINT8 Ch1_Mode2N; + +/** Offset 0x0074 - Ch1_OdtLevels + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), + 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. +**/ + UINT8 Ch1_OdtLevels; + +/** Offset 0x0075 - Ch2_RankEnable + NOTE: Only for memory down. Set to 1 to enable Ch2 rank. +**/ + UINT8 Ch2_RankEnable; + +/** Offset 0x0076 - Ch2_DeviceWidth + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + UINT8 Ch2_DeviceWidth; + +/** Offset 0x0077 - Ch2_DramDensity + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + UINT8 Ch2_DramDensity; + +/** Offset 0x0078 - Ch2_Option + Rank Select Interleaving Enable. See Address Mapping section for full description.. + 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] + Bank Address Hashing Enable. See Address Mapping section for full description.. + 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). + 01:2KB (B). +**/ + UINT8 Ch2_Option; + +/** Offset 0x0079 - Ch2_OdtConfig + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. +**/ + UINT8 Ch2_OdtConfig; + +/** Offset 0x007A - Ch2_TristateClk1 + Parameter used to determine whether to tristate CLK1. 0x00(Default). +**/ + UINT8 Ch2_TristateClk1; + +/** Offset 0x007B - Ch2_Mode2N + 2N Mode. 0x00(Default). +**/ + UINT8 Ch2_Mode2N; + +/** Offset 0x007C - Ch2_OdtLevels + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), + 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. +**/ + UINT8 Ch2_OdtLevels; + +/** Offset 0x007D - Ch3_RankEnable + NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default). +**/ + UINT8 Ch3_RankEnable; + +/** Offset 0x007E - Ch3_DeviceWidth + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), + 0x01:x16, 0x02:x32, 0x03:x64. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + UINT8 Ch3_DeviceWidth; + +/** Offset 0x007F - Ch3_DramDensity + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), + 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + UINT8 Ch3_DramDensity; + +/** Offset 0x0080 - Ch3_Option + Rank Select Interleaving Enable. See Address Mapping section for full description.. + 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] + Bank Address Hashing Enable. See Address Mapping section for full description.. + 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 + - 2KB (B). +**/ + UINT8 Ch3_Option; + +/** Offset 0x0081 - Ch3_OdtConfig + ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG. +**/ + UINT8 Ch3_OdtConfig; + +/** Offset 0x0082 - Ch3_TristateClk1 + Parameter used to determine whether to tristate CLK1. 0x00(Default). +**/ + UINT8 Ch3_TristateClk1; + +/** Offset 0x0083 - Ch3_Mode2N + 2N Mode. 0x00(Default). +**/ + UINT8 Ch3_Mode2N; + +/** Offset 0x0084 - Ch3_OdtLevels + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), + 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. +**/ + UINT8 Ch3_OdtLevels; + +/** Offset 0x0085 - RmtCheckRun + RmtCheckRun: 0x00(Default). +**/ + UINT8 RmtCheckRun; + +/** Offset 0x0086 - Ch0_Bit_swizzling + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + UINT8 Ch0_Bit_swizzling[32]; + +/** Offset 0x00A6 - Ch1_Bit_swizzling + Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + UINT8 Ch1_Bit_swizzling[32]; + +/** Offset 0x00C6 - Ch2_Bit_swizzling + Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + UINT8 Ch2_Bit_swizzling[32]; + +/** Offset 0x00E6 - Ch3_Bit_swizzling + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + UINT8 Ch3_Bit_swizzling[32]; + +/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold + RmtMarginCheckScaleHighThreshold. 0x0000(Default). +**/ + UINT16 RmtMarginCheckScaleHighThreshold; + +/** Offset 0x0108 - MsgLevelMask + MsgLevelMask. 0x00000000(Default). +**/ + UINT32 MsgLevelMask; + +/** Offset 0x010C +**/ + UINT32 UnusedUpdSpace0; + +/** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4 + Number of Entries in PreMem GPIO Table. 0(Default). +**/ + UINT8 PreMemGpioTableEntryNum; + +/** Offset 0x0111 - PreMem GPIO Pin Number for each table + Number of Pins in each PreMem GPIO Table. 0(Default). +**/ + UINT8 PreMemGpioTablePinNum[4]; + +/** Offset 0x0115 - PreMem GPIO Table Pointer + Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default). +**/ + UINT32 PreMemGpioTablePtr; + +/** Offset 0x0119 - Enhance the port 8xh decoding + Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 EnhancePort8xhDecoding; + +/** Offset 0x011A - OEM File Loading Address + Determine the memory base address to load a specified file from CSE file system + after memory is available. +**/ + UINT32 OemLoadingBase; + +/** Offset 0x011E - OEM File Name to Load + Specify a file name to load from CSE file system after memory is available. Empty + indicates no file needs to be loaded. +**/ + UINT8 OemFileName[16]; + +/** Offset 0x012E - SPD Data Write + Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 SpdWriteEnable; + +/** Offset 0x012F - MRC Training Data Saving + Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 MrcDataSaving; + +/** Offset 0x0130 - eMMC Trace Length + Select eMMC trace length to load OEM file from when loading OEM file name is specified. + 0x0:Long(Default), 0x1:Short. + 0x0:Long, 0x1:Short +**/ + UINT8 eMMCTraceLen; + +/** Offset 0x0131 +**/ + VOID* MrcBootDataPtr; + +/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB + Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of + CSE. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 SkipCseRbp; + +/** Offset 0x0136 - Npk Enable + Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default). + 0:Disable, 1:Enable, 2:Debugger, 3:Auto +**/ + UINT8 NpkEn; + +/** Offset 0x0137 - FW Trace Enable + Enable/Disable FW Trace. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 FwTraceEn; + +/** Offset 0x0138 - FW Trace Destination + FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB, + 4-NPK_TRACE_TO_PTI(Default). +**/ + UINT8 FwTraceDestination; + +/** Offset 0x0139 - NPK Recovery Dump + Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 RecoverDump; + +/** Offset 0x013A - Memory Region 0 Buffer WrapAround + Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + UINT8 Msc0Wrap; + +/** Offset 0x013B - Memory Region 1 Buffer WrapAround + Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + UINT8 Msc1Wrap; + +/** Offset 0x013C - Memory Region 0 Buffer Size + Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, + 6-512MB, 7-1GB. +**/ + UINT32 Msc0Size; + +/** Offset 0x0140 - Memory Region 1 Buffer Size + Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, + 6-512MB, 7-1GB. +**/ + UINT32 Msc1Size; + +/** Offset 0x0144 - PTI Mode + PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. +**/ + UINT8 PtiMode; + +/** Offset 0x0145 - PTI Training + PTI Training. 0-off(Default), 1-6=1-6. +**/ + UINT8 PtiTraining; + +/** Offset 0x0146 - PTI Speed + PTI Speed. 0-full, 1-half, 2-quarter(Default). +**/ + UINT8 PtiSpeed; + +/** Offset 0x0147 - Punit Message Level + Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. +**/ + UINT8 PunitMlvl; + +/** Offset 0x0148 - PMC Message Level + PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. +**/ + UINT8 PmcMlvl; + +/** Offset 0x0149 - SW Trace Enable + Enable/Disable SW Trace. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 SwTraceEn; + +/** Offset 0x014A - Periodic Retraining Disable + Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 PeriodicRetrainingDisable; + +/** Offset 0x014B +**/ + UINT8 ReservedFspmUpd[5]; +} FSP_M_CONFIG; + +/** Fsp M Test Configuration +**/ +typedef struct { + +/** Offset 0x0150 +**/ + UINT32 Signature; + +/** Offset 0x0154 +**/ + UINT8 ReservedFspmTestUpd[28]; +} FSP_M_TEST_CONFIG; + +/** Fsp M Restricted Configuration +**/ +typedef struct { + +/** Offset 0x0170 +**/ + UINT32 Signature; + +/** Offset 0x0174 +**/ + UINT8 ReservedFspmRestrictedUpd[138]; +} FSP_M_RESTRICTED_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0150 +**/ + FSP_M_TEST_CONFIG FspmTestConfig; + +/** Offset 0x0170 +**/ + FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; + +/** Offset 0x01FE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h new file mode 100644 index 0000000..553eba3 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h @@ -0,0 +1,1541 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - ActiveProcessorCores + Number of active cores. 0:Disable(Default), 1:Enable. +**/ + UINT8 ActiveProcessorCores; + +/** Offset 0x0021 - Disable Core1 + Disable/Enable Core1. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DisableCore1; + +/** Offset 0x0022 - Disable Core2 + Disable/Enable Core2. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DisableCore2; + +/** Offset 0x0023 - Disable Core3 + Disable/Enable Core3. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DisableCore3; + +/** Offset 0x0024 - VMX Enable + Enable or Disable VMX. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x0025 - Memory region allocation for Processor Trace + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to + 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default) +**/ + UINT8 ProcTraceMemSize; + +/** Offset 0x0026 - Enable Processor Trace + Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 ProcTraceEnable; + +/** Offset 0x0027 - Eist + Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x0028 - Boot PState + Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. +**/ + UINT8 BootPState; + +/** Offset 0x0029 - CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 EnableCx; + +/** Offset 0x002A - Enhanced C-states + Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 C1e; + +/** Offset 0x002B - Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 BiProcHot; + +/** Offset 0x002C - Max Pkg Cstate + Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, + 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. +**/ + UINT8 PkgCStateLimit; + +/** Offset 0x002D +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x002E - C-State auto-demotion + C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 + Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion + to C1 and C3. +**/ + UINT8 CStateAutoDemotion; + +/** Offset 0x002F - C-State un-demotion + C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, + 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. +**/ + UINT8 CStateUnDemotion; + +/** Offset 0x0030 - Max Core C-State + Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). +**/ + UINT8 MaxCoreCState; + +/** Offset 0x0031 - Package C-State Demotion + Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PkgCStateDemotion; + +/** Offset 0x0032 - Package C-State Un-demotion + Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PkgCStateUnDemotion; + +/** Offset 0x0033 - Turbo Mode + Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x0034 - SC HDA Verb Table Entry Number + Number of Entries in Verb Table. 0(Default). +**/ + UINT8 HdaVerbTableEntryNum; + +/** Offset 0x0035 - SC HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. 0x00000000(Default). +**/ + UINT32 HdaVerbTablePtr; + +/** Offset 0x0039 - Enable/Disable P2SB device hidden. + Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 P2sbUnhide; + +/** Offset 0x003A - IPU Enable/Disable + Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 IpuEn; + +/** Offset 0x003B - IMGU ACPI mode selection + 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. + 0:Disable, 1:IGFX Child device, 2:ACPI device +**/ + UINT8 IpuAcpiMode; + +/** Offset 0x003C - GttMmAdr + GttMmAdr structure for initialization. 0xBF000000(Default). +**/ + UINT32 GttMmAdr; + +/** Offset 0x0040 - GmAdr + GmAdr structure for initialization. 0xA0000000(Default). +**/ + UINT32 GmAdr; + +/** Offset 0x0044 - Enable ForceWake + Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 ForceWake; + +/** Offset 0x0045 - Enable PavpLock + Enable/disable PavpLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PavpLock; + +/** Offset 0x0046 - Enable GraphicsFreqModify + Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 GraphicsFreqModify; + +/** Offset 0x0047 - Enable GraphicsFreqReq + Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 GraphicsFreqReq; + +/** Offset 0x0048 - Enable GraphicsVideoFreq + Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 GraphicsVideoFreq; + +/** Offset 0x0049 - Enable PmLock + Enable/disable PmLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PmLock; + +/** Offset 0x004A - Enable DopClockGating + Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 DopClockGating; + +/** Offset 0x004B - Enable UnsolicitedAttackOverride + Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 UnsolicitedAttackOverride; + +/** Offset 0x004C - Enable WOPCMSupport + Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 WOPCMSupport; + +/** Offset 0x004D - Enable WOPCMSize + Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 WOPCMSize; + +/** Offset 0x004E - Enable PowerGating + Enable/disable PowerGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PowerGating; + +/** Offset 0x004F - Enable UnitLevelClockGating + Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 UnitLevelClockGating; + +/** Offset 0x0050 - Enable FastBoot + Enable/disable FastBoot. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 FastBoot; + +/** Offset 0x0051 - Enable DynSR + Enable/disable DynSR. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 DynSR; + +/** Offset 0x0052 - Enable SaIpuEnable + Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x0053 - BMP Logo Data Size + BMP logo data buffer size. 0x00000000(Default). +**/ + UINT32 LogoSize; + +/** Offset 0x0057 - BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. 0x00000000(Default). +**/ + UINT32 LogoPtr; + +/** Offset 0x005B - Graphics Configuration Data Pointer + Graphics configuration data used for initialization. 0x00000000(Default). +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x005F - GT PM Support + Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PmSupport; + +/** Offset 0x0060 - RC6(Render Standby) + Enable/Disable render standby support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 EnableRenderStandby; + +/** Offset 0x0061 - PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PavpEnable; + +/** Offset 0x0062 - PAVP PR3 + Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PavpPr3; + +/** Offset 0x0063 - CdClock Frequency selection + 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +**/ + UINT8 CdClock; + +/** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit + Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x0065 - Write Protection Support + Enable/disable Write Protection. 0:Disable, 1:Enable(Default). +**/ + UINT8 WriteProtectionEnable[5]; + +/** Offset 0x006A - Read Protection Support + Enable/disable Read Protection. 0:Disable, 1:Enable(Default). +**/ + UINT8 ReadProtectionEnable[5]; + +/** Offset 0x006F - Protected Range Limitation + The address of the upper limit of protection, 0x0FFFh(Default). +**/ + UINT16 ProtectedRangeLimit[5]; + +/** Offset 0x0079 - Protected Range Base + The base address of the upper limit of protection. 0x0000(Default). +**/ + UINT16 ProtectedRangeBase[5]; + +/** Offset 0x0083 - Enable SC Gaussian Mixture Models + Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 Gmm; + +/** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk + Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingPgcbClkTrunk; + +/** Offset 0x0085 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingSb; + +/** Offset 0x0086 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingSbClkTrunk; + +/** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition + Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingSbClkPartition; + +/** Offset 0x0088 - GMM Clock Gating - Core + Enable/disable Core. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingCore; + +/** Offset 0x0089 - GMM Clock Gating - DMA + Enable/disable DMA. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingDma; + +/** Offset 0x008A - GMM Clock Gating - Register Access + Enable/disable Register Access. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingRegAccess; + +/** Offset 0x008B - GMM Clock Gating - Host + Enable/disable Host. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingHost; + +/** Offset 0x008C - GMM Clock Gating - Partition + Enable/disable Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingPartition; + +/** Offset 0x008D - Clock Gating - Trunk + Enable/disable Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingTrunk; + +/** Offset 0x008E - HD Audio Support + Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 HdaEnable; + +/** Offset 0x008F - HD Audio DSP Support + Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DspEnable; + +/** Offset 0x0090 - Azalia wake-on-ring + Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 Pme; + +/** Offset 0x0091 - HD-Audio I/O Buffer Ownership + Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default) + 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and + I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers +**/ + UINT8 HdAudioIoBufferOwnership; + +/** Offset 0x0092 - HD-Audio I/O Buffer Voltage + HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. + 0: 3.3V, 1: 1.8V +**/ + UINT8 HdAudioIoBufferVoltage; + +/** Offset 0x0093 - HD-Audio Virtual Channel Type + HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. + 0: VC0, 1: VC1 +**/ + UINT8 HdAudioVcType; + +/** Offset 0x0094 - HD-Audio Link Frequency + HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, + 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + UINT8 HdAudioLinkFrequency; + +/** Offset 0x0095 - HD-Audio iDisp-Link Frequency + HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, + 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + UINT8 HdAudioIDispLinkFrequency; + +/** Offset 0x0096 - HD-Audio iDisp-Link T-Mode + HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. + 0: 2T, 1: 1T +**/ + UINT8 HdAudioIDispLinkTmode; + +/** Offset 0x0097 - HD-Audio Disp DMIC + HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. + 0: Disable, 1: 2ch array, 2: 4ch array +**/ + UINT8 DspEndpointDmic; + +/** Offset 0x0098 - HD-Audio Bluetooth + Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DspEndpointBluetooth; + +/** Offset 0x0099 - HD-Audio I2S SHK + Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 DspEndpointI2sSkp; + +/** Offset 0x009A - HD-Audio I2S HP + Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 DspEndpointI2sHp; + +/** Offset 0x009B - HD-Audio Controller Power Gating + Enable/Disable HD-Audio Controller Power Gating. This option is deprecated. + $EN_DIS +**/ + UINT8 AudioCtlPwrGate; + +/** Offset 0x009C - HD-Audio ADSP Power Gating + Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated. + $EN_DIS +**/ + UINT8 AudioDspPwrGate; + +/** Offset 0x009D - HD-Audio CSME Memory Transfers + Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + UINT8 Mmt; + +/** Offset 0x009E - HD-Audio Host Memory Transfers + Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + UINT8 Hmt; + +/** Offset 0x009F - HD-Audio BIOS Configuration Lock Down + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 BiosCfgLockDown; + +/** Offset 0x00A0 - HD-Audio Power Gating + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 HDAudioPwrGate; + +/** Offset 0x00A1 - HD-Audio Clock Gatingn + Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 HDAudioClkGate; + +/** Offset 0x00A2 - Bitmask of DSP Feature + Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] + - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: + Intel WoV, 1: Windows Voice Activation +**/ + UINT32 DspFeatureMask; + +/** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules + Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] + - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: + Intel WoV, 1: Windows Voice Activation +**/ + UINT32 DspPpModuleMask; + +/** Offset 0x00AA - Enable High Precision Timer + Enable/Disable Hpet. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 Hpet; + +/** Offset 0x00AB - Hpet Valid BDF Value + Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 HpetBdfValid; + +/** Offset 0x00AC - Bus Number of Hpet + Completer ID of Bus Number of Hpet. Default = 0xFA(Default). +**/ + UINT8 HpetBusNumber; + +/** Offset 0x00AD - Device Number of Hpet + Completer ID of Device Number of Hpet. 0x1F(Default). +**/ + UINT8 HpetDeviceNumber; + +/** Offset 0x00AE - Function Number of Hpet + Completer ID of Function Number of Hpet. 0x00(Default). +**/ + UINT8 HpetFunctionNumber; + +/** Offset 0x00AF +**/ + UINT32 UnusedUpdSpace1; + +/** Offset 0x00B3 - IoApic Valid BDF Value + Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 IoApicBdfValid; + +/** Offset 0x00B4 - Bus Number of IoApic + Completer ID of Bus Number of IoApic. 0xFA(Default). +**/ + UINT8 IoApicBusNumber; + +/** Offset 0x00B5 - Device Number of IoApic + Completer ID of Device Number of IoApic. 0x0F(Default). +**/ + UINT8 IoApicDeviceNumber; + +/** Offset 0x00B6 - Function Number of IoApic + Completer ID of Function Number of IoApic. 0x00(Default). +**/ + UINT8 IoApicFunctionNumber; + +/** Offset 0x00B7 - IOAPIC Entry 24-119 + Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 IoApicEntry24_119; + +/** Offset 0x00B8 - IO APIC ID + This member determines IOAPIC ID. 0x01(Default). +**/ + UINT8 IoApicId; + +/** Offset 0x00B9 - IoApic Range + Define address bits 19:12 for the IOxAPIC range. 0x00(Default). +**/ + UINT8 IoApicRangeSelect; + +/** Offset 0x00BA - ISH Controller + Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 IshEnable; + +/** Offset 0x00BB - BIOS Interface Lock Down + Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control + Register. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 BiosInterface; + +/** Offset 0x00BC - Bios LockDown Enable + Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 BiosLock; + +/** Offset 0x00BD - SPI EISS Status + Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SpiEiss; + +/** Offset 0x00BE - BiosLock SWSMI Number + This member describes the SwSmi value for Bios Lock. 0xA9(Default). +**/ + UINT8 BiosLockSwSmiNumber; + +/** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable + Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 LPSS_S0ixEnable; + +/** Offset 0x00C0 - LPSS I2C Clock Gating Configuration + Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). +**/ + UINT8 I2cClkGateCfg[8]; + +/** Offset 0x00C8 - PSS HSUART Clock Gating Configuration + Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). +**/ + UINT8 HsuartClkGateCfg[4]; + +/** Offset 0x00CC - LPSS SPI Clock Gating Configuration + Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). +**/ + UINT8 SpiClkGateCfg[3]; + +/** Offset 0x00CF - I2C Device 0 + Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c0Enable; + +/** Offset 0x00D0 - I2C Device 1 + Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c1Enable; + +/** Offset 0x00D1 - I2C Device 2 + Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c2Enable; + +/** Offset 0x00D2 - I2C Device 3 + Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c3Enable; + +/** Offset 0x00D3 - I2C Device 4 + Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c4Enable; + +/** Offset 0x00D4 - I2C Device 5 + Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c5Enable; + +/** Offset 0x00D5 - I2C Device 6 + Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c6Enable; + +/** Offset 0x00D6 - I2C Device 7 + Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c7Enable; + +/** Offset 0x00D7 - UART Device 0 + Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Hsuart0Enable; + +/** Offset 0x00D8 - UART Device 1 + Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Hsuart1Enable; + +/** Offset 0x00D9 - UART Device 2 + Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Hsuart2Enable; + +/** Offset 0x00DA - UART Device 3 + Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Hsuart3Enable; + +/** Offset 0x00DB - SPI UART Device 0 + Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Spi0Enable; + +/** Offset 0x00DC - SPI UART Device 1 + Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Spi1Enable; + +/** Offset 0x00DD - SPI UART Device 2 + Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Spi2Enable; + +/** Offset 0x00DE - UART Debug Base Address + UART Debug Base Address. 0x00000000(Default). +**/ + UINT32 Uart2KernelDebugBaseAddress; + +/** Offset 0x00E2 - OS Debug Feature + Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + UINT8 OsDbgEnable; + +/** Offset 0x00E3 - DCI Feature + Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x00E4 - Enable PCIE Clock Gating + Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). + 0:Enable, 1:Disable +**/ + UINT8 PcieClockGatingDisabled; + +/** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode + Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PcieRootPort8xhDecode; + +/** Offset 0x00E6 - PCIE 8xh Decode Port Index + PCIE 8xh Decode Port Index. 0x00(Default). +**/ + UINT8 Pcie8xhDecodePortIndex; + +/** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write + Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PcieRootPortPeerMemoryWriteEnable; + +/** Offset 0x00E8 - PCIE SWSMI Number + This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). +**/ + UINT8 PcieAspmSwSmiNumber; + +/** Offset 0x00E9 - PCI Express Root Port + Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRootPortEn[6]; + +/** Offset 0x00EF - Hide PCIE Root Port Configuration Space + Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. +**/ + UINT8 PcieRpHide[6]; + +/** Offset 0x00F5 - PCIE Root Port Slot Implement + Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpSlotImplemented[6]; + +/** Offset 0x00FB - Hot Plug + PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpHotPlug[6]; + +/** Offset 0x0101 - PCIE PM SCI + Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. +**/ + UINT8 PcieRpPmSci[6]; + +/** Offset 0x0107 - PCIE Root Port Extended Sync + Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpExtSync[6]; + +/** Offset 0x010D - Transmitter Half Swing + Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpTransmitterHalfSwing[6]; + +/** Offset 0x0113 - ACS + Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpAcsEnabled[6]; + +/** Offset 0x0119 - Clock Request Support + Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpClkReqSupported[6]; + +/** Offset 0x011F - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, + 0x01, 0x02, 0x03. +**/ + UINT8 PcieRpClkReqNumber[6]; + +/** Offset 0x0125 - CLKREQ# Detection + Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. +**/ + UINT8 PcieRpClkReqDetect[6]; + +/** Offset 0x012B - Advanced Error Reporting + Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. +**/ + UINT8 AdvancedErrorReporting[6]; + +/** Offset 0x0131 - PME Interrupt + Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. +**/ + UINT8 PmeInterrupt[6]; + +/** Offset 0x0137 - URR + PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 UnsupportedRequestReport[6]; + +/** Offset 0x013D - FER + PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 FatalErrorReport[6]; + +/** Offset 0x0143 - NFER + PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 NoFatalErrorReport[6]; + +/** Offset 0x0149 - CER + PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 CorrectableErrorReport[6]; + +/** Offset 0x014F - SEFE + Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 SystemErrorOnFatalError[6]; + +/** Offset 0x0155 - SENFE + Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 SystemErrorOnNonFatalError[6]; + +/** Offset 0x015B - SECE + Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 SystemErrorOnCorrectableError[6]; + +/** Offset 0x0161 - PCIe Speed + Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. +**/ + UINT8 PcieRpSpeed[6]; + +/** Offset 0x0167 - Physical Slot Number + Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. +**/ + UINT8 PhysicalSlotNumber[6]; + +/** Offset 0x016D - CTO + Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. +**/ + UINT8 PcieRpCompletionTimeout[6]; + +/** Offset 0x0173 - PTM Support + Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. +**/ + UINT8 PtmEnable[6]; + +/** Offset 0x0179 - ASPM + PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, + 4:Auto(Default). +**/ + UINT8 PcieRpAspm[6]; + +/** Offset 0x017F - L1 Substates + PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). +**/ + UINT8 PcieRpL1Substates[6]; + +/** Offset 0x0185 - PCH PCIe LTR + PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpLtrEnable[6]; + +/** Offset 0x018B - PCIE LTR Lock + PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. +**/ + UINT8 PcieRpLtrConfigLock[6]; + +/** Offset 0x0191 - PME_B0_S5 Disable bit + PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PmeB0S5Dis; + +/** Offset 0x0192 - PCI Clock Run + This member describes whether or not the PCI ClockRun feature of SC should be enabled. + 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PciClockRun; + +/** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting + Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 Timer8254ClkSetting; + +/** Offset 0x0194 - Chipset SATA + Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports + the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 EnableSata; + +/** Offset 0x0195 - SATA Mode Selection + Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x0196 - Aggressive LPM Support + Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0197 - SATA Power Optimization + Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x0198 - eSATA Speed Limit + Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 eSATASpeedLimit; + +/** Offset 0x0199 - SATA Speed Limit + SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). + 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) +**/ + UINT8 SpeedLimit; + +/** Offset 0x019A - SATA Port + Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). +**/ + UINT8 SataPortsEnable[2]; + +/** Offset 0x019C - SATA Port DevSlp + Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsDevSlp[2]; + +/** Offset 0x019E - SATA Port HotPlug + Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsHotPlug[2]; + +/** Offset 0x01A0 - Mechanical Presence Switch + Controls reporting if this port has an Mechanical Presence Switch.\n + Note:Requires hardware support. 0:Disable, 1:Enable(Default). +**/ + UINT8 SataPortsInterlockSw[2]; + +/** Offset 0x01A2 - External SATA Ports + Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsExternal[2]; + +/** Offset 0x01A4 - Spin Up Device + Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsSpinUp[2]; + +/** Offset 0x01A6 - SATA Solid State + Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard + Disk Drive(Default), 1:Solid State Drive. +**/ + UINT8 SataPortsSolidStateDrive[2]; + +/** Offset 0x01A8 - DITO Configuration + Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsEnableDitoConfig[2]; + +/** Offset 0x01AA - DM Value + DM Value. 0:Minimum, 0x0F:Maximum(Default). +**/ + UINT8 SataPortsDmVal[2]; + +/** Offset 0x01AC - DITO Value + DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). +**/ + UINT16 SataPortsDitoVal[2]; + +/** Offset 0x01B0 - Subsystem Vendor ID + Subsystem Vendor ID. 0x8086(Default). +**/ + UINT16 SubSystemVendorId; + +/** Offset 0x01B2 - Subsystem ID + Subsystem ID. 0x7270(Default). +**/ + UINT16 SubSystemId; + +/** Offset 0x01B4 +**/ + UINT8 UnusedUpdSpace2[10]; + +/** Offset 0x01BE - CRIDSettings + PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. +**/ + UINT8 CRIDSettings; + +/** Offset 0x01BF - ResetSelect + ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. +**/ + UINT8 ResetSelect; + +/** Offset 0x01C0 - SD Card Support (D27:F0) + Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SdcardEnabled; + +/** Offset 0x01C1 - SeMMC Support (D28:F0) + Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 eMMCEnabled; + +/** Offset 0x01C2 - eMMC Max Speed + Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. + 0:HS400, 1: HS200, 2:DDR50 +**/ + UINT8 eMMCHostMaxSpeed; + +/** Offset 0x01C3 - UFS Support (D29:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 UfsEnabled; + +/** Offset 0x01C4 - SDIO Support (D30:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SdioEnabled; + +/** Offset 0x01C5 - GPP Lock Feature + Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 GppLock; + +/** Offset 0x01C6 - Serial IRQ + Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SirqEnable; + +/** Offset 0x01C7 - Serial IRQ Mode + Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. + $EN_DIS +**/ + UINT8 SirqMode; + +/** Offset 0x01C8 - Start Frame Pulse Width + Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. + 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk +**/ + UINT8 StartFramePulse; + +/** Offset 0x01C9 - Enable SMBus + Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x01CA - SMBus ARP Support + Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ArpEnable; + +/** Offset 0x01CB +**/ + UINT16 UnusedUpdSpace3; + +/** Offset 0x01CD - SMBus Table Elements + The number of elements in the Reserved SMBus Address Table. 0x0080(Default). +**/ + UINT16 NumRsvdSmbusAddresses; + +/** Offset 0x01CF - Reserved SMBus Address Table + Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). +**/ + UINT8 RsvdSmbusAddressTable[128]; + +/** Offset 0x024F - XHCI Disable Compliance Mode + Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance + Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. + $EN_DIS +**/ + UINT8 DisableComplianceMode; + +/** Offset 0x0250 - USB Per-Port Control + Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 UsbPerPortCtl; + +/** Offset 0x0251 - xHCI Mode + Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 Usb30Mode; + +/** Offset 0x0252 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. 0x01(Default). +**/ + UINT8 PortUsb20Enable[8]; + +/** Offset 0x025A - USB20 Over Current Pin + Over Current Pin number of USB 2.0 Port. 0x00(Default). +**/ + UINT8 PortUs20bOverCurrentPin[8]; + +/** Offset 0x0262 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. 0x01(Default). +**/ + UINT8 PortUsb30Enable[6]; + +/** Offset 0x0268 - USB20 Over Current Pin + Over Current Pin number of USB 3.0 Port. 0x01(Default). +**/ + UINT8 PortUs30bOverCurrentPin[6]; + +/** Offset 0x026E - XDCI Support + Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. + 0:Disable, 1:PCI_Mode, 2:ACPI_mode +**/ + UINT8 UsbOtg; + +/** Offset 0x026F - Enable XHCI HSIC Support + Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 HsicSupportEnable; + +/** Offset 0x0270 - Enable XHCI SSIC Support + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for + port1. 0x00(Default). +**/ + UINT8 SsicPortEnable[2]; + +/** Offset 0x0272 - SSIC Dlane PowerGating + Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT16 DlanePwrGating; + +/** Offset 0x0274 - VT-d + Enable/Disable VT-d. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 VtdEnable; + +/** Offset 0x0275 - HDAudio Delay Timer + The delay timer after Azalia reset. 0x012C(Default). +**/ + UINT16 ResetWaitTimer; + +/** Offset 0x0277 - SMI Lock bit + Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, + 1:Enable(Default). + $EN_DIS +**/ + UINT8 LockDownGlobalSmi; + +/** Offset 0x0278 - RTC Lock Bits + Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 RtcLock; + +/** Offset 0x0279 - XHCI SSIC RATE + Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. +**/ + UINT8 SsicRate[2]; + +/** Offset 0x027B - SATA Test Mode Selection + Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 SataTestMode; + +/** Offset 0x027C - SMBus Dynamic Power Gating + Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT16 DynamicPowerGating; + +/** Offset 0x027E - Max Snoop Latency + Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). +**/ + UINT16 PcieRpLtrMaxSnoopLatency[6]; + +/** Offset 0x028A - Snoop Latency Override + Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). +**/ + UINT8 PcieRpSnoopLatencyOverrideMode[6]; + +/** Offset 0x0290 - Snoop Latency Value + LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + UINT16 PcieRpSnoopLatencyOverrideValue[6]; + +/** Offset 0x029C - Snoop Latency Multiplier + LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, + 4:1048576ns, 5:33554432ns. +**/ + UINT8 PcieRpSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02A2 - Max Non-Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). +**/ + UINT16 PcieRpLtrMaxNonSnoopLatency[6]; + +/** Offset 0x02AE - Non Snoop Latency Override + Non Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMode[6]; + +/** Offset 0x02B4 - Non Snoop Latency Value + LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + UINT16 PcieRpNonSnoopLatencyOverrideValue[6]; + +/** Offset 0x02C0 - Non Snoop Latency Multiplier + LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), + 3:32768ns, 4:1048576ns, 5:33554432ns. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale + Specifies scale used for slot power limit value. 0x00(Default). +**/ + UINT8 PcieRpSlotPowerLimitScale[6]; + +/** Offset 0x02CC - PCIE Root Port Slot Power Limit Value + Specifies upper limit on power supplie by slot. 0x00(Default). +**/ + UINT8 PcieRpSlotPowerLimitValue[6]; + +/** Offset 0x02D2 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize(Default), 1: Skip + $EN_DIS +**/ + UINT8 SkipMpInit; + +/** Offset 0x02D3 - DCI Auto Detect + Enable/disable DCI AUTO mode. Enabled(Default). + $EN_DIS +**/ + UINT8 DciAutoDetect; + +/** Offset 0x02D4 - Halt and Lock TCO Timer + Halt and Lock the TCO Timer (Watchdog). + 0:No, 1:Yes (default) +**/ + UINT8 TcoTimerHaltLock; + +/** Offset 0x02D5 - Power Button Override Period + specifies how long will PMC wait before initiating a global reset. 000b-4s(default), + 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) + 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s +**/ + UINT8 PwrBtnOverridePeriod; + +/** Offset 0x02D6 - Power Button Native Mode Disable + Disable power button native mode, when 1, this will result in the PMC logic constantly + seeing the power button as de-asserted. 0 (default)) + $EN_DIS +**/ + UINT8 DisableNativePowerButton; + +/** Offset 0x02D7 - Power Button Debounce Mode + Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default) + $EN_DIS +**/ + UINT8 PowerButterDebounceMode; + +/** Offset 0x02D8 - SDIO_TX_CMD_DLL_CNTL + SDIO_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + UINT32 SdioTxCmdCntl; + +/** Offset 0x02DC - SDIO_TX_DATA_DLL_CNTL1 + SDIO_TX_DATA_DLL_CNTL1. 0xE(Default). +**/ + UINT32 SdioTxDataCntl1; + +/** Offset 0x02E0 - SDIO_TX_DATA_DLL_CNTL2 + SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default). +**/ + UINT32 SdioTxDataCntl2; + +/** Offset 0x02E4 - SDIO_RX_CMD_DATA_DLL_CNTL1 + SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default). +**/ + UINT32 SdioRxCmdDataCntl1; + +/** Offset 0x02E8 - SDIO_RX_CMD_DATA_DLL_CNTL2 + SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). +**/ + UINT32 SdioRxCmdDataCntl2; + +/** Offset 0x02EC - SDCARD_TX_CMD_DLL_CNTL + SDCARD_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + UINT32 SdcardTxCmdCntl; + +/** Offset 0x02F0 - SDCARD_TX_DATA_DLL_CNTL1 + SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default). +**/ + UINT32 SdcardTxDataCntl1; + +/** Offset 0x02F4 - SDCARD_TX_DATA_DLL_CNTL2 + SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default). +**/ + UINT32 SdcardTxDataCntl2; + +/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL1 + SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default). +**/ + UINT32 SdcardRxCmdDataCntl1; + +/** Offset 0x02FC - SDCARD_RX_STROBE_DLL_CNTL + SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default). +**/ + UINT32 SdcardRxStrobeCntl; + +/** Offset 0x0300 - SDCARD_RX_CMD_DATA_DLL_CNTL2 + SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). +**/ + UINT32 SdcardRxCmdDataCntl2; + +/** Offset 0x0304 - EMMC_TX_CMD_DLL_CNTL + EMMC_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + UINT32 EmmcTxCmdCntl; + +/** Offset 0x0308 - EMMC_TX_DATA_DLL_CNTL1 + EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default). +**/ + UINT32 EmmcTxDataCntl1; + +/** Offset 0x030C - EMMC_TX_DATA_DLL_CNTL2 + EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default). +**/ + UINT32 EmmcTxDataCntl2; + +/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL1 + EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default). +**/ + UINT32 EmmcRxCmdDataCntl1; + +/** Offset 0x0314 - EMMC_RX_STROBE_DLL_CNTL + EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default). +**/ + UINT32 EmmcRxStrobeCntl; + +/** Offset 0x0318 - EMMC_RX_CMD_DATA_DLL_CNTL2 + EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default). +**/ + UINT32 EmmcRxCmdDataCntl2; + +/** Offset 0x031C - EMMC_MASTER_DLL_CNTL + EMMC_MASTER_DLL_CNTL. 0x001(Default). +**/ + UINT32 EmmcMasterSwCntl; + +/** Offset 0x0320 - PCIe Selectable De-emphasis + When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis + for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpSelectableDeemphasis[6]; + +/** Offset 0x0326 +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x0327 - Monitor Mwait Enable + Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux + based OS, this should be Disabled. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 MonitorMwaitEnable; + +/** Offset 0x0328 +**/ + UINT8 ReservedFspsUpd[8]; +} FSP_S_CONFIG; + +/** Fsp S Test Configuration +**/ +typedef struct { + +/** Offset 0x0330 +**/ + UINT32 Signature; + +/** Offset 0x0334 +**/ + UINT8 ReservedFspsTestUpd[12]; +} FSP_S_TEST_CONFIG; + +/** Fsp S Restricted Configuration +**/ +typedef struct { + +/** Offset 0x0340 +**/ + UINT32 Signature; + +/** Offset 0x0344 +**/ + UINT8 ReservedFspsRestrictedUpd[12]; +} FSP_S_RESTRICTED_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x0330 +**/ + FSP_S_TEST_CONFIG FspsTestConfig; + +/** Offset 0x0340 +**/ + FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; + +/** Offset 0x0350 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack(pop) + +#endif

1 0

Patch merged into coreboot/master: skylake: Add initial FSP2.0 support
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit 1222a73205bd3a0faba988411b4aec6ea8de1059 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Aug 23 14:31:23 2016 +0530 skylake: Add initial FSP2.0 support Add Initial pieces of code to support fsp2.0 in skylake keeping the fsp1.1 flow intact. The soc/romstage.h and soc/ramstage.h have a reference to fsp driver includes, so split these header files for each version of FSP driver. Add the below files, car_stage.S: Add romstage entry point (car_stage_entry). This calls into romstage_fsp20.c and aslo handles the car teardown. romstage_fsp20.c: Call fsp_memory_init() and also has the callback for filling memory init parameters. Also add monotonic_timer.c to verstage. With this patchset and relevant change in kunimitsu mainboard, we are able to boot to romstage. TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1 Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0 Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-on: https://review.coreboot.org/16267 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16267 for details. -gerrit

1 0

Patch merged into coreboot/master: i945: Enable changing VRAM size
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit 874a8f961ff537bc12cfca3d9937a07fcda2fe6e Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu May 19 16:06:09 2016 +0200 i945: Enable changing VRAM size On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states. What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge. TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/14819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14819 for details. -gerrit

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Patch set updated for coreboot: rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpu
by Martin Roth 31 Aug '16

31 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16368 -gerrit commit 07326e34e997df21fbbd3e60cb8b704e98a5e7db Author: Eric Gao <eric.gao(a)rock-chips.com> Date: Fri Jul 29 12:34:32 2016 +0800 rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpu Before, we calculate the pwm duties for cpu cores and centerlogic by hand, adding pwm_regulator.c to handle this. The default pwm design min/max voltage may be different between revs. With the pwm regulator, this patch changes the little cpu frequency from 600M to 1512M, and raises CPU voltage to 1.2V correspondingly. This also means we decide to drop the ES1 because it may fail to bootup with 1.5G ~ 1.2v. BRANCH=none BUG=chrome-os-partner:54376,chrome-os-partner:54862 TEST=Bootup on kevin board Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9 Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b Original-Signed-off-by: Eric Gao <eric.gao(a)rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364410 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/Makefile.inc | 3 ++ src/mainboard/google/gru/bootblock.c | 17 +++++- src/mainboard/google/gru/pwm_regulator.c | 82 +++++++++++++++++++++++++++++ src/mainboard/google/gru/pwm_regulator.h | 28 ++++++++++ src/mainboard/google/gru/romstage.c | 72 ++----------------------- src/soc/rockchip/rk3399/Makefile.inc | 2 + src/soc/rockchip/rk3399/bootblock.c | 1 - src/soc/rockchip/rk3399/clock.c | 6 +-- src/soc/rockchip/rk3399/include/soc/clock.h | 2 +- 9 files changed, 140 insertions(+), 73 deletions(-) diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index e1ba56a..9e07a6c 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -18,6 +18,8 @@ subdirs-y += sdram_params/ bootblock-y += bootblock.c bootblock-y += chromeos.c bootblock-y += memlayout.ld +bootblock-y += pwm_regulator.c +bootblock-y += boardid.c verstage-y += chromeos.c verstage-y += memlayout.ld @@ -26,6 +28,7 @@ verstage-y += reset.c romstage-y += boardid.c romstage-y += chromeos.c romstage-y += memlayout.ld +romstage-y += pwm_regulator.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index e80f4a3..ff91e1a 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -16,13 +16,17 @@ #include <arch/io.h> #include <bootblock_common.h> +#include <console/console.h> +#include <delay.h> #include <soc/grf.h> #include <gpio.h> +#include <soc/clock.h> #include <soc/i2c.h> +#include <soc/pwm.h> #include <soc/spi.h> -#include <console/console.h> #include "board.h" +#include "pwm_regulator.h" void bootblock_mainboard_early_init(void) { @@ -58,8 +62,19 @@ void bootblock_mainboard_early_init(void) #endif } +static void speed_up_boot_cpu(void) +{ + pwm_regulator_configure(PWM_REGULATOR_LIT, 1200); + + udelay(200); + + rkclk_configure_cpu(APLL_1512_MHZ, false); +} + void bootblock_mainboard_init(void) { + speed_up_boot_cpu(); + /* Set pinmux and configure spi flashrom. */ write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX); write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c new file mode 100644 index 0000000..f382b2b --- /dev/null +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <assert.h> +#include <boardid.h> +#include <console/console.h> +#include <soc/grf.h> +#include <soc/pwm.h> + +#include "pwm_regulator.h" + +/* + * Apparently a period of 3333 is determined by EEs to be ideal for our + * board design / resistors / capacitors / regulators but due to + * clock dividers we actually get 3337. + */ +#define PWM_PERIOD 3337 +#define PWM_DESIGN_VOLTAGE_MIN 8000 +#define PWM_DESIGN_VOLTAGE_MAX 15000 + +/* The min & max design voltages are different after kevin-r6 */ +int kevin_voltage_min_max_r6[][2] = { + [PWM_REGULATOR_GPU] = {7910, 12139}, + [PWM_REGULATOR_BIG] = {7986, 13057}, + [PWM_REGULATOR_LIT] = {7997, 13002}, + [PWM_REGULATOR_CENTERLOG] = {7996, 10507} +}; + +void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) +{ + int duty_ns, voltage_max, voltage_min; + int voltage = millivolt * 10; /* for higer calculation accuracy */ + + switch (pwm) { + case PWM_REGULATOR_GPU: + write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); + break; + case PWM_REGULATOR_BIG: + write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); + break; + case PWM_REGULATOR_LIT: + write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); + break; + case PWM_REGULATOR_CENTERLOG: + write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); + break; + } + + voltage_min = PWM_DESIGN_VOLTAGE_MIN; + voltage_max = PWM_DESIGN_VOLTAGE_MAX; + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6) { + voltage_min = kevin_voltage_min_max_r6[pwm][0]; + voltage_max = kevin_voltage_min_max_r6[pwm][1]; + } + + assert(voltage <= voltage_max && voltage >= voltage_min); + + /* + * Intentionally round down (higher volt) to be safe. + * eg, for the default min & max design voltage: + * period = 3337, volt = 1.1: 1906 + * period = 3337, volt = 1.0: 2383 + * period = 3337, volt = 0.9: 2860 + */ + duty_ns = PWM_PERIOD * (voltage_max - voltage) + / (voltage_max - voltage_min); + + pwm_init(pwm, PWM_PERIOD, duty_ns); +} diff --git a/src/mainboard/google/gru/pwm_regulator.h b/src/mainboard/google/gru/pwm_regulator.h new file mode 100644 index 0000000..6ef0c59 --- /dev/null +++ b/src/mainboard/google/gru/pwm_regulator.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_PWM_REGULATOR_H +#define __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_PWM_REGULATOR_H + +enum pwm_regulator { + PWM_REGULATOR_GPU = 0, + PWM_REGULATOR_BIG, + PWM_REGULATOR_LIT, + PWM_REGULATOR_CENTERLOG +}; + +void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt); + +#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_PWM_REGULATOR_H */ diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index ccf42b9..1e2507a 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -17,90 +17,28 @@ #include <arch/cache.h> #include <arch/cpu.h> #include <arch/exception.h> -#include <arch/io.h> #include <arch/mmu.h> -#include <boardid.h> #include <cbfs.h> #include <console/console.h> -#include <delay.h> #include <program_loading.h> #include <romstage_handoff.h> #include <soc/addressmap.h> -#include <soc/grf.h> #include <soc/mmu_operations.h> -#include <soc/pwm.h> #include <soc/tsadc.h> #include <soc/sdram.h> #include <symbols.h> #include <soc/usb.h> +#include "pwm_regulator.h" + static const uint64_t dram_size = (uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS); static void init_dvs_outputs(void) { - int duty_ns; - uint32_t i; - uint32_t id; - - write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); /* GPU */ - write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); /* Big */ - write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); /* Little */ - write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); /* Centerlog */ - - /* - * Set up voltages for all DVS rails. - * - * LITTLE CPU: At the speed we're running at right now and on the - * early silicon, .9V is sane. If/when we run faster, let's bump this. - * - * CENTER LOGIC: There are some claims that this should simply always - * be .9 V. There are other claims that say that we need to adjust this - * dynamically depending on the memory frequency. Until this is sorted - * out, it appears that .9 V works for the 800 MHz. - * - * BIG CPU / GPU: These aren't used in coreboot. Init to .9V which is - * supposed to be a good default. - * - * Details: - * design_min = 0.8 - * design_max = 1.5 - * period = 3337 # 300 kHz - * volt = 1.1 - * # Intentionally round down (higher volt) to be safe. - * int((period / (design_max - design_min)) * (design_max - volt)) - * - * Apparently a period of 3333 is determined by EEs to be ideal for our - * board design / resistors / capacitors / regulators but due to - * clock dividers we actually get 3337. Solving, we get: - * period = 3337, volt = 1.1: 1906 - * period = 3337, volt = 1.0: 2383 - * period = 3337, volt = 0.9: 2860 - */ - duty_ns = 2860; /* 0.9v */ - - /* TODO: Clean all this up, implement proper pwm_regulator driver. */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) { - id = board_id(); - if (id <= 2) - duty_ns = 1906; /* 1.1v */ - else if (id == 3) - duty_ns = 2621; /* 0.95v */ - else if (id >= 6) { - /* GPU: 3337 * (12043 - 9000) / (12043 - 7984) = 2501 */ - pwm_init(0, 3337, 2501); - /* BIG: 3337 * (12837 - 9000) / (12837 - 7985) = 2638 */ - pwm_init(1, 3337, 2638); - /* LIT: 3337 * (12807 - 9000) / (12807 - 8009) = 2647 */ - pwm_init(2, 3337, 2647); - /* CTR: 3337 * (10507 - 9500) / (10507 - 7996) = 1338 */ - pwm_init(3, 3337, 1338); - return; - } - } - - for (i = 0; i < 4; i++) - pwm_init(i, 3337, duty_ns); + pwm_regulator_configure(PWM_REGULATOR_GPU, 900); + pwm_regulator_configure(PWM_REGULATOR_BIG, 900); + pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 950); } static void prepare_usb(void) diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 6e75278..ceec7bc 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -23,10 +23,12 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c endif bootblock-y += ../common/gpio.c +bootblock-y += ../common/pwm.c bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += gpio.c bootblock-y += mmu_operations.c +bootblock-y += saradc.c bootblock-y += timer.c verstage-y += ../common/cbmem.c diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c index 4f85e94..7b80a75 100644 --- a/src/soc/rockchip/rk3399/bootblock.c +++ b/src/soc/rockchip/rk3399/bootblock.c @@ -22,7 +22,6 @@ void bootblock_soc_init(void) { rkclk_init(); - rkclk_configure_cpu(APLL_600_MHZ, false); /* all ddr range non-secure */ write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index ed9afda..428a210 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -47,11 +47,11 @@ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); -static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); -static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div apll_1512_cfg = PLL_DIVISORS(1512*MHz, 1, 1, 1); +static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 3, 1); static const struct pll_div *apll_cfgs[] = { - [APLL_1600_MHZ] = &apll_1600_cfg, + [APLL_1512_MHZ] = &apll_1512_cfg, [APLL_600_MHZ] = &apll_600_cfg, }; diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 19e315b..de86ed4 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -97,7 +97,7 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PWM_CLOCK_HZ PMU_PCLK_HZ enum apll_frequencies { - APLL_1600_MHZ, + APLL_1512_MHZ, APLL_600_MHZ, };

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Patch merged into coreboot/master: rockchip/rk3399: Move romstage.c to mainboard/gru
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit 868cd7128262ca8442301c2910ed843ab3f193ff Author: Shunqian Zheng <zhengsq(a)rock-chips.com> Date: Thu Aug 25 02:28:19 2016 +0800 rockchip/rk3399: Move romstage.c to mainboard/gru The romstage.c is more board related than soc specific, like setting the pwm regulators, so moving it to mainboard/gru. BRANCH=none BUG=chrome-os-partner:54819 TEST=Bootup on kevin board Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474 Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443 Original-Signed-off-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/375398 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/16367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16367 for details. -gerrit

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Patch merged into coreboot/master: Provide CAR decoration for tpm2 statics
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit f706020ed6efa4892de61710fa30b8520522c61d Author: Victor Prupis <vprupis(a)google.com> Date: Fri Aug 19 10:45:04 2016 -0700 Provide CAR decoration for tpm2 statics Decorated tpm2 statics with CAR_GLOBAL BUG=chrome-os-partner:55083 BRANCH=none TEST=none Change-Id: I85620d5c6ffddab5514c01c2c652670bf33b4e7e Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: ae43d3bb7fed5b891ed38cd268bfe4e1416b77e2 Original-Change-Id: I871442ec096836a86870f8d53a3058c9c040cff8 Original-Signed-off-by: Victor Prupis <vprupis(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/373243 Original-Commit-Ready: Stefan Reinauer <reinauer(a)google.com> Original-Tested-by: Stefan Reinauer <reinauer(a)google.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16366 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16366 for details. -gerrit

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Patch merged into coreboot/master: parade/ps8640: disable mipi mcs
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit 70c496b24ee2ed09969575afc291dadb19eea189 Author: Jitao Shi <jitao.shi(a)mediatek.com> Date: Fri Aug 19 16:00:01 2016 +0800 parade/ps8640: disable mipi mcs Disable ps8640 mipi mcs function to avoid recognizing the normal mipi dsi signal as msc cmd. BUG=chrome-os-partner:56346 BRANCH=none TEST=build pass elm and show ui Change-Id: I91c690fb1ff3bd9b5c1f227205829c914347cd30 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 4fd441b46300fea9f238b27c9c1cda4e9e53c80d Original-Change-Id: I85b9f1e6677e4bf8ab1e30c2e69445079fff2d18 Original-Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/373219 Original-Commit-Ready: Daniel Kurtz <djkurtz(a)chromium.org> Original-Tested-by: jitao shi <jitao.shi(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz(a)chromium.org> Reviewed-on: https://review.coreboot.org/16365 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16365 for details. -gerrit

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Patch set updated for coreboot: parade/ps8640: disable mipi mcs
by Martin Roth 31 Aug '16

31 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16365 -gerrit commit b50939c00d5bdadbb12939b795eadb65c723f67d Author: Jitao Shi <jitao.shi(a)mediatek.com> Date: Fri Aug 19 16:00:01 2016 +0800 parade/ps8640: disable mipi mcs Disable ps8640 mipi mcs function to avoid recognizing the normal mipi dsi signal as msc cmd. BUG=chrome-os-partner:56346 BRANCH=none TEST=build pass elm and show ui Change-Id: I91c690fb1ff3bd9b5c1f227205829c914347cd30 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 4fd441b46300fea9f238b27c9c1cda4e9e53c80d Original-Change-Id: I85b9f1e6677e4bf8ab1e30c2e69445079fff2d18 Original-Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/373219 Original-Commit-Ready: Daniel Kurtz <djkurtz(a)chromium.org> Original-Tested-by: jitao shi <jitao.shi(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz(a)chromium.org> --- src/drivers/parade/ps8640/ps8640.c | 10 ++++++++++ src/drivers/parade/ps8640/ps8640.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c index c26c6ef..9596560 100644 --- a/src/drivers/parade/ps8640/ps8640.c +++ b/src/drivers/parade/ps8640/ps8640.c @@ -76,6 +76,16 @@ int ps8640_init(uint8_t bus, uint8_t chip) } mdelay(50); + + /* + * The Manufacturer Command Set (MCS) is a device dependent interface + * intended for factory programming of the display module default + * parameters. Once the display module is configured, the MCS shall be + * disabled by the manufacturer. Once disabled, all MCS commands are + * ignored by the display interface. + */ + i2c_write_field(bus, chip + 2, PAGE2_MCS_EN, 0x0, MCS_EN_MASK, + MCS_EN_SHIFT); i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD); i2c_writeb(bus, chip + 3, PAGE3_SET_VAL, VDO_DIS); i2c_writeb(bus, chip + 3, PAGE3_SET_ADD, VDO_CTL_ADD); diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h index f7b4006..4540122 100644 --- a/src/drivers/parade/ps8640/ps8640.h +++ b/src/drivers/parade/ps8640/ps8640.h @@ -26,6 +26,9 @@ enum { PS_GPIO9 = BIT(1), I2C_BYPASS_EN = BIT(7), + PAGE2_MCS_EN = 0xf3, + MCS_EN_SHIFT = 0, + MCS_EN_MASK = 0x1, PAGE3_SET_ADD = 0xfe, PAGE3_SET_VAL = 0xff, VDO_CTL_ADD = 0x13,

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Patch merged into coreboot/master: parade/ps8640: add delay to every loop when polling ps8640 ready
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit 54aa89c7b4ea793f49f6cfe73e13b4ce71dd138f Author: Jitao Shi <jitao.shi(a)mediatek.com> Date: Wed Aug 17 10:21:37 2016 +0800 parade/ps8640: add delay to every loop when polling ps8640 ready Add delay before and in polling ps8640 ready to reduce the frequency of polling. BUG=chrome-os-partner:54897 BRANCH=none TEST=build pass elm and show ui Change-Id: I43c833af910490e53496a343330a6a6af35623a9 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: bc8c3d6f7cf0b2da693a465cf3845e8bbc53825a Original-Change-Id: I5c725eed8110ff9f545c1142ca28bcff336b6860 Original-Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/371718 Original-Commit-Ready: Nicolas Boichat <drinkcat(a)chromium.org> Original-Tested-by: jitao shi <jitao.shi(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz(a)chromium.org> Reviewed-on: https://review.coreboot.org/16364 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16364 for details. -gerrit

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Patch merged into coreboot/master: mainboard/*/Kconfig: Set GBB_HWID where missing
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit a4e7165fd1c2b6d7a548cfb65f171f3e2a6879f8 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Thu Aug 18 11:22:28 2016 +0200 mainboard/*/Kconfig: Set GBB_HWID where missing Provide GBB's hardware ID (used on Chrome OS devices) because it will be dropped from depthcharge. BRANCH=none BUG=none TEST=none Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00 Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/372579 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16363 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16363 for details. -gerrit

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coreboot-gerrit August 2016