coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: commonlib: update fsp_relocate to make it compatible with UEFI 2.6
by Brandon Breitenstein 31 Aug '16

31 Aug '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16309 -gerrit commit c88a5e413863ebae6d0091c814c6e5f380363c29 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Tue Aug 23 14:55:13 2016 -0700 commonlib: update fsp_relocate to make it compatible with UEFI 2.6 UEFI 2.6 spec casts the return of FFS_FILE2_SIZE to a UINT32 which cannot be read using read_le32(&returnval). Add in a cast in order to safeguard for any non x86 architecture that may use this relocate. The proper change will be to get the UEFI header files changed to not cast this return value. Change-Id: Ie1b50d99576ac42a0413204bbd599bab9f01828e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/commonlib/fsp_relocate.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 7f1e49a..57c0ac9 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -258,8 +258,15 @@ static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh) { size_t size; - if (IS_FFS_FILE2(ffsfh)) - size = read_le32(&FFS_FILE2_SIZE(ffsfh)); + if (IS_FFS_FILE2(ffsfh)) { + /* + * this cast is needed with UEFI 2.6 headers in order + * to read the UINT32 value that FFS_FILE2_SIZE converts + * the return into + */ + uint32_t file2_size = FFS_FILE2_SIZE(ffsfh); + size = read_le32(&file2_size); + } else { size = read_le8(&ffsfh->Size[0]) << 0; size |= read_le8(&ffsfh->Size[1]) << 8;

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Patch set updated for coreboot: apollolake: relocate fsp header files to vendorcode
by Brandon Breitenstein 31 Aug '16

31 Aug '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16310 -gerrit commit 97f1734a62ce6b39a555c570ce8465e3f2144c71 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Tue Aug 23 15:03:50 2016 -0700 apollolake: relocate fsp header files to vendorcode FSP header files should be located in vendorcode, not soc directory. This patch includes changes any references to the old location to the new location. Change-Id: I44270392617418ec1b9dec15ee187863f2503341 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/soc_binding.h | 6 +- src/mainboard/intel/amenia/romstage.c | 2 +- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/fsp/FspUpd.h | 48 - src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 721 --------- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 1541 -------------------- src/soc/intel/apollolake/include/soc/meminit.h | 2 +- src/soc/intel/apollolake/meminit.c | 2 +- .../intel/fsp/fsp2_0/apollolake/FspUpd.h | 48 + .../intel/fsp/fsp2_0/apollolake/FspmUpd.h | 721 +++++++++ .../intel/fsp/fsp2_0/apollolake/FspsUpd.h | 1541 ++++++++++++++++++++ 11 files changed, 2317 insertions(+), 2316 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index cfe5a02..8709cb7 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -18,13 +18,13 @@ #pragma pack(push) /* - * This file is found in the soc / chipset directory. It is + * This file is found in the vendorcode directory. It is * a per implementation specific header. i.e. different FSP implementations * for different chipsets. */ #include <Base.h> -#include <soc/fsp/FspmUpd.h> -#include <soc/fsp/FspsUpd.h> +#include <FspmUpd.h> +#include <FspsUpd.h> #pragma pack(pop) diff --git a/src/mainboard/intel/amenia/romstage.c b/src/mainboard/intel/amenia/romstage.c index 6719472..13e096b 100644 --- a/src/mainboard/intel/amenia/romstage.c +++ b/src/mainboard/intel/amenia/romstage.c @@ -17,7 +17,7 @@ #include <soc/romstage.h> #include <string.h> -#include <soc/fsp/FspmUpd.h> +#include <FspmUpd.h> /* Channel 0 PHY to DUnit DQ mapping */ static const uint8_t swizzling_ch0_amenia[] = { diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1f3c276..3c45cbe 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -93,6 +93,7 @@ verstage-y += reset.c verstage-y += spi.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake # Since FSP-M runs in CAR we need to relocate it to a specific address $(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h deleted file mode 100644 index a7114ce..0000000 --- a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#pragma pack(push, 1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ - -#pragma pack(pop) - -#endif diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h deleted file mode 100644 index 48225e0..0000000 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ /dev/null @@ -1,721 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -#define MAX_CHANNELS_NUM 4 -#define MAX_DIMMS_NUM 1 - -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - /** Module part number for DRR3 is 18 bytes - but DRR4 is 20 bytes as per JEDEC Spec, so - reserving 20 bytes **/ - UINT8 ModulePartNum[20]; -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT8 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT16 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} FSP_SMBIOS_MEMORY_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Debug Serial Port Base address - Debug serial port base address. This option will be used only when the 'Serial Port - Debug Device' option is set to 'External Device'. 0x00000000(Default). -**/ - UINT32 SerialDebugPortAddress; - -/** Offset 0x0044 - Debug Serial Port Type - 16550 compatible debug serial port resource type. NONE means no serial port support. - 0x02:MMIO(Default). - 0:NONE, 1:I/O, 2:MMIO -**/ - UINT8 SerialDebugPortType; - -/** Offset 0x0045 - Serial Port Debug Device - Select active serial port device for debug. For SOC UART devices,'Debug Serial Port - Base' options will be ignored. 0x02:SOC UART2(Default). - 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device -**/ - UINT8 SerialDebugPortDevice; - -/** Offset 0x0046 - Debug Serial Port Stride Size - Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). - 0:1, 2:4 -**/ - UINT8 SerialDebugPortStrideSize; - -/** Offset 0x0047 - Memory Fast Boot - Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0048 - Integrated Graphics Device - Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video - Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 Igd; - -/** Offset 0x0049 - DVMT Pre-Allocated - Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal - Graphics Device. 0x02:64 MB(Default). - 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 - MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, - 0x0F:480 MB, 0x10:512 MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x004A - Aperture Size - Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), - 0x2:256 MB, 0x3:512 MB. - 0x1:128 MB, 0x2:256 MB, 0x3:512 MB -**/ - UINT8 IgdApertureSize; - -/** Offset 0x004B - GTT Size - Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 - MB(Default). - 0x1:2 MB, 0x2:4 MB, 0x3:8 MB -**/ - UINT8 GttSize; - -/** Offset 0x004C - Primary Display - Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), - 0x2:IGD, 0x3:PCI - 0x0:AUTO, 0x2:IGD, 0x3:PCI -**/ - UINT8 PrimaryVideoAdaptor; - -/** Offset 0x004D - Package - NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L - is being used. 0x00(Default). - 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD -**/ - UINT8 Package; - -/** Offset 0x004E - Profile - Profile list. 0x19(Default). - 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, - 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, - 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, - 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, - 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, - 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, - 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, - 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, - 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, - 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, - 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, - 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 -**/ - UINT8 Profile; - -/** Offset 0x004F - MemoryDown - Memory Down. 0x0(Default). - 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 -**/ - UINT8 MemoryDown; - -/** Offset 0x0050 - DDR3LPageSize - NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB. - 0x1:1KB, 0x2:2KB -**/ - UINT8 DDR3LPageSize; - -/** Offset 0x0051 - DDR3LASR - NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported. - 0x0:Not Supported, 0x1:Supported -**/ - UINT8 DDR3LASR; - -/** Offset 0x0052 - ScramblerSupport - Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default). - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x0053 - ChannelHashMask - Channel Hash Mask. 0x00(Default). -**/ - UINT16 ChannelHashMask; - -/** Offset 0x0055 - SliceHashMask - Slice Hash Mask. 0x00(Default). -**/ - UINT16 SliceHashMask; - -/** Offset 0x0057 - InterleavedMode - Interleaved Mode. 0x00:Disable(Default), 0x02:Enable. - 0x0:Disable, 0x2:Enable -**/ - UINT8 InterleavedMode; - -/** Offset 0x0058 - ChannelsSlicesEnable - Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 ChannelsSlicesEnable; - -/** Offset 0x0059 - MinRefRate2xEnable - Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), - 0x01:Enable. - $EN_DIS -**/ - UINT8 MinRefRate2xEnable; - -/** Offset 0x005A - DualRankSupportEnable - Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). - $EN_DIS -**/ - UINT8 DualRankSupportEnable; - -/** Offset 0x005B - RmtMode - Rank Margin Tool Mode. 0x00(Default). - $EN_DIS -**/ - UINT8 RmtMode; - -/** Offset 0x005C - MemorySizeLimit - Memory Size Limit: This value is used to restrict the total amount of memory and - the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, - 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) -**/ - UINT16 MemorySizeLimit; - -/** Offset 0x005E - LowMemoryMaxValue - Low Memory Max Value: This value is used to restrict the amount of memory below - 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 - = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). -**/ - UINT16 LowMemoryMaxValue; - -/** Offset 0x0060 - DisableFastBoot - 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train - of memory. - $EN_DIS -**/ - UINT8 DisableFastBoot; - -/** Offset 0x0061 - HighMemoryMaxValue - High Memory Max Value: This value is used to restrict the amount of memory above - 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, - 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). -**/ - UINT16 HighMemoryMaxValue; - -/** Offset 0x0063 - DIMM0SPDAddress - DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). -**/ - UINT8 DIMM0SPDAddress; - -/** Offset 0x0064 - DIMM1SPDAddress - DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). -**/ - UINT8 DIMM1SPDAddress; - -/** Offset 0x0065 - Ch0_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default). -**/ - UINT8 Ch0_RankEnable; - -/** Offset 0x0066 - Ch0_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch0_DeviceWidth; - -/** Offset 0x0067 - Ch0_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch0_DramDensity; - -/** Offset 0x0068 - Ch0_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank - Address Hashing Enable. See Address Mapping section for full description. 0:Bank - Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] - This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). - 0x03(Default). -**/ - UINT8 Ch0_Option; - -/** Offset 0x0069 - Ch0_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. -**/ - UINT8 Ch0_OdtConfig; - -/** Offset 0x006A - Ch0_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). -**/ - UINT8 Ch0_TristateClk1; - -/** Offset 0x006B - Ch0_Mode2N - 2N Mode. 0x00(Default). -**/ - UINT8 Ch0_Mode2N; - -/** Offset 0x006C - Ch0_OdtLevels - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. - [1] Bank Address Hashing Enable. See Address Mapping section for full description. - 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). -**/ - UINT8 Ch0_OdtLevels; - -/** Offset 0x006D - Ch1_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch1 rank. -**/ - UINT8 Ch1_RankEnable; - -/** Offset 0x006E - Ch1_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch1_DeviceWidth; - -/** Offset 0x006F - Ch1_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default). - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch1_DramDensity; - -/** Offset 0x0070 - Ch1_Option - Rank Select Interleaving Enable. See Address Mapping section for full description. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB - (B), 0x03(Default). -**/ - UINT8 Ch1_Option; - -/** Offset 0x0071 - Ch1_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. -**/ - UINT8 Ch1_OdtConfig; - -/** Offset 0x0072 - Ch1_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). -**/ - UINT8 Ch1_TristateClk1; - -/** Offset 0x0073 - Ch1_Mode2N - 2N Mode. 0x00(Default). -**/ - UINT8 Ch1_Mode2N; - -/** Offset 0x0074 - Ch1_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. -**/ - UINT8 Ch1_OdtLevels; - -/** Offset 0x0075 - Ch2_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch2 rank. -**/ - UINT8 Ch2_RankEnable; - -/** Offset 0x0076 - Ch2_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch2_DeviceWidth; - -/** Offset 0x0077 - Ch2_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch2_DramDensity; - -/** Offset 0x0078 - Ch2_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description.. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). - 01:2KB (B). -**/ - UINT8 Ch2_Option; - -/** Offset 0x0079 - Ch2_OdtConfig - ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. -**/ - UINT8 Ch2_OdtConfig; - -/** Offset 0x007A - Ch2_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). -**/ - UINT8 Ch2_TristateClk1; - -/** Offset 0x007B - Ch2_Mode2N - 2N Mode. 0x00(Default). -**/ - UINT8 Ch2_Mode2N; - -/** Offset 0x007C - Ch2_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. -**/ - UINT8 Ch2_OdtLevels; - -/** Offset 0x007D - Ch3_RankEnable - NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default). -**/ - UINT8 Ch3_RankEnable; - -/** Offset 0x007E - Ch3_DeviceWidth - NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), - 0x01:x16, 0x02:x32, 0x03:x64. - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 -**/ - UINT8 Ch3_DeviceWidth; - -/** Offset 0x007F - Ch3_DramDensity - NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), - 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb -**/ - UINT8 Ch3_DramDensity; - -/** Offset 0x0080 - Ch3_Option - Rank Select Interleaving Enable. See Address Mapping section for full description.. - 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] - Bank Address Hashing Enable. See Address Mapping section for full description.. - 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. - [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 - - 2KB (B). -**/ - UINT8 Ch3_Option; - -/** Offset 0x0081 - Ch3_OdtConfig - ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG. -**/ - UINT8 Ch3_OdtConfig; - -/** Offset 0x0082 - Ch3_TristateClk1 - Parameter used to determine whether to tristate CLK1. 0x00(Default). -**/ - UINT8 Ch3_TristateClk1; - -/** Offset 0x0083 - Ch3_Mode2N - 2N Mode. 0x00(Default). -**/ - UINT8 Ch3_Mode2N; - -/** Offset 0x0084 - Ch3_OdtLevels - Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), - 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. -**/ - UINT8 Ch3_OdtLevels; - -/** Offset 0x0085 - RmtCheckRun - RmtCheckRun: 0x00(Default). -**/ - UINT8 RmtCheckRun; - -/** Offset 0x0086 - Ch0_Bit_swizzling - Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch0_Bit_swizzling[32]; - -/** Offset 0x00A6 - Ch1_Bit_swizzling - Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch1_Bit_swizzling[32]; - -/** Offset 0x00C6 - Ch2_Bit_swizzling - Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch2_Bit_swizzling[32]; - -/** Offset 0x00E6 - Ch3_Bit_swizzling - Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. -**/ - UINT8 Ch3_Bit_swizzling[32]; - -/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold - RmtMarginCheckScaleHighThreshold. 0x0000(Default). -**/ - UINT16 RmtMarginCheckScaleHighThreshold; - -/** Offset 0x0108 - MsgLevelMask - MsgLevelMask. 0x00000000(Default). -**/ - UINT32 MsgLevelMask; - -/** Offset 0x010C -**/ - UINT32 UnusedUpdSpace0; - -/** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4 - Number of Entries in PreMem GPIO Table. 0(Default). -**/ - UINT8 PreMemGpioTableEntryNum; - -/** Offset 0x0111 - PreMem GPIO Pin Number for each table - Number of Pins in each PreMem GPIO Table. 0(Default). -**/ - UINT8 PreMemGpioTablePinNum[4]; - -/** Offset 0x0115 - PreMem GPIO Table Pointer - Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default). -**/ - UINT32 PreMemGpioTablePtr; - -/** Offset 0x0119 - Enhance the port 8xh decoding - Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnhancePort8xhDecoding; - -/** Offset 0x011A - OEM File Loading Address - Determine the memory base address to load a specified file from CSE file system - after memory is available. -**/ - UINT32 OemLoadingBase; - -/** Offset 0x011E - OEM File Name to Load - Specify a file name to load from CSE file system after memory is available. Empty - indicates no file needs to be loaded. -**/ - UINT8 OemFileName[16]; - -/** Offset 0x012E - SPD Data Write - Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 SpdWriteEnable; - -/** Offset 0x012F - MRC Training Data Saving - Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 MrcDataSaving; - -/** Offset 0x0130 - eMMC Trace Length - Select eMMC trace length to load OEM file from when loading OEM file name is specified. - 0x0:Long(Default), 0x1:Short. - 0x0:Long, 0x1:Short -**/ - UINT8 eMMCTraceLen; - -/** Offset 0x0131 -**/ - VOID* MrcBootDataPtr; - -/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB - Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of - CSE. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 SkipCseRbp; - -/** Offset 0x0136 - Npk Enable - Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default). - 0:Disable, 1:Enable, 2:Debugger, 3:Auto -**/ - UINT8 NpkEn; - -/** Offset 0x0137 - FW Trace Enable - Enable/Disable FW Trace. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 FwTraceEn; - -/** Offset 0x0138 - FW Trace Destination - FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB, - 4-NPK_TRACE_TO_PTI(Default). -**/ - UINT8 FwTraceDestination; - -/** Offset 0x0139 - NPK Recovery Dump - Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 RecoverDump; - -/** Offset 0x013A - Memory Region 0 Buffer WrapAround - Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - UINT8 Msc0Wrap; - -/** Offset 0x013B - Memory Region 1 Buffer WrapAround - Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - UINT8 Msc1Wrap; - -/** Offset 0x013C - Memory Region 0 Buffer Size - Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, - 6-512MB, 7-1GB. -**/ - UINT32 Msc0Size; - -/** Offset 0x0140 - Memory Region 1 Buffer Size - Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, - 6-512MB, 7-1GB. -**/ - UINT32 Msc1Size; - -/** Offset 0x0144 - PTI Mode - PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. -**/ - UINT8 PtiMode; - -/** Offset 0x0145 - PTI Training - PTI Training. 0-off(Default), 1-6=1-6. -**/ - UINT8 PtiTraining; - -/** Offset 0x0146 - PTI Speed - PTI Speed. 0-full, 1-half, 2-quarter(Default). -**/ - UINT8 PtiSpeed; - -/** Offset 0x0147 - Punit Message Level - Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. -**/ - UINT8 PunitMlvl; - -/** Offset 0x0148 - PMC Message Level - PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. -**/ - UINT8 PmcMlvl; - -/** Offset 0x0149 - SW Trace Enable - Enable/Disable SW Trace. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SwTraceEn; - -/** Offset 0x014A - Periodic Retraining Disable - Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. - $EN_DIS -**/ - UINT8 PeriodicRetrainingDisable; - -/** Offset 0x014B -**/ - UINT8 ReservedFspmUpd[5]; -} FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0150 -**/ - UINT32 Signature; - -/** Offset 0x0154 -**/ - UINT8 ReservedFspmTestUpd[28]; -} FSP_M_TEST_CONFIG; - -/** Fsp M Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0170 -**/ - UINT32 Signature; - -/** Offset 0x0174 -**/ - UINT8 ReservedFspmRestrictedUpd[138]; -} FSP_M_RESTRICTED_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0150 -**/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x0170 -**/ - FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; - -/** Offset 0x01FE -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack(pop) - -#endif diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h deleted file mode 100644 index 553eba3..0000000 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ /dev/null @@ -1,1541 +0,0 @@ -/** @file - -Copyright (c) 2016, Intel Corporation. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - -#pragma pack(push, 1) - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - ActiveProcessorCores - Number of active cores. 0:Disable(Default), 1:Enable. -**/ - UINT8 ActiveProcessorCores; - -/** Offset 0x0021 - Disable Core1 - Disable/Enable Core1. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore1; - -/** Offset 0x0022 - Disable Core2 - Disable/Enable Core2. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore2; - -/** Offset 0x0023 - Disable Core3 - Disable/Enable Core3. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DisableCore3; - -/** Offset 0x0024 - VMX Enable - Enable or Disable VMX. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x0025 - Memory region allocation for Processor Trace - Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to - 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default) -**/ - UINT8 ProcTraceMemSize; - -/** Offset 0x0026 - Enable Processor Trace - Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 ProcTraceEnable; - -/** Offset 0x0027 - Eist - Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x0028 - Boot PState - Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. -**/ - UINT8 BootPState; - -/** Offset 0x0029 - CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableCx; - -/** Offset 0x002A - Enhanced C-states - Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x002B - Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x002C - Max Pkg Cstate - Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, - 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x002D -**/ - UINT8 UnusedUpdSpace0; - -/** Offset 0x002E - C-State auto-demotion - C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 - Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion - to C1 and C3. -**/ - UINT8 CStateAutoDemotion; - -/** Offset 0x002F - C-State un-demotion - C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, - 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. -**/ - UINT8 CStateUnDemotion; - -/** Offset 0x0030 - Max Core C-State - Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). -**/ - UINT8 MaxCoreCState; - -/** Offset 0x0031 - Package C-State Demotion - Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x0032 - Package C-State Un-demotion - Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x0033 - Turbo Mode - Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0034 - SC HDA Verb Table Entry Number - Number of Entries in Verb Table. 0(Default). -**/ - UINT8 HdaVerbTableEntryNum; - -/** Offset 0x0035 - SC HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. 0x00000000(Default). -**/ - UINT32 HdaVerbTablePtr; - -/** Offset 0x0039 - Enable/Disable P2SB device hidden. - Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 P2sbUnhide; - -/** Offset 0x003A - IPU Enable/Disable - Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IpuEn; - -/** Offset 0x003B - IMGU ACPI mode selection - 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. - 0:Disable, 1:IGFX Child device, 2:ACPI device -**/ - UINT8 IpuAcpiMode; - -/** Offset 0x003C - GttMmAdr - GttMmAdr structure for initialization. 0xBF000000(Default). -**/ - UINT32 GttMmAdr; - -/** Offset 0x0040 - GmAdr - GmAdr structure for initialization. 0xA0000000(Default). -**/ - UINT32 GmAdr; - -/** Offset 0x0044 - Enable ForceWake - Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 ForceWake; - -/** Offset 0x0045 - Enable PavpLock - Enable/disable PavpLock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PavpLock; - -/** Offset 0x0046 - Enable GraphicsFreqModify - Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsFreqModify; - -/** Offset 0x0047 - Enable GraphicsFreqReq - Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsFreqReq; - -/** Offset 0x0048 - Enable GraphicsVideoFreq - Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GraphicsVideoFreq; - -/** Offset 0x0049 - Enable PmLock - Enable/disable PmLock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PmLock; - -/** Offset 0x004A - Enable DopClockGating - Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DopClockGating; - -/** Offset 0x004B - Enable UnsolicitedAttackOverride - Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UnsolicitedAttackOverride; - -/** Offset 0x004C - Enable WOPCMSupport - Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 WOPCMSupport; - -/** Offset 0x004D - Enable WOPCMSize - Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 WOPCMSize; - -/** Offset 0x004E - Enable PowerGating - Enable/disable PowerGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PowerGating; - -/** Offset 0x004F - Enable UnitLevelClockGating - Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UnitLevelClockGating; - -/** Offset 0x0050 - Enable FastBoot - Enable/disable FastBoot. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 FastBoot; - -/** Offset 0x0051 - Enable DynSR - Enable/disable DynSR. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DynSR; - -/** Offset 0x0052 - Enable SaIpuEnable - Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x0053 - BMP Logo Data Size - BMP logo data buffer size. 0x00000000(Default). -**/ - UINT32 LogoSize; - -/** Offset 0x0057 - BMP Logo Data Pointer - BMP logo data pointer to a BMP format buffer. 0x00000000(Default). -**/ - UINT32 LogoPtr; - -/** Offset 0x005B - Graphics Configuration Data Pointer - Graphics configuration data used for initialization. 0x00000000(Default). -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x005F - GT PM Support - Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x0060 - RC6(Render Standby) - Enable/Disable render standby support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableRenderStandby; - -/** Offset 0x0061 - PAVP Enable - Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0062 - PAVP PR3 - Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PavpPr3; - -/** Offset 0x0063 - CdClock Frequency selection - 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). - 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz -**/ - UINT8 CdClock; - -/** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit - Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x0065 - Write Protection Support - Enable/disable Write Protection. 0:Disable, 1:Enable(Default). -**/ - UINT8 WriteProtectionEnable[5]; - -/** Offset 0x006A - Read Protection Support - Enable/disable Read Protection. 0:Disable, 1:Enable(Default). -**/ - UINT8 ReadProtectionEnable[5]; - -/** Offset 0x006F - Protected Range Limitation - The address of the upper limit of protection, 0x0FFFh(Default). -**/ - UINT16 ProtectedRangeLimit[5]; - -/** Offset 0x0079 - Protected Range Base - The base address of the upper limit of protection. 0x0000(Default). -**/ - UINT16 ProtectedRangeBase[5]; - -/** Offset 0x0083 - Enable SC Gaussian Mixture Models - Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Gmm; - -/** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk - Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingPgcbClkTrunk; - -/** Offset 0x0085 - GMM Clock Gating - Sideband - Enable/disable Sideband. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSb; - -/** Offset 0x0086 - GMM Clock Gating - Sideband - Enable/disable Sideband. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSbClkTrunk; - -/** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition - Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingSbClkPartition; - -/** Offset 0x0088 - GMM Clock Gating - Core - Enable/disable Core. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingCore; - -/** Offset 0x0089 - GMM Clock Gating - DMA - Enable/disable DMA. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingDma; - -/** Offset 0x008A - GMM Clock Gating - Register Access - Enable/disable Register Access. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingRegAccess; - -/** Offset 0x008B - GMM Clock Gating - Host - Enable/disable Host. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingHost; - -/** Offset 0x008C - GMM Clock Gating - Partition - Enable/disable Partition. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingPartition; - -/** Offset 0x008D - Clock Gating - Trunk - Enable/disable Trunk. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ClkGatingTrunk; - -/** Offset 0x008E - HD Audio Support - Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 HdaEnable; - -/** Offset 0x008F - HD Audio DSP Support - Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DspEnable; - -/** Offset 0x0090 - Azalia wake-on-ring - Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 Pme; - -/** Offset 0x0091 - HD-Audio I/O Buffer Ownership - Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default) - 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and - I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers -**/ - UINT8 HdAudioIoBufferOwnership; - -/** Offset 0x0092 - HD-Audio I/O Buffer Voltage - HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. - 0: 3.3V, 1: 1.8V -**/ - UINT8 HdAudioIoBufferVoltage; - -/** Offset 0x0093 - HD-Audio Virtual Channel Type - HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. - 0: VC0, 1: VC1 -**/ - UINT8 HdAudioVcType; - -/** Offset 0x0094 - HD-Audio Link Frequency - HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, - 4:96MHz, 5:Invalid. - 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid -**/ - UINT8 HdAudioLinkFrequency; - -/** Offset 0x0095 - HD-Audio iDisp-Link Frequency - HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, - 4:96MHz, 5:Invalid. - 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid -**/ - UINT8 HdAudioIDispLinkFrequency; - -/** Offset 0x0096 - HD-Audio iDisp-Link T-Mode - HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. - 0: 2T, 1: 1T -**/ - UINT8 HdAudioIDispLinkTmode; - -/** Offset 0x0097 - HD-Audio Disp DMIC - HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. - 0: Disable, 1: 2ch array, 2: 4ch array -**/ - UINT8 DspEndpointDmic; - -/** Offset 0x0098 - HD-Audio Bluetooth - Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 DspEndpointBluetooth; - -/** Offset 0x0099 - HD-Audio I2S SHK - Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DspEndpointI2sSkp; - -/** Offset 0x009A - HD-Audio I2S HP - Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 DspEndpointI2sHp; - -/** Offset 0x009B - HD-Audio Controller Power Gating - Enable/Disable HD-Audio Controller Power Gating. This option is deprecated. - $EN_DIS -**/ - UINT8 AudioCtlPwrGate; - -/** Offset 0x009C - HD-Audio ADSP Power Gating - Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated. - $EN_DIS -**/ - UINT8 AudioDspPwrGate; - -/** Offset 0x009D - HD-Audio CSME Memory Transfers - Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. - 0: VC0, 1: VC2 -**/ - UINT8 Mmt; - -/** Offset 0x009E - HD-Audio Host Memory Transfers - Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. - 0: VC0, 1: VC2 -**/ - UINT8 Hmt; - -/** Offset 0x009F - HD-Audio BIOS Configuration Lock Down - Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 BiosCfgLockDown; - -/** Offset 0x00A0 - HD-Audio Power Gating - Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HDAudioPwrGate; - -/** Offset 0x00A1 - HD-Audio Clock Gatingn - Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HDAudioClkGate; - -/** Offset 0x00A2 - Bitmask of DSP Feature - Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: - Intel WoV, 1: Windows Voice Activation -**/ - UINT32 DspFeatureMask; - -/** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules - Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). - [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] - - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: - Intel WoV, 1: Windows Voice Activation -**/ - UINT32 DspPpModuleMask; - -/** Offset 0x00AA - Enable High Precision Timer - Enable/Disable Hpet. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 Hpet; - -/** Offset 0x00AB - Hpet Valid BDF Value - Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HpetBdfValid; - -/** Offset 0x00AC - Bus Number of Hpet - Completer ID of Bus Number of Hpet. Default = 0xFA(Default). -**/ - UINT8 HpetBusNumber; - -/** Offset 0x00AD - Device Number of Hpet - Completer ID of Device Number of Hpet. 0x1F(Default). -**/ - UINT8 HpetDeviceNumber; - -/** Offset 0x00AE - Function Number of Hpet - Completer ID of Function Number of Hpet. 0x00(Default). -**/ - UINT8 HpetFunctionNumber; - -/** Offset 0x00AF -**/ - UINT32 UnusedUpdSpace1; - -/** Offset 0x00B3 - IoApic Valid BDF Value - Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 IoApicBdfValid; - -/** Offset 0x00B4 - Bus Number of IoApic - Completer ID of Bus Number of IoApic. 0xFA(Default). -**/ - UINT8 IoApicBusNumber; - -/** Offset 0x00B5 - Device Number of IoApic - Completer ID of Device Number of IoApic. 0x0F(Default). -**/ - UINT8 IoApicDeviceNumber; - -/** Offset 0x00B6 - Function Number of IoApic - Completer ID of Function Number of IoApic. 0x00(Default). -**/ - UINT8 IoApicFunctionNumber; - -/** Offset 0x00B7 - IOAPIC Entry 24-119 - Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IoApicEntry24_119; - -/** Offset 0x00B8 - IO APIC ID - This member determines IOAPIC ID. 0x01(Default). -**/ - UINT8 IoApicId; - -/** Offset 0x00B9 - IoApic Range - Define address bits 19:12 for the IOxAPIC range. 0x00(Default). -**/ - UINT8 IoApicRangeSelect; - -/** Offset 0x00BA - ISH Controller - Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 IshEnable; - -/** Offset 0x00BB - BIOS Interface Lock Down - Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control - Register. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 BiosInterface; - -/** Offset 0x00BC - Bios LockDown Enable - Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 BiosLock; - -/** Offset 0x00BD - SPI EISS Status - Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SpiEiss; - -/** Offset 0x00BE - BiosLock SWSMI Number - This member describes the SwSmi value for Bios Lock. 0xA9(Default). -**/ - UINT8 BiosLockSwSmiNumber; - -/** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable - Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 LPSS_S0ixEnable; - -/** Offset 0x00C0 - LPSS I2C Clock Gating Configuration - Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 I2cClkGateCfg[8]; - -/** Offset 0x00C8 - PSS HSUART Clock Gating Configuration - Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 HsuartClkGateCfg[4]; - -/** Offset 0x00CC - LPSS SPI Clock Gating Configuration - Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). -**/ - UINT8 SpiClkGateCfg[3]; - -/** Offset 0x00CF - I2C Device 0 - Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c0Enable; - -/** Offset 0x00D0 - I2C Device 1 - Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c1Enable; - -/** Offset 0x00D1 - I2C Device 2 - Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c2Enable; - -/** Offset 0x00D2 - I2C Device 3 - Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c3Enable; - -/** Offset 0x00D3 - I2C Device 4 - Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c4Enable; - -/** Offset 0x00D4 - I2C Device 5 - Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c5Enable; - -/** Offset 0x00D5 - I2C Device 6 - Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c6Enable; - -/** Offset 0x00D6 - I2C Device 7 - Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 I2c7Enable; - -/** Offset 0x00D7 - UART Device 0 - Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart0Enable; - -/** Offset 0x00D8 - UART Device 1 - Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart1Enable; - -/** Offset 0x00D9 - UART Device 2 - Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart2Enable; - -/** Offset 0x00DA - UART Device 3 - Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Hsuart3Enable; - -/** Offset 0x00DB - SPI UART Device 0 - Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi0Enable; - -/** Offset 0x00DC - SPI UART Device 1 - Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi1Enable; - -/** Offset 0x00DD - SPI UART Device 2 - Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. - 0: Disabled, 1: PCI Mode, 2: ACPI Mode -**/ - UINT8 Spi2Enable; - -/** Offset 0x00DE - UART Debug Base Address - UART Debug Base Address. 0x00000000(Default). -**/ - UINT32 Uart2KernelDebugBaseAddress; - -/** Offset 0x00E2 - OS Debug Feature - Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. - $EN_DIS -**/ - UINT8 OsDbgEnable; - -/** Offset 0x00E3 - DCI Feature - Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable. - $EN_DIS -**/ - UINT8 DciEn; - -/** Offset 0x00E4 - Enable PCIE Clock Gating - Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). - 0:Enable, 1:Disable -**/ - UINT8 PcieClockGatingDisabled; - -/** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode - Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 PcieRootPort8xhDecode; - -/** Offset 0x00E6 - PCIE 8xh Decode Port Index - PCIE 8xh Decode Port Index. 0x00(Default). -**/ - UINT8 Pcie8xhDecodePortIndex; - -/** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write - Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PcieRootPortPeerMemoryWriteEnable; - -/** Offset 0x00E8 - PCIE SWSMI Number - This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). -**/ - UINT8 PcieAspmSwSmiNumber; - -/** Offset 0x00E9 - PCI Express Root Port - Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRootPortEn[6]; - -/** Offset 0x00EF - Hide PCIE Root Port Configuration Space - Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpHide[6]; - -/** Offset 0x00F5 - PCIE Root Port Slot Implement - Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpSlotImplemented[6]; - -/** Offset 0x00FB - Hot Plug - PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpHotPlug[6]; - -/** Offset 0x0101 - PCIE PM SCI - Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpPmSci[6]; - -/** Offset 0x0107 - PCIE Root Port Extended Sync - Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpExtSync[6]; - -/** Offset 0x010D - Transmitter Half Swing - Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpTransmitterHalfSwing[6]; - -/** Offset 0x0113 - ACS - Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpAcsEnabled[6]; - -/** Offset 0x0119 - Clock Request Support - Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpClkReqSupported[6]; - -/** Offset 0x011F - Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, - 0x01, 0x02, 0x03. -**/ - UINT8 PcieRpClkReqNumber[6]; - -/** Offset 0x0125 - CLKREQ# Detection - Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. -**/ - UINT8 PcieRpClkReqDetect[6]; - -/** Offset 0x012B - Advanced Error Reporting - Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. -**/ - UINT8 AdvancedErrorReporting[6]; - -/** Offset 0x0131 - PME Interrupt - Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. -**/ - UINT8 PmeInterrupt[6]; - -/** Offset 0x0137 - URR - PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 UnsupportedRequestReport[6]; - -/** Offset 0x013D - FER - PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 FatalErrorReport[6]; - -/** Offset 0x0143 - NFER - PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 NoFatalErrorReport[6]; - -/** Offset 0x0149 - CER - PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 CorrectableErrorReport[6]; - -/** Offset 0x014F - SEFE - Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnFatalError[6]; - -/** Offset 0x0155 - SENFE - Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnNonFatalError[6]; - -/** Offset 0x015B - SECE - Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SystemErrorOnCorrectableError[6]; - -/** Offset 0x0161 - PCIe Speed - Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. -**/ - UINT8 PcieRpSpeed[6]; - -/** Offset 0x0167 - Physical Slot Number - Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. -**/ - UINT8 PhysicalSlotNumber[6]; - -/** Offset 0x016D - CTO - Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpCompletionTimeout[6]; - -/** Offset 0x0173 - PTM Support - Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. -**/ - UINT8 PtmEnable[6]; - -/** Offset 0x0179 - ASPM - PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, - 4:Auto(Default). -**/ - UINT8 PcieRpAspm[6]; - -/** Offset 0x017F - L1 Substates - PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). -**/ - UINT8 PcieRpL1Substates[6]; - -/** Offset 0x0185 - PCH PCIe LTR - PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpLtrEnable[6]; - -/** Offset 0x018B - PCIE LTR Lock - PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. -**/ - UINT8 PcieRpLtrConfigLock[6]; - -/** Offset 0x0191 - PME_B0_S5 Disable bit - PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PmeB0S5Dis; - -/** Offset 0x0192 - PCI Clock Run - This member describes whether or not the PCI ClockRun feature of SC should be enabled. - 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 PciClockRun; - -/** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting - Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 Timer8254ClkSetting; - -/** Offset 0x0194 - Chipset SATA - Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports - the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 EnableSata; - -/** Offset 0x0195 - SATA Mode Selection - Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x0196 - Aggressive LPM Support - Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x0197 - SATA Power Optimization - Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x0198 - eSATA Speed Limit - Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 eSATASpeedLimit; - -/** Offset 0x0199 - SATA Speed Limit - SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). - 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) -**/ - UINT8 SpeedLimit; - -/** Offset 0x019A - SATA Port - Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). -**/ - UINT8 SataPortsEnable[2]; - -/** Offset 0x019C - SATA Port DevSlp - Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsDevSlp[2]; - -/** Offset 0x019E - SATA Port HotPlug - Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsHotPlug[2]; - -/** Offset 0x01A0 - Mechanical Presence Switch - Controls reporting if this port has an Mechanical Presence Switch.\n - Note:Requires hardware support. 0:Disable, 1:Enable(Default). -**/ - UINT8 SataPortsInterlockSw[2]; - -/** Offset 0x01A2 - External SATA Ports - Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsExternal[2]; - -/** Offset 0x01A4 - Spin Up Device - Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsSpinUp[2]; - -/** Offset 0x01A6 - SATA Solid State - Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard - Disk Drive(Default), 1:Solid State Drive. -**/ - UINT8 SataPortsSolidStateDrive[2]; - -/** Offset 0x01A8 - DITO Configuration - Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. -**/ - UINT8 SataPortsEnableDitoConfig[2]; - -/** Offset 0x01AA - DM Value - DM Value. 0:Minimum, 0x0F:Maximum(Default). -**/ - UINT8 SataPortsDmVal[2]; - -/** Offset 0x01AC - DITO Value - DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). -**/ - UINT16 SataPortsDitoVal[2]; - -/** Offset 0x01B0 - Subsystem Vendor ID - Subsystem Vendor ID. 0x8086(Default). -**/ - UINT16 SubSystemVendorId; - -/** Offset 0x01B2 - Subsystem ID - Subsystem ID. 0x7270(Default). -**/ - UINT16 SubSystemId; - -/** Offset 0x01B4 -**/ - UINT8 UnusedUpdSpace2[10]; - -/** Offset 0x01BE - CRIDSettings - PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. -**/ - UINT8 CRIDSettings; - -/** Offset 0x01BF - ResetSelect - ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. -**/ - UINT8 ResetSelect; - -/** Offset 0x01C0 - SD Card Support (D27:F0) - Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SdcardEnabled; - -/** Offset 0x01C1 - SeMMC Support (D28:F0) - Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 eMMCEnabled; - -/** Offset 0x01C2 - eMMC Max Speed - Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. - 0:HS400, 1: HS200, 2:DDR50 -**/ - UINT8 eMMCHostMaxSpeed; - -/** Offset 0x01C3 - UFS Support (D29:F0) - Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 UfsEnabled; - -/** Offset 0x01C4 - SDIO Support (D30:F0) - Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SdioEnabled; - -/** Offset 0x01C5 - GPP Lock Feature - Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 GppLock; - -/** Offset 0x01C6 - Serial IRQ - Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SirqEnable; - -/** Offset 0x01C7 - Serial IRQ Mode - Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. - $EN_DIS -**/ - UINT8 SirqMode; - -/** Offset 0x01C8 - Start Frame Pulse Width - Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. - 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk -**/ - UINT8 StartFramePulse; - -/** Offset 0x01C9 - Enable SMBus - Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x01CA - SMBus ARP Support - Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 ArpEnable; - -/** Offset 0x01CB -**/ - UINT16 UnusedUpdSpace3; - -/** Offset 0x01CD - SMBus Table Elements - The number of elements in the Reserved SMBus Address Table. 0x0080(Default). -**/ - UINT16 NumRsvdSmbusAddresses; - -/** Offset 0x01CF - Reserved SMBus Address Table - Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). -**/ - UINT8 RsvdSmbusAddressTable[128]; - -/** Offset 0x024F - XHCI Disable Compliance Mode - Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance - Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. - $EN_DIS -**/ - UINT8 DisableComplianceMode; - -/** Offset 0x0250 - USB Per-Port Control - Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 UsbPerPortCtl; - -/** Offset 0x0251 - xHCI Mode - Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Usb30Mode; - -/** Offset 0x0252 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. 0x01(Default). -**/ - UINT8 PortUsb20Enable[8]; - -/** Offset 0x025A - USB20 Over Current Pin - Over Current Pin number of USB 2.0 Port. 0x00(Default). -**/ - UINT8 PortUs20bOverCurrentPin[8]; - -/** Offset 0x0262 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. 0x01(Default). -**/ - UINT8 PortUsb30Enable[6]; - -/** Offset 0x0268 - USB20 Over Current Pin - Over Current Pin number of USB 3.0 Port. 0x01(Default). -**/ - UINT8 PortUs30bOverCurrentPin[6]; - -/** Offset 0x026E - XDCI Support - Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. - 0:Disable, 1:PCI_Mode, 2:ACPI_mode -**/ - UINT8 UsbOtg; - -/** Offset 0x026F - Enable XHCI HSIC Support - Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 HsicSupportEnable; - -/** Offset 0x0270 - Enable XHCI SSIC Support - Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for - port1. 0x00(Default). -**/ - UINT8 SsicPortEnable[2]; - -/** Offset 0x0272 - SSIC Dlane PowerGating - Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT16 DlanePwrGating; - -/** Offset 0x0274 - VT-d - Enable/Disable VT-d. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 VtdEnable; - -/** Offset 0x0275 - HDAudio Delay Timer - The delay timer after Azalia reset. 0x012C(Default). -**/ - UINT16 ResetWaitTimer; - -/** Offset 0x0277 - SMI Lock bit - Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, - 1:Enable(Default). - $EN_DIS -**/ - UINT8 LockDownGlobalSmi; - -/** Offset 0x0278 - RTC Lock Bits - Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 RtcLock; - -/** Offset 0x0279 - XHCI SSIC RATE - Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. -**/ - UINT8 SsicRate[2]; - -/** Offset 0x027B - SATA Test Mode Selection - Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x027C - SMBus Dynamic Power Gating - Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. - $EN_DIS -**/ - UINT16 DynamicPowerGating; - -/** Offset 0x027E - Max Snoop Latency - Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). -**/ - UINT16 PcieRpLtrMaxSnoopLatency[6]; - -/** Offset 0x028A - Snoop Latency Override - Snoop Latency Override for PCH PCIE. \n - Disabled:Disable override.\n - Manual:Manually enter override values.\n - Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[6]; - -/** Offset 0x0290 - Snoop Latency Value - LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[6]; - -/** Offset 0x029C - Snoop Latency Multiplier - LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, - 4:1048576ns, 5:33554432ns. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[6]; - -/** Offset 0x02A2 - Max Non-Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). -**/ - UINT16 PcieRpLtrMaxNonSnoopLatency[6]; - -/** Offset 0x02AE - Non Snoop Latency Override - Non Snoop Latency Override for PCH PCIE. \n - Disabled:Disable override.\n - Manual:Manually enter override values.\n - Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[6]; - -/** Offset 0x02B4 - Non Snoop Latency Value - LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[6]; - -/** Offset 0x02C0 - Non Snoop Latency Multiplier - LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), - 3:32768ns, 4:1048576ns, 5:33554432ns. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6]; - -/** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale - Specifies scale used for slot power limit value. 0x00(Default). -**/ - UINT8 PcieRpSlotPowerLimitScale[6]; - -/** Offset 0x02CC - PCIE Root Port Slot Power Limit Value - Specifies upper limit on power supplie by slot. 0x00(Default). -**/ - UINT8 PcieRpSlotPowerLimitValue[6]; - -/** Offset 0x02D2 - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize(Default), 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x02D3 - DCI Auto Detect - Enable/disable DCI AUTO mode. Enabled(Default). - $EN_DIS -**/ - UINT8 DciAutoDetect; - -/** Offset 0x02D4 - Halt and Lock TCO Timer - Halt and Lock the TCO Timer (Watchdog). - 0:No, 1:Yes (default) -**/ - UINT8 TcoTimerHaltLock; - -/** Offset 0x02D5 - Power Button Override Period - specifies how long will PMC wait before initiating a global reset. 000b-4s(default), - 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) - 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s -**/ - UINT8 PwrBtnOverridePeriod; - -/** Offset 0x02D6 - Power Button Native Mode Disable - Disable power button native mode, when 1, this will result in the PMC logic constantly - seeing the power button as de-asserted. 0 (default)) - $EN_DIS -**/ - UINT8 DisableNativePowerButton; - -/** Offset 0x02D7 - Power Button Debounce Mode - Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default) - $EN_DIS -**/ - UINT8 PowerButterDebounceMode; - -/** Offset 0x02D8 - SDIO_TX_CMD_DLL_CNTL - SDIO_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 SdioTxCmdCntl; - -/** Offset 0x02DC - SDIO_TX_DATA_DLL_CNTL1 - SDIO_TX_DATA_DLL_CNTL1. 0xE(Default). -**/ - UINT32 SdioTxDataCntl1; - -/** Offset 0x02E0 - SDIO_TX_DATA_DLL_CNTL2 - SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default). -**/ - UINT32 SdioTxDataCntl2; - -/** Offset 0x02E4 - SDIO_RX_CMD_DATA_DLL_CNTL1 - SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default). -**/ - UINT32 SdioRxCmdDataCntl1; - -/** Offset 0x02E8 - SDIO_RX_CMD_DATA_DLL_CNTL2 - SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). -**/ - UINT32 SdioRxCmdDataCntl2; - -/** Offset 0x02EC - SDCARD_TX_CMD_DLL_CNTL - SDCARD_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 SdcardTxCmdCntl; - -/** Offset 0x02F0 - SDCARD_TX_DATA_DLL_CNTL1 - SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default). -**/ - UINT32 SdcardTxDataCntl1; - -/** Offset 0x02F4 - SDCARD_TX_DATA_DLL_CNTL2 - SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default). -**/ - UINT32 SdcardTxDataCntl2; - -/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL1 - SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default). -**/ - UINT32 SdcardRxCmdDataCntl1; - -/** Offset 0x02FC - SDCARD_RX_STROBE_DLL_CNTL - SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default). -**/ - UINT32 SdcardRxStrobeCntl; - -/** Offset 0x0300 - SDCARD_RX_CMD_DATA_DLL_CNTL2 - SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). -**/ - UINT32 SdcardRxCmdDataCntl2; - -/** Offset 0x0304 - EMMC_TX_CMD_DLL_CNTL - EMMC_TX_CMD_DLL_CNTL. 0x505(Default). -**/ - UINT32 EmmcTxCmdCntl; - -/** Offset 0x0308 - EMMC_TX_DATA_DLL_CNTL1 - EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default). -**/ - UINT32 EmmcTxDataCntl1; - -/** Offset 0x030C - EMMC_TX_DATA_DLL_CNTL2 - EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default). -**/ - UINT32 EmmcTxDataCntl2; - -/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL1 - EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default). -**/ - UINT32 EmmcRxCmdDataCntl1; - -/** Offset 0x0314 - EMMC_RX_STROBE_DLL_CNTL - EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default). -**/ - UINT32 EmmcRxStrobeCntl; - -/** Offset 0x0318 - EMMC_RX_CMD_DATA_DLL_CNTL2 - EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default). -**/ - UINT32 EmmcRxCmdDataCntl2; - -/** Offset 0x031C - EMMC_MASTER_DLL_CNTL - EMMC_MASTER_DLL_CNTL. 0x001(Default). -**/ - UINT32 EmmcMasterSwCntl; - -/** Offset 0x0320 - PCIe Selectable De-emphasis - When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis - for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). -**/ - UINT8 PcieRpSelectableDeemphasis[6]; - -/** Offset 0x0326 -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x0327 - Monitor Mwait Enable - Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux - based OS, this should be Disabled. 0:Disable, 1:Enable(Default). - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x0328 -**/ - UINT8 ReservedFspsUpd[8]; -} FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x0330 -**/ - UINT32 Signature; - -/** Offset 0x0334 -**/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; - -/** Fsp S Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0340 -**/ - UINT32 Signature; - -/** Offset 0x0344 -**/ - UINT8 ReservedFspsRestrictedUpd[12]; -} FSP_S_RESTRICTED_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x0330 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0340 -**/ - FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; - -/** Offset 0x0350 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack(pop) - -#endif diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 5561363..f7a68d7 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -18,7 +18,7 @@ #include <stddef.h> #include <stdint.h> -#include <soc/fsp/FspmUpd.h> +#include <FspmUpd.h> /* * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 7a19e69..7f31247 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -19,7 +19,7 @@ #include <smbios.h> #include <soc/meminit.h> #include <stddef.h> /* required for FspmUpd.h */ -#include <soc/fsp/FspmUpd.h> +#include <FspmUpd.h> #include <string.h> static void set_lpddr4_defaults(FSP_M_CONFIG *cfg) diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h new file mode 100644 index 0000000..a7114ce --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(push, 1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h new file mode 100644 index 0000000..48225e0 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h @@ -0,0 +1,721 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +#define MAX_CHANNELS_NUM 4 +#define MAX_DIMMS_NUM 1 + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + UINT8 ModulePartNum[20]; +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT8 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT16 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Debug Serial Port Base address + Debug serial port base address. This option will be used only when the 'Serial Port + Debug Device' option is set to 'External Device'. 0x00000000(Default). +**/ + UINT32 SerialDebugPortAddress; + +/** Offset 0x0044 - Debug Serial Port Type + 16550 compatible debug serial port resource type. NONE means no serial port support. + 0x02:MMIO(Default). + 0:NONE, 1:I/O, 2:MMIO +**/ + UINT8 SerialDebugPortType; + +/** Offset 0x0045 - Serial Port Debug Device + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port + Base' options will be ignored. 0x02:SOC UART2(Default). + 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device +**/ + UINT8 SerialDebugPortDevice; + +/** Offset 0x0046 - Debug Serial Port Stride Size + Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). + 0:1, 2:4 +**/ + UINT8 SerialDebugPortStrideSize; + +/** Offset 0x0047 - Memory Fast Boot + Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x0048 - Integrated Graphics Device + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video + Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). + $EN_DIS +**/ + UINT8 Igd; + +/** Offset 0x0049 - DVMT Pre-Allocated + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal + Graphics Device. 0x02:64 MB(Default). + 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 + MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, + 0x0F:480 MB, 0x10:512 MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x004A - Aperture Size + Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), + 0x2:256 MB, 0x3:512 MB. + 0x1:128 MB, 0x2:256 MB, 0x3:512 MB +**/ + UINT8 IgdApertureSize; + +/** Offset 0x004B - GTT Size + Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 + MB(Default). + 0x1:2 MB, 0x2:4 MB, 0x3:8 MB +**/ + UINT8 GttSize; + +/** Offset 0x004C - Primary Display + Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), + 0x2:IGD, 0x3:PCI + 0x0:AUTO, 0x2:IGD, 0x3:PCI +**/ + UINT8 PrimaryVideoAdaptor; + +/** Offset 0x004D - Package + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L + is being used. 0x00(Default). + 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD +**/ + UINT8 Package; + +/** Offset 0x004E - Profile + Profile list. 0x19(Default). + 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, + 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, + 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, + 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, + 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, + 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, + 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, + 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, + 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, + 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, + 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, + 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 +**/ + UINT8 Profile; + +/** Offset 0x004F - MemoryDown + Memory Down. 0x0(Default). + 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 +**/ + UINT8 MemoryDown; + +/** Offset 0x0050 - DDR3LPageSize + NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB. + 0x1:1KB, 0x2:2KB +**/ + UINT8 DDR3LPageSize; + +/** Offset 0x0051 - DDR3LASR + NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported. + 0x0:Not Supported, 0x1:Supported +**/ + UINT8 DDR3LASR; + +/** Offset 0x0052 - ScramblerSupport + Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default). + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x0053 - ChannelHashMask + Channel Hash Mask. 0x00(Default). +**/ + UINT16 ChannelHashMask; + +/** Offset 0x0055 - SliceHashMask + Slice Hash Mask. 0x00(Default). +**/ + UINT16 SliceHashMask; + +/** Offset 0x0057 - InterleavedMode + Interleaved Mode. 0x00:Disable(Default), 0x02:Enable. + 0x0:Disable, 0x2:Enable +**/ + UINT8 InterleavedMode; + +/** Offset 0x0058 - ChannelsSlicesEnable + Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 ChannelsSlicesEnable; + +/** Offset 0x0059 - MinRefRate2xEnable + Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), + 0x01:Enable. + $EN_DIS +**/ + UINT8 MinRefRate2xEnable; + +/** Offset 0x005A - DualRankSupportEnable + Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). + $EN_DIS +**/ + UINT8 DualRankSupportEnable; + +/** Offset 0x005B - RmtMode + Rank Margin Tool Mode. 0x00(Default). + $EN_DIS +**/ + UINT8 RmtMode; + +/** Offset 0x005C - MemorySizeLimit + Memory Size Limit: This value is used to restrict the total amount of memory and + the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, + 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) +**/ + UINT16 MemorySizeLimit; + +/** Offset 0x005E - LowMemoryMaxValue + Low Memory Max Value: This value is used to restrict the amount of memory below + 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 + = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). +**/ + UINT16 LowMemoryMaxValue; + +/** Offset 0x0060 - DisableFastBoot + 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train + of memory. + $EN_DIS +**/ + UINT8 DisableFastBoot; + +/** Offset 0x0061 - HighMemoryMaxValue + High Memory Max Value: This value is used to restrict the amount of memory above + 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, + 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). +**/ + UINT16 HighMemoryMaxValue; + +/** Offset 0x0063 - DIMM0SPDAddress + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). +**/ + UINT8 DIMM0SPDAddress; + +/** Offset 0x0064 - DIMM1SPDAddress + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). +**/ + UINT8 DIMM1SPDAddress; + +/** Offset 0x0065 - Ch0_RankEnable + NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default). +**/ + UINT8 Ch0_RankEnable; + +/** Offset 0x0066 - Ch0_DeviceWidth + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + UINT8 Ch0_DeviceWidth; + +/** Offset 0x0067 - Ch0_DramDensity + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + UINT8 Ch0_DramDensity; + +/** Offset 0x0068 - Ch0_Option + Rank Select Interleaving Enable. See Address Mapping section for full description. + 0:Rank Select Interleaving disabled, 1:Rank Select Interleaving enabled. [1] Bank + Address Hashing Enable. See Address Mapping section for full description. 0:Bank + Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] + This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). + 0x03(Default). +**/ + UINT8 Ch0_Option; + +/** Offset 0x0069 - Ch0_OdtConfig + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. +**/ + UINT8 Ch0_OdtConfig; + +/** Offset 0x006A - Ch0_TristateClk1 + Parameter used to determine whether to tristate CLK1. 0x00(Default). +**/ + UINT8 Ch0_TristateClk1; + +/** Offset 0x006B - Ch0_Mode2N + 2N Mode. 0x00(Default). +**/ + UINT8 Ch0_Mode2N; + +/** Offset 0x006C - Ch0_OdtLevels + Rank Select Interleaving Enable. See Address Mapping section for full description. + 0:Rank Select Interleaving disabled(Default), 1:Rank Select Interleaving enabled. + [1] Bank Address Hashing Enable. See Address Mapping section for full description. + 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). +**/ + UINT8 Ch0_OdtLevels; + +/** Offset 0x006D - Ch1_RankEnable + NOTE: Only for memory down. Set to 1 to enable Ch1 rank. +**/ + UINT8 Ch1_RankEnable; + +/** Offset 0x006E - Ch1_DeviceWidth + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + UINT8 Ch1_DeviceWidth; + +/** Offset 0x006F - Ch1_DramDensity + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default). + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + UINT8 Ch1_DramDensity; + +/** Offset 0x0070 - Ch1_Option + Rank Select Interleaving Enable. See Address Mapping section for full description. + 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] + Bank Address Hashing Enable. See Address Mapping section for full description. + 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB + (B), 0x03(Default). +**/ + UINT8 Ch1_Option; + +/** Offset 0x0071 - Ch1_OdtConfig + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. +**/ + UINT8 Ch1_OdtConfig; + +/** Offset 0x0072 - Ch1_TristateClk1 + Parameter used to determine whether to tristate CLK1. 0x00(Default). +**/ + UINT8 Ch1_TristateClk1; + +/** Offset 0x0073 - Ch1_Mode2N + 2N Mode. 0x00(Default). +**/ + UINT8 Ch1_Mode2N; + +/** Offset 0x0074 - Ch1_OdtLevels + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), + 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. +**/ + UINT8 Ch1_OdtLevels; + +/** Offset 0x0075 - Ch2_RankEnable + NOTE: Only for memory down. Set to 1 to enable Ch2 rank. +**/ + UINT8 Ch2_RankEnable; + +/** Offset 0x0076 - Ch2_DeviceWidth + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + UINT8 Ch2_DeviceWidth; + +/** Offset 0x0077 - Ch2_DramDensity + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + UINT8 Ch2_DramDensity; + +/** Offset 0x0078 - Ch2_Option + Rank Select Interleaving Enable. See Address Mapping section for full description.. + 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] + Bank Address Hashing Enable. See Address Mapping section for full description.. + 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). + 01:2KB (B). +**/ + UINT8 Ch2_Option; + +/** Offset 0x0079 - Ch2_OdtConfig + ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. +**/ + UINT8 Ch2_OdtConfig; + +/** Offset 0x007A - Ch2_TristateClk1 + Parameter used to determine whether to tristate CLK1. 0x00(Default). +**/ + UINT8 Ch2_TristateClk1; + +/** Offset 0x007B - Ch2_Mode2N + 2N Mode. 0x00(Default). +**/ + UINT8 Ch2_Mode2N; + +/** Offset 0x007C - Ch2_OdtLevels + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), + 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. +**/ + UINT8 Ch2_OdtLevels; + +/** Offset 0x007D - Ch3_RankEnable + NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default). +**/ + UINT8 Ch3_RankEnable; + +/** Offset 0x007E - Ch3_DeviceWidth + NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), + 0x01:x16, 0x02:x32, 0x03:x64. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + UINT8 Ch3_DeviceWidth; + +/** Offset 0x007F - Ch3_DramDensity + NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), + 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + UINT8 Ch3_DramDensity; + +/** Offset 0x0080 - Ch3_Option + Rank Select Interleaving Enable. See Address Mapping section for full description.. + 0 - Rank Select Interleaving disabled. 1 - Rank Select Interleaving enabled. [1] + Bank Address Hashing Enable. See Address Mapping section for full description.. + 0 - Bank Address Hashing disabled. 1 - Bank Address Hashing enabled. [3:2] Reserved. + [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 + - 2KB (B). +**/ + UINT8 Ch3_Option; + +/** Offset 0x0081 - Ch3_OdtConfig + ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG. +**/ + UINT8 Ch3_OdtConfig; + +/** Offset 0x0082 - Ch3_TristateClk1 + Parameter used to determine whether to tristate CLK1. 0x00(Default). +**/ + UINT8 Ch3_TristateClk1; + +/** Offset 0x0083 - Ch3_Mode2N + 2N Mode. 0x00(Default). +**/ + UINT8 Ch3_Mode2N; + +/** Offset 0x0084 - Ch3_OdtLevels + Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), + 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. +**/ + UINT8 Ch3_OdtLevels; + +/** Offset 0x0085 - RmtCheckRun + RmtCheckRun: 0x00(Default). +**/ + UINT8 RmtCheckRun; + +/** Offset 0x0086 - Ch0_Bit_swizzling + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + UINT8 Ch0_Bit_swizzling[32]; + +/** Offset 0x00A6 - Ch1_Bit_swizzling + Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + UINT8 Ch1_Bit_swizzling[32]; + +/** Offset 0x00C6 - Ch2_Bit_swizzling + Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + UINT8 Ch2_Bit_swizzling[32]; + +/** Offset 0x00E6 - Ch3_Bit_swizzling + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + UINT8 Ch3_Bit_swizzling[32]; + +/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold + RmtMarginCheckScaleHighThreshold. 0x0000(Default). +**/ + UINT16 RmtMarginCheckScaleHighThreshold; + +/** Offset 0x0108 - MsgLevelMask + MsgLevelMask. 0x00000000(Default). +**/ + UINT32 MsgLevelMask; + +/** Offset 0x010C +**/ + UINT32 UnusedUpdSpace0; + +/** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4 + Number of Entries in PreMem GPIO Table. 0(Default). +**/ + UINT8 PreMemGpioTableEntryNum; + +/** Offset 0x0111 - PreMem GPIO Pin Number for each table + Number of Pins in each PreMem GPIO Table. 0(Default). +**/ + UINT8 PreMemGpioTablePinNum[4]; + +/** Offset 0x0115 - PreMem GPIO Table Pointer + Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default). +**/ + UINT32 PreMemGpioTablePtr; + +/** Offset 0x0119 - Enhance the port 8xh decoding + Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 EnhancePort8xhDecoding; + +/** Offset 0x011A - OEM File Loading Address + Determine the memory base address to load a specified file from CSE file system + after memory is available. +**/ + UINT32 OemLoadingBase; + +/** Offset 0x011E - OEM File Name to Load + Specify a file name to load from CSE file system after memory is available. Empty + indicates no file needs to be loaded. +**/ + UINT8 OemFileName[16]; + +/** Offset 0x012E - SPD Data Write + Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 SpdWriteEnable; + +/** Offset 0x012F - MRC Training Data Saving + Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 MrcDataSaving; + +/** Offset 0x0130 - eMMC Trace Length + Select eMMC trace length to load OEM file from when loading OEM file name is specified. + 0x0:Long(Default), 0x1:Short. + 0x0:Long, 0x1:Short +**/ + UINT8 eMMCTraceLen; + +/** Offset 0x0131 +**/ + VOID* MrcBootDataPtr; + +/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB + Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of + CSE. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 SkipCseRbp; + +/** Offset 0x0136 - Npk Enable + Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default). + 0:Disable, 1:Enable, 2:Debugger, 3:Auto +**/ + UINT8 NpkEn; + +/** Offset 0x0137 - FW Trace Enable + Enable/Disable FW Trace. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 FwTraceEn; + +/** Offset 0x0138 - FW Trace Destination + FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB, + 4-NPK_TRACE_TO_PTI(Default). +**/ + UINT8 FwTraceDestination; + +/** Offset 0x0139 - NPK Recovery Dump + Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 RecoverDump; + +/** Offset 0x013A - Memory Region 0 Buffer WrapAround + Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + UINT8 Msc0Wrap; + +/** Offset 0x013B - Memory Region 1 Buffer WrapAround + Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + UINT8 Msc1Wrap; + +/** Offset 0x013C - Memory Region 0 Buffer Size + Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, + 6-512MB, 7-1GB. +**/ + UINT32 Msc0Size; + +/** Offset 0x0140 - Memory Region 1 Buffer Size + Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, + 6-512MB, 7-1GB. +**/ + UINT32 Msc1Size; + +/** Offset 0x0144 - PTI Mode + PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. +**/ + UINT8 PtiMode; + +/** Offset 0x0145 - PTI Training + PTI Training. 0-off(Default), 1-6=1-6. +**/ + UINT8 PtiTraining; + +/** Offset 0x0146 - PTI Speed + PTI Speed. 0-full, 1-half, 2-quarter(Default). +**/ + UINT8 PtiSpeed; + +/** Offset 0x0147 - Punit Message Level + Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. +**/ + UINT8 PunitMlvl; + +/** Offset 0x0148 - PMC Message Level + PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. +**/ + UINT8 PmcMlvl; + +/** Offset 0x0149 - SW Trace Enable + Enable/Disable SW Trace. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 SwTraceEn; + +/** Offset 0x014A - Periodic Retraining Disable + Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + UINT8 PeriodicRetrainingDisable; + +/** Offset 0x014B +**/ + UINT8 ReservedFspmUpd[5]; +} FSP_M_CONFIG; + +/** Fsp M Test Configuration +**/ +typedef struct { + +/** Offset 0x0150 +**/ + UINT32 Signature; + +/** Offset 0x0154 +**/ + UINT8 ReservedFspmTestUpd[28]; +} FSP_M_TEST_CONFIG; + +/** Fsp M Restricted Configuration +**/ +typedef struct { + +/** Offset 0x0170 +**/ + UINT32 Signature; + +/** Offset 0x0174 +**/ + UINT8 ReservedFspmRestrictedUpd[138]; +} FSP_M_RESTRICTED_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0150 +**/ + FSP_M_TEST_CONFIG FspmTestConfig; + +/** Offset 0x0170 +**/ + FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; + +/** Offset 0x01FE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h new file mode 100644 index 0000000..553eba3 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h @@ -0,0 +1,1541 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - ActiveProcessorCores + Number of active cores. 0:Disable(Default), 1:Enable. +**/ + UINT8 ActiveProcessorCores; + +/** Offset 0x0021 - Disable Core1 + Disable/Enable Core1. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DisableCore1; + +/** Offset 0x0022 - Disable Core2 + Disable/Enable Core2. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DisableCore2; + +/** Offset 0x0023 - Disable Core3 + Disable/Enable Core3. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DisableCore3; + +/** Offset 0x0024 - VMX Enable + Enable or Disable VMX. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x0025 - Memory region allocation for Processor Trace + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to + 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default) +**/ + UINT8 ProcTraceMemSize; + +/** Offset 0x0026 - Enable Processor Trace + Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 ProcTraceEnable; + +/** Offset 0x0027 - Eist + Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x0028 - Boot PState + Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. +**/ + UINT8 BootPState; + +/** Offset 0x0029 - CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 EnableCx; + +/** Offset 0x002A - Enhanced C-states + Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 C1e; + +/** Offset 0x002B - Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 BiProcHot; + +/** Offset 0x002C - Max Pkg Cstate + Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, + 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. +**/ + UINT8 PkgCStateLimit; + +/** Offset 0x002D +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x002E - C-State auto-demotion + C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 + Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion + to C1 and C3. +**/ + UINT8 CStateAutoDemotion; + +/** Offset 0x002F - C-State un-demotion + C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, + 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. +**/ + UINT8 CStateUnDemotion; + +/** Offset 0x0030 - Max Core C-State + Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). +**/ + UINT8 MaxCoreCState; + +/** Offset 0x0031 - Package C-State Demotion + Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PkgCStateDemotion; + +/** Offset 0x0032 - Package C-State Un-demotion + Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PkgCStateUnDemotion; + +/** Offset 0x0033 - Turbo Mode + Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x0034 - SC HDA Verb Table Entry Number + Number of Entries in Verb Table. 0(Default). +**/ + UINT8 HdaVerbTableEntryNum; + +/** Offset 0x0035 - SC HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. 0x00000000(Default). +**/ + UINT32 HdaVerbTablePtr; + +/** Offset 0x0039 - Enable/Disable P2SB device hidden. + Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 P2sbUnhide; + +/** Offset 0x003A - IPU Enable/Disable + Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 IpuEn; + +/** Offset 0x003B - IMGU ACPI mode selection + 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. + 0:Disable, 1:IGFX Child device, 2:ACPI device +**/ + UINT8 IpuAcpiMode; + +/** Offset 0x003C - GttMmAdr + GttMmAdr structure for initialization. 0xBF000000(Default). +**/ + UINT32 GttMmAdr; + +/** Offset 0x0040 - GmAdr + GmAdr structure for initialization. 0xA0000000(Default). +**/ + UINT32 GmAdr; + +/** Offset 0x0044 - Enable ForceWake + Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 ForceWake; + +/** Offset 0x0045 - Enable PavpLock + Enable/disable PavpLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PavpLock; + +/** Offset 0x0046 - Enable GraphicsFreqModify + Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 GraphicsFreqModify; + +/** Offset 0x0047 - Enable GraphicsFreqReq + Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 GraphicsFreqReq; + +/** Offset 0x0048 - Enable GraphicsVideoFreq + Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 GraphicsVideoFreq; + +/** Offset 0x0049 - Enable PmLock + Enable/disable PmLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PmLock; + +/** Offset 0x004A - Enable DopClockGating + Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 DopClockGating; + +/** Offset 0x004B - Enable UnsolicitedAttackOverride + Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 UnsolicitedAttackOverride; + +/** Offset 0x004C - Enable WOPCMSupport + Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 WOPCMSupport; + +/** Offset 0x004D - Enable WOPCMSize + Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 WOPCMSize; + +/** Offset 0x004E - Enable PowerGating + Enable/disable PowerGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PowerGating; + +/** Offset 0x004F - Enable UnitLevelClockGating + Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 UnitLevelClockGating; + +/** Offset 0x0050 - Enable FastBoot + Enable/disable FastBoot. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 FastBoot; + +/** Offset 0x0051 - Enable DynSR + Enable/disable DynSR. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 DynSR; + +/** Offset 0x0052 - Enable SaIpuEnable + Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x0053 - BMP Logo Data Size + BMP logo data buffer size. 0x00000000(Default). +**/ + UINT32 LogoSize; + +/** Offset 0x0057 - BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. 0x00000000(Default). +**/ + UINT32 LogoPtr; + +/** Offset 0x005B - Graphics Configuration Data Pointer + Graphics configuration data used for initialization. 0x00000000(Default). +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x005F - GT PM Support + Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PmSupport; + +/** Offset 0x0060 - RC6(Render Standby) + Enable/Disable render standby support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 EnableRenderStandby; + +/** Offset 0x0061 - PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PavpEnable; + +/** Offset 0x0062 - PAVP PR3 + Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PavpPr3; + +/** Offset 0x0063 - CdClock Frequency selection + 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +**/ + UINT8 CdClock; + +/** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit + Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x0065 - Write Protection Support + Enable/disable Write Protection. 0:Disable, 1:Enable(Default). +**/ + UINT8 WriteProtectionEnable[5]; + +/** Offset 0x006A - Read Protection Support + Enable/disable Read Protection. 0:Disable, 1:Enable(Default). +**/ + UINT8 ReadProtectionEnable[5]; + +/** Offset 0x006F - Protected Range Limitation + The address of the upper limit of protection, 0x0FFFh(Default). +**/ + UINT16 ProtectedRangeLimit[5]; + +/** Offset 0x0079 - Protected Range Base + The base address of the upper limit of protection. 0x0000(Default). +**/ + UINT16 ProtectedRangeBase[5]; + +/** Offset 0x0083 - Enable SC Gaussian Mixture Models + Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 Gmm; + +/** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk + Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingPgcbClkTrunk; + +/** Offset 0x0085 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingSb; + +/** Offset 0x0086 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingSbClkTrunk; + +/** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition + Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingSbClkPartition; + +/** Offset 0x0088 - GMM Clock Gating - Core + Enable/disable Core. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingCore; + +/** Offset 0x0089 - GMM Clock Gating - DMA + Enable/disable DMA. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingDma; + +/** Offset 0x008A - GMM Clock Gating - Register Access + Enable/disable Register Access. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingRegAccess; + +/** Offset 0x008B - GMM Clock Gating - Host + Enable/disable Host. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingHost; + +/** Offset 0x008C - GMM Clock Gating - Partition + Enable/disable Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingPartition; + +/** Offset 0x008D - Clock Gating - Trunk + Enable/disable Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ClkGatingTrunk; + +/** Offset 0x008E - HD Audio Support + Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 HdaEnable; + +/** Offset 0x008F - HD Audio DSP Support + Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DspEnable; + +/** Offset 0x0090 - Azalia wake-on-ring + Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 Pme; + +/** Offset 0x0091 - HD-Audio I/O Buffer Ownership + Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default) + 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and + I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers +**/ + UINT8 HdAudioIoBufferOwnership; + +/** Offset 0x0092 - HD-Audio I/O Buffer Voltage + HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. + 0: 3.3V, 1: 1.8V +**/ + UINT8 HdAudioIoBufferVoltage; + +/** Offset 0x0093 - HD-Audio Virtual Channel Type + HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. + 0: VC0, 1: VC1 +**/ + UINT8 HdAudioVcType; + +/** Offset 0x0094 - HD-Audio Link Frequency + HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, + 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + UINT8 HdAudioLinkFrequency; + +/** Offset 0x0095 - HD-Audio iDisp-Link Frequency + HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, + 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + UINT8 HdAudioIDispLinkFrequency; + +/** Offset 0x0096 - HD-Audio iDisp-Link T-Mode + HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. + 0: 2T, 1: 1T +**/ + UINT8 HdAudioIDispLinkTmode; + +/** Offset 0x0097 - HD-Audio Disp DMIC + HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. + 0: Disable, 1: 2ch array, 2: 4ch array +**/ + UINT8 DspEndpointDmic; + +/** Offset 0x0098 - HD-Audio Bluetooth + Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 DspEndpointBluetooth; + +/** Offset 0x0099 - HD-Audio I2S SHK + Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 DspEndpointI2sSkp; + +/** Offset 0x009A - HD-Audio I2S HP + Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 DspEndpointI2sHp; + +/** Offset 0x009B - HD-Audio Controller Power Gating + Enable/Disable HD-Audio Controller Power Gating. This option is deprecated. + $EN_DIS +**/ + UINT8 AudioCtlPwrGate; + +/** Offset 0x009C - HD-Audio ADSP Power Gating + Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated. + $EN_DIS +**/ + UINT8 AudioDspPwrGate; + +/** Offset 0x009D - HD-Audio CSME Memory Transfers + Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + UINT8 Mmt; + +/** Offset 0x009E - HD-Audio Host Memory Transfers + Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + UINT8 Hmt; + +/** Offset 0x009F - HD-Audio BIOS Configuration Lock Down + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 BiosCfgLockDown; + +/** Offset 0x00A0 - HD-Audio Power Gating + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 HDAudioPwrGate; + +/** Offset 0x00A1 - HD-Audio Clock Gatingn + Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 HDAudioClkGate; + +/** Offset 0x00A2 - Bitmask of DSP Feature + Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] + - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: + Intel WoV, 1: Windows Voice Activation +**/ + UINT32 DspFeatureMask; + +/** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules + Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] + - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: + Intel WoV, 1: Windows Voice Activation +**/ + UINT32 DspPpModuleMask; + +/** Offset 0x00AA - Enable High Precision Timer + Enable/Disable Hpet. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 Hpet; + +/** Offset 0x00AB - Hpet Valid BDF Value + Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 HpetBdfValid; + +/** Offset 0x00AC - Bus Number of Hpet + Completer ID of Bus Number of Hpet. Default = 0xFA(Default). +**/ + UINT8 HpetBusNumber; + +/** Offset 0x00AD - Device Number of Hpet + Completer ID of Device Number of Hpet. 0x1F(Default). +**/ + UINT8 HpetDeviceNumber; + +/** Offset 0x00AE - Function Number of Hpet + Completer ID of Function Number of Hpet. 0x00(Default). +**/ + UINT8 HpetFunctionNumber; + +/** Offset 0x00AF +**/ + UINT32 UnusedUpdSpace1; + +/** Offset 0x00B3 - IoApic Valid BDF Value + Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 IoApicBdfValid; + +/** Offset 0x00B4 - Bus Number of IoApic + Completer ID of Bus Number of IoApic. 0xFA(Default). +**/ + UINT8 IoApicBusNumber; + +/** Offset 0x00B5 - Device Number of IoApic + Completer ID of Device Number of IoApic. 0x0F(Default). +**/ + UINT8 IoApicDeviceNumber; + +/** Offset 0x00B6 - Function Number of IoApic + Completer ID of Function Number of IoApic. 0x00(Default). +**/ + UINT8 IoApicFunctionNumber; + +/** Offset 0x00B7 - IOAPIC Entry 24-119 + Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 IoApicEntry24_119; + +/** Offset 0x00B8 - IO APIC ID + This member determines IOAPIC ID. 0x01(Default). +**/ + UINT8 IoApicId; + +/** Offset 0x00B9 - IoApic Range + Define address bits 19:12 for the IOxAPIC range. 0x00(Default). +**/ + UINT8 IoApicRangeSelect; + +/** Offset 0x00BA - ISH Controller + Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 IshEnable; + +/** Offset 0x00BB - BIOS Interface Lock Down + Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control + Register. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 BiosInterface; + +/** Offset 0x00BC - Bios LockDown Enable + Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 BiosLock; + +/** Offset 0x00BD - SPI EISS Status + Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SpiEiss; + +/** Offset 0x00BE - BiosLock SWSMI Number + This member describes the SwSmi value for Bios Lock. 0xA9(Default). +**/ + UINT8 BiosLockSwSmiNumber; + +/** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable + Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 LPSS_S0ixEnable; + +/** Offset 0x00C0 - LPSS I2C Clock Gating Configuration + Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). +**/ + UINT8 I2cClkGateCfg[8]; + +/** Offset 0x00C8 - PSS HSUART Clock Gating Configuration + Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). +**/ + UINT8 HsuartClkGateCfg[4]; + +/** Offset 0x00CC - LPSS SPI Clock Gating Configuration + Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). +**/ + UINT8 SpiClkGateCfg[3]; + +/** Offset 0x00CF - I2C Device 0 + Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c0Enable; + +/** Offset 0x00D0 - I2C Device 1 + Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c1Enable; + +/** Offset 0x00D1 - I2C Device 2 + Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c2Enable; + +/** Offset 0x00D2 - I2C Device 3 + Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c3Enable; + +/** Offset 0x00D3 - I2C Device 4 + Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c4Enable; + +/** Offset 0x00D4 - I2C Device 5 + Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c5Enable; + +/** Offset 0x00D5 - I2C Device 6 + Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c6Enable; + +/** Offset 0x00D6 - I2C Device 7 + Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 I2c7Enable; + +/** Offset 0x00D7 - UART Device 0 + Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Hsuart0Enable; + +/** Offset 0x00D8 - UART Device 1 + Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Hsuart1Enable; + +/** Offset 0x00D9 - UART Device 2 + Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Hsuart2Enable; + +/** Offset 0x00DA - UART Device 3 + Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Hsuart3Enable; + +/** Offset 0x00DB - SPI UART Device 0 + Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Spi0Enable; + +/** Offset 0x00DC - SPI UART Device 1 + Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Spi1Enable; + +/** Offset 0x00DD - SPI UART Device 2 + Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + UINT8 Spi2Enable; + +/** Offset 0x00DE - UART Debug Base Address + UART Debug Base Address. 0x00000000(Default). +**/ + UINT32 Uart2KernelDebugBaseAddress; + +/** Offset 0x00E2 - OS Debug Feature + Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + UINT8 OsDbgEnable; + +/** Offset 0x00E3 - DCI Feature + Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x00E4 - Enable PCIE Clock Gating + Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). + 0:Enable, 1:Disable +**/ + UINT8 PcieClockGatingDisabled; + +/** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode + Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 PcieRootPort8xhDecode; + +/** Offset 0x00E6 - PCIE 8xh Decode Port Index + PCIE 8xh Decode Port Index. 0x00(Default). +**/ + UINT8 Pcie8xhDecodePortIndex; + +/** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write + Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PcieRootPortPeerMemoryWriteEnable; + +/** Offset 0x00E8 - PCIE SWSMI Number + This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). +**/ + UINT8 PcieAspmSwSmiNumber; + +/** Offset 0x00E9 - PCI Express Root Port + Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRootPortEn[6]; + +/** Offset 0x00EF - Hide PCIE Root Port Configuration Space + Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. +**/ + UINT8 PcieRpHide[6]; + +/** Offset 0x00F5 - PCIE Root Port Slot Implement + Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpSlotImplemented[6]; + +/** Offset 0x00FB - Hot Plug + PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpHotPlug[6]; + +/** Offset 0x0101 - PCIE PM SCI + Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. +**/ + UINT8 PcieRpPmSci[6]; + +/** Offset 0x0107 - PCIE Root Port Extended Sync + Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpExtSync[6]; + +/** Offset 0x010D - Transmitter Half Swing + Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpTransmitterHalfSwing[6]; + +/** Offset 0x0113 - ACS + Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpAcsEnabled[6]; + +/** Offset 0x0119 - Clock Request Support + Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpClkReqSupported[6]; + +/** Offset 0x011F - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, + 0x01, 0x02, 0x03. +**/ + UINT8 PcieRpClkReqNumber[6]; + +/** Offset 0x0125 - CLKREQ# Detection + Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. +**/ + UINT8 PcieRpClkReqDetect[6]; + +/** Offset 0x012B - Advanced Error Reporting + Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. +**/ + UINT8 AdvancedErrorReporting[6]; + +/** Offset 0x0131 - PME Interrupt + Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. +**/ + UINT8 PmeInterrupt[6]; + +/** Offset 0x0137 - URR + PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 UnsupportedRequestReport[6]; + +/** Offset 0x013D - FER + PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 FatalErrorReport[6]; + +/** Offset 0x0143 - NFER + PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 NoFatalErrorReport[6]; + +/** Offset 0x0149 - CER + PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 CorrectableErrorReport[6]; + +/** Offset 0x014F - SEFE + Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 SystemErrorOnFatalError[6]; + +/** Offset 0x0155 - SENFE + Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 SystemErrorOnNonFatalError[6]; + +/** Offset 0x015B - SECE + Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + UINT8 SystemErrorOnCorrectableError[6]; + +/** Offset 0x0161 - PCIe Speed + Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. +**/ + UINT8 PcieRpSpeed[6]; + +/** Offset 0x0167 - Physical Slot Number + Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. +**/ + UINT8 PhysicalSlotNumber[6]; + +/** Offset 0x016D - CTO + Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. +**/ + UINT8 PcieRpCompletionTimeout[6]; + +/** Offset 0x0173 - PTM Support + Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. +**/ + UINT8 PtmEnable[6]; + +/** Offset 0x0179 - ASPM + PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, + 4:Auto(Default). +**/ + UINT8 PcieRpAspm[6]; + +/** Offset 0x017F - L1 Substates + PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). +**/ + UINT8 PcieRpL1Substates[6]; + +/** Offset 0x0185 - PCH PCIe LTR + PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpLtrEnable[6]; + +/** Offset 0x018B - PCIE LTR Lock + PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. +**/ + UINT8 PcieRpLtrConfigLock[6]; + +/** Offset 0x0191 - PME_B0_S5 Disable bit + PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PmeB0S5Dis; + +/** Offset 0x0192 - PCI Clock Run + This member describes whether or not the PCI ClockRun feature of SC should be enabled. + 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 PciClockRun; + +/** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting + Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 Timer8254ClkSetting; + +/** Offset 0x0194 - Chipset SATA + Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports + the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 EnableSata; + +/** Offset 0x0195 - SATA Mode Selection + Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x0196 - Aggressive LPM Support + Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x0197 - SATA Power Optimization + Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x0198 - eSATA Speed Limit + Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 eSATASpeedLimit; + +/** Offset 0x0199 - SATA Speed Limit + SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). + 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) +**/ + UINT8 SpeedLimit; + +/** Offset 0x019A - SATA Port + Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). +**/ + UINT8 SataPortsEnable[2]; + +/** Offset 0x019C - SATA Port DevSlp + Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsDevSlp[2]; + +/** Offset 0x019E - SATA Port HotPlug + Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsHotPlug[2]; + +/** Offset 0x01A0 - Mechanical Presence Switch + Controls reporting if this port has an Mechanical Presence Switch.\n + Note:Requires hardware support. 0:Disable, 1:Enable(Default). +**/ + UINT8 SataPortsInterlockSw[2]; + +/** Offset 0x01A2 - External SATA Ports + Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsExternal[2]; + +/** Offset 0x01A4 - Spin Up Device + Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsSpinUp[2]; + +/** Offset 0x01A6 - SATA Solid State + Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard + Disk Drive(Default), 1:Solid State Drive. +**/ + UINT8 SataPortsSolidStateDrive[2]; + +/** Offset 0x01A8 - DITO Configuration + Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. +**/ + UINT8 SataPortsEnableDitoConfig[2]; + +/** Offset 0x01AA - DM Value + DM Value. 0:Minimum, 0x0F:Maximum(Default). +**/ + UINT8 SataPortsDmVal[2]; + +/** Offset 0x01AC - DITO Value + DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). +**/ + UINT16 SataPortsDitoVal[2]; + +/** Offset 0x01B0 - Subsystem Vendor ID + Subsystem Vendor ID. 0x8086(Default). +**/ + UINT16 SubSystemVendorId; + +/** Offset 0x01B2 - Subsystem ID + Subsystem ID. 0x7270(Default). +**/ + UINT16 SubSystemId; + +/** Offset 0x01B4 +**/ + UINT8 UnusedUpdSpace2[10]; + +/** Offset 0x01BE - CRIDSettings + PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. +**/ + UINT8 CRIDSettings; + +/** Offset 0x01BF - ResetSelect + ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. +**/ + UINT8 ResetSelect; + +/** Offset 0x01C0 - SD Card Support (D27:F0) + Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SdcardEnabled; + +/** Offset 0x01C1 - SeMMC Support (D28:F0) + Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 eMMCEnabled; + +/** Offset 0x01C2 - eMMC Max Speed + Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. + 0:HS400, 1: HS200, 2:DDR50 +**/ + UINT8 eMMCHostMaxSpeed; + +/** Offset 0x01C3 - UFS Support (D29:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 UfsEnabled; + +/** Offset 0x01C4 - SDIO Support (D30:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SdioEnabled; + +/** Offset 0x01C5 - GPP Lock Feature + Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 GppLock; + +/** Offset 0x01C6 - Serial IRQ + Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SirqEnable; + +/** Offset 0x01C7 - Serial IRQ Mode + Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. + $EN_DIS +**/ + UINT8 SirqMode; + +/** Offset 0x01C8 - Start Frame Pulse Width + Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. + 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk +**/ + UINT8 StartFramePulse; + +/** Offset 0x01C9 - Enable SMBus + Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x01CA - SMBus ARP Support + Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 ArpEnable; + +/** Offset 0x01CB +**/ + UINT16 UnusedUpdSpace3; + +/** Offset 0x01CD - SMBus Table Elements + The number of elements in the Reserved SMBus Address Table. 0x0080(Default). +**/ + UINT16 NumRsvdSmbusAddresses; + +/** Offset 0x01CF - Reserved SMBus Address Table + Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). +**/ + UINT8 RsvdSmbusAddressTable[128]; + +/** Offset 0x024F - XHCI Disable Compliance Mode + Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance + Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. + $EN_DIS +**/ + UINT8 DisableComplianceMode; + +/** Offset 0x0250 - USB Per-Port Control + Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 UsbPerPortCtl; + +/** Offset 0x0251 - xHCI Mode + Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 Usb30Mode; + +/** Offset 0x0252 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. 0x01(Default). +**/ + UINT8 PortUsb20Enable[8]; + +/** Offset 0x025A - USB20 Over Current Pin + Over Current Pin number of USB 2.0 Port. 0x00(Default). +**/ + UINT8 PortUs20bOverCurrentPin[8]; + +/** Offset 0x0262 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. 0x01(Default). +**/ + UINT8 PortUsb30Enable[6]; + +/** Offset 0x0268 - USB20 Over Current Pin + Over Current Pin number of USB 3.0 Port. 0x01(Default). +**/ + UINT8 PortUs30bOverCurrentPin[6]; + +/** Offset 0x026E - XDCI Support + Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. + 0:Disable, 1:PCI_Mode, 2:ACPI_mode +**/ + UINT8 UsbOtg; + +/** Offset 0x026F - Enable XHCI HSIC Support + Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 HsicSupportEnable; + +/** Offset 0x0270 - Enable XHCI SSIC Support + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for + port1. 0x00(Default). +**/ + UINT8 SsicPortEnable[2]; + +/** Offset 0x0272 - SSIC Dlane PowerGating + Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT16 DlanePwrGating; + +/** Offset 0x0274 - VT-d + Enable/Disable VT-d. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 VtdEnable; + +/** Offset 0x0275 - HDAudio Delay Timer + The delay timer after Azalia reset. 0x012C(Default). +**/ + UINT16 ResetWaitTimer; + +/** Offset 0x0277 - SMI Lock bit + Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, + 1:Enable(Default). + $EN_DIS +**/ + UINT8 LockDownGlobalSmi; + +/** Offset 0x0278 - RTC Lock Bits + Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 RtcLock; + +/** Offset 0x0279 - XHCI SSIC RATE + Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. +**/ + UINT8 SsicRate[2]; + +/** Offset 0x027B - SATA Test Mode Selection + Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 SataTestMode; + +/** Offset 0x027C - SMBus Dynamic Power Gating + Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT16 DynamicPowerGating; + +/** Offset 0x027E - Max Snoop Latency + Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). +**/ + UINT16 PcieRpLtrMaxSnoopLatency[6]; + +/** Offset 0x028A - Snoop Latency Override + Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). +**/ + UINT8 PcieRpSnoopLatencyOverrideMode[6]; + +/** Offset 0x0290 - Snoop Latency Value + LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + UINT16 PcieRpSnoopLatencyOverrideValue[6]; + +/** Offset 0x029C - Snoop Latency Multiplier + LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, + 4:1048576ns, 5:33554432ns. +**/ + UINT8 PcieRpSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02A2 - Max Non-Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). +**/ + UINT16 PcieRpLtrMaxNonSnoopLatency[6]; + +/** Offset 0x02AE - Non Snoop Latency Override + Non Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMode[6]; + +/** Offset 0x02B4 - Non Snoop Latency Value + LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + UINT16 PcieRpNonSnoopLatencyOverrideValue[6]; + +/** Offset 0x02C0 - Non Snoop Latency Multiplier + LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), + 3:32768ns, 4:1048576ns, 5:33554432ns. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale + Specifies scale used for slot power limit value. 0x00(Default). +**/ + UINT8 PcieRpSlotPowerLimitScale[6]; + +/** Offset 0x02CC - PCIE Root Port Slot Power Limit Value + Specifies upper limit on power supplie by slot. 0x00(Default). +**/ + UINT8 PcieRpSlotPowerLimitValue[6]; + +/** Offset 0x02D2 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize(Default), 1: Skip + $EN_DIS +**/ + UINT8 SkipMpInit; + +/** Offset 0x02D3 - DCI Auto Detect + Enable/disable DCI AUTO mode. Enabled(Default). + $EN_DIS +**/ + UINT8 DciAutoDetect; + +/** Offset 0x02D4 - Halt and Lock TCO Timer + Halt and Lock the TCO Timer (Watchdog). + 0:No, 1:Yes (default) +**/ + UINT8 TcoTimerHaltLock; + +/** Offset 0x02D5 - Power Button Override Period + specifies how long will PMC wait before initiating a global reset. 000b-4s(default), + 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) + 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s +**/ + UINT8 PwrBtnOverridePeriod; + +/** Offset 0x02D6 - Power Button Native Mode Disable + Disable power button native mode, when 1, this will result in the PMC logic constantly + seeing the power button as de-asserted. 0 (default)) + $EN_DIS +**/ + UINT8 DisableNativePowerButton; + +/** Offset 0x02D7 - Power Button Debounce Mode + Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default) + $EN_DIS +**/ + UINT8 PowerButterDebounceMode; + +/** Offset 0x02D8 - SDIO_TX_CMD_DLL_CNTL + SDIO_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + UINT32 SdioTxCmdCntl; + +/** Offset 0x02DC - SDIO_TX_DATA_DLL_CNTL1 + SDIO_TX_DATA_DLL_CNTL1. 0xE(Default). +**/ + UINT32 SdioTxDataCntl1; + +/** Offset 0x02E0 - SDIO_TX_DATA_DLL_CNTL2 + SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default). +**/ + UINT32 SdioTxDataCntl2; + +/** Offset 0x02E4 - SDIO_RX_CMD_DATA_DLL_CNTL1 + SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default). +**/ + UINT32 SdioRxCmdDataCntl1; + +/** Offset 0x02E8 - SDIO_RX_CMD_DATA_DLL_CNTL2 + SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). +**/ + UINT32 SdioRxCmdDataCntl2; + +/** Offset 0x02EC - SDCARD_TX_CMD_DLL_CNTL + SDCARD_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + UINT32 SdcardTxCmdCntl; + +/** Offset 0x02F0 - SDCARD_TX_DATA_DLL_CNTL1 + SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default). +**/ + UINT32 SdcardTxDataCntl1; + +/** Offset 0x02F4 - SDCARD_TX_DATA_DLL_CNTL2 + SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default). +**/ + UINT32 SdcardTxDataCntl2; + +/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL1 + SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default). +**/ + UINT32 SdcardRxCmdDataCntl1; + +/** Offset 0x02FC - SDCARD_RX_STROBE_DLL_CNTL + SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default). +**/ + UINT32 SdcardRxStrobeCntl; + +/** Offset 0x0300 - SDCARD_RX_CMD_DATA_DLL_CNTL2 + SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). +**/ + UINT32 SdcardRxCmdDataCntl2; + +/** Offset 0x0304 - EMMC_TX_CMD_DLL_CNTL + EMMC_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + UINT32 EmmcTxCmdCntl; + +/** Offset 0x0308 - EMMC_TX_DATA_DLL_CNTL1 + EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default). +**/ + UINT32 EmmcTxDataCntl1; + +/** Offset 0x030C - EMMC_TX_DATA_DLL_CNTL2 + EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default). +**/ + UINT32 EmmcTxDataCntl2; + +/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL1 + EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default). +**/ + UINT32 EmmcRxCmdDataCntl1; + +/** Offset 0x0314 - EMMC_RX_STROBE_DLL_CNTL + EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default). +**/ + UINT32 EmmcRxStrobeCntl; + +/** Offset 0x0318 - EMMC_RX_CMD_DATA_DLL_CNTL2 + EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default). +**/ + UINT32 EmmcRxCmdDataCntl2; + +/** Offset 0x031C - EMMC_MASTER_DLL_CNTL + EMMC_MASTER_DLL_CNTL. 0x001(Default). +**/ + UINT32 EmmcMasterSwCntl; + +/** Offset 0x0320 - PCIe Selectable De-emphasis + When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis + for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). +**/ + UINT8 PcieRpSelectableDeemphasis[6]; + +/** Offset 0x0326 +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x0327 - Monitor Mwait Enable + Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux + based OS, this should be Disabled. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + UINT8 MonitorMwaitEnable; + +/** Offset 0x0328 +**/ + UINT8 ReservedFspsUpd[8]; +} FSP_S_CONFIG; + +/** Fsp S Test Configuration +**/ +typedef struct { + +/** Offset 0x0330 +**/ + UINT32 Signature; + +/** Offset 0x0334 +**/ + UINT8 ReservedFspsTestUpd[12]; +} FSP_S_TEST_CONFIG; + +/** Fsp S Restricted Configuration +**/ +typedef struct { + +/** Offset 0x0340 +**/ + UINT32 Signature; + +/** Offset 0x0344 +**/ + UINT8 ReservedFspsRestrictedUpd[12]; +} FSP_S_RESTRICTED_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x0330 +**/ + FSP_S_TEST_CONFIG FspsTestConfig; + +/** Offset 0x0340 +**/ + FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; + +/** Offset 0x0350 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack(pop) + +#endif

1 0

Patch set updated for coreboot: src/southbridge: Code formating
by HAOUAS Elyes 31 Aug '16

31 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16291 -gerrit commit a52e9e0ba7f451056f3afc3b93921b3dad27ff22 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Aug 31 19:22:16 2016 +0200 src/southbridge: Code formating Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 4 +- src/southbridge/amd/amd8111/acpi.c | 2 +- src/southbridge/amd/amd8111/amd8111_smbus.h | 12 +- src/southbridge/amd/amd8111/early_ctrl.c | 40 ++-- src/southbridge/amd/amd8111/ide.c | 4 +- src/southbridge/amd/amd8111/reset.c | 22 +- src/southbridge/amd/amd8131/bridge.c | 65 +++--- src/southbridge/amd/amd8132/bridge.c | 157 +++++++------ src/southbridge/amd/amd8151/agp3.c | 2 +- src/southbridge/amd/cimx/sb700/Platform.h | 2 +- src/southbridge/amd/cimx/sb700/reset.c | 2 +- src/southbridge/amd/cimx/sb800/early.c | 4 +- src/southbridge/amd/cimx/sb800/late.c | 54 ++--- src/southbridge/amd/cimx/sb800/reset.c | 2 +- src/southbridge/amd/cimx/sb800/smbus.c | 8 +- src/southbridge/amd/cimx/sb900/cfg.c | 4 +- src/southbridge/amd/cimx/sb900/early.c | 2 +- src/southbridge/amd/cimx/sb900/late.c | 98 ++++---- src/southbridge/amd/cimx/sb900/reset.c | 2 +- src/southbridge/amd/cimx/sb900/smbus.c | 8 +- src/southbridge/amd/common/amd_pci_util.c | 2 +- src/southbridge/amd/cs5535/chipsetinit.c | 4 +- src/southbridge/amd/cs5535/cs5535.c | 14 +- src/southbridge/amd/cs5535/early_setup.c | 4 +- src/southbridge/amd/cs5536/early_setup.c | 4 +- src/southbridge/amd/pi/hudson/acpi/fch.asl | 4 +- src/southbridge/amd/rs690/gfx.c | 62 ++--- src/southbridge/amd/rs690/ht.c | 8 +- src/southbridge/amd/rs690/pcie.c | 2 +- src/southbridge/amd/rs780/early_setup.c | 4 +- src/southbridge/amd/rs780/gfx.c | 121 ++++------ src/southbridge/amd/rs780/rs780.h | 2 +- src/southbridge/amd/sb600/early_setup.c | 2 +- src/southbridge/amd/sb600/hda.c | 4 +- src/southbridge/amd/sb600/sata.c | 2 +- src/southbridge/amd/sb700/Kconfig | 10 - src/southbridge/amd/sb700/bootblock.c | 34 --- src/southbridge/amd/sb700/hda.c | 4 +- src/southbridge/amd/sb700/reset.c | 2 +- src/southbridge/amd/sb700/sm.c | 24 +- src/southbridge/amd/sb800/hda.c | 4 +- src/southbridge/amd/sb800/sata.c | 2 +- src/southbridge/amd/sr5650/early_setup.c | 34 +-- src/southbridge/amd/sr5650/sr5650.c | 4 +- src/southbridge/broadcom/bcm21000/pcie.c | 2 +- src/southbridge/broadcom/bcm5780/nic.c | 12 +- src/southbridge/broadcom/bcm5780/pcie.c | 16 +- src/southbridge/broadcom/bcm5780/pcix.c | 20 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 14 +- src/southbridge/broadcom/bcm5785/chip.h | 8 +- src/southbridge/broadcom/bcm5785/early_setup.c | 236 +++++++++---------- src/southbridge/broadcom/bcm5785/early_smbus.c | 8 +- src/southbridge/broadcom/bcm5785/ide.c | 16 +- src/southbridge/broadcom/bcm5785/lpc.c | 30 +-- src/southbridge/broadcom/bcm5785/reset.c | 24 +- src/southbridge/broadcom/bcm5785/sata.c | 32 +-- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 98 ++++---- src/southbridge/broadcom/bcm5785/smbus.h | 110 ++++----- src/southbridge/broadcom/bcm5785/usb.c | 8 +- src/southbridge/intel/bd82x6x/azalia.c | 4 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 8 +- src/southbridge/intel/bd82x6x/reset.c | 4 +- src/southbridge/intel/bd82x6x/smihandler.c | 64 +++--- src/southbridge/intel/fsp_bd82x6x/azalia.c | 4 +- src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +- src/southbridge/intel/fsp_bd82x6x/me.c | 2 +- src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 13 +- src/southbridge/intel/fsp_bd82x6x/reset.c | 4 +- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 64 +++--- src/southbridge/intel/fsp_i89xx/lpc.c | 2 +- src/southbridge/intel/fsp_i89xx/me.c | 2 +- src/southbridge/intel/fsp_i89xx/me_8.x.c | 8 +- src/southbridge/intel/fsp_i89xx/romstage.c | 2 +- src/southbridge/intel/fsp_i89xx/smihandler.c | 64 +++--- src/southbridge/intel/fsp_rangeley/gpio.c | 4 +- src/southbridge/intel/fsp_rangeley/lpc.c | 4 +- src/southbridge/intel/i3100/early_smbus.c | 2 +- src/southbridge/intel/i3100/lpc.c | 28 +-- src/southbridge/intel/i3100/sata.c | 2 +- src/southbridge/intel/i82371eb/acpi_tables.c | 2 +- src/southbridge/intel/i82371eb/smbus.h | 6 +- src/southbridge/intel/i82801dx/smihandler.c | 64 +++--- src/southbridge/intel/i82801ex/early_smbus.c | 6 +- src/southbridge/intel/i82801ex/lpc.c | 18 +- src/southbridge/intel/i82801ex/reset.c | 4 +- src/southbridge/intel/i82801ex/smbus.h | 6 +- src/southbridge/intel/i82801ex/watchdog.c | 34 +-- src/southbridge/intel/i82801gx/azalia.c | 4 +- src/southbridge/intel/i82801gx/bootblock.c | 16 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801gx/reset.c | 6 +- src/southbridge/intel/i82801gx/smbus.c | 8 +- src/southbridge/intel/i82801gx/smihandler.c | 64 +++--- src/southbridge/intel/i82801ix/bootblock.c | 16 +- src/southbridge/intel/i82801ix/hdaudio.c | 4 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801ix/smihandler.c | 2 +- src/southbridge/intel/i82870/ioapic.c | 97 ++++---- src/southbridge/intel/i82870/pci_parity.c | 24 +- src/southbridge/intel/i82870/pcibridge.c | 16 +- src/southbridge/intel/ibexpeak/azalia.c | 4 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/ibexpeak/sata.c | 2 +- src/southbridge/intel/ibexpeak/smbus.h | 8 +- src/southbridge/intel/ibexpeak/smihandler.c | 64 +++--- src/southbridge/intel/lynxpoint/hda_verb.c | 4 +- src/southbridge/intel/lynxpoint/lpc.c | 4 +- src/southbridge/intel/lynxpoint/me_9.x.c | 4 +- src/southbridge/intel/lynxpoint/reset.c | 4 +- src/southbridge/intel/lynxpoint/smihandler.c | 64 +++--- src/southbridge/nvidia/ck804/early_setup_car.c | 4 +- src/southbridge/nvidia/mcp55/early_setup_car.c | 2 +- src/southbridge/nvidia/mcp55/nic.c | 16 +- src/southbridge/nvidia/mcp55/sata.c | 2 +- src/southbridge/nvidia/mcp55/smbus.h | 2 +- src/southbridge/ricoh/rl5c476/rl5c476.c | 6 +- src/southbridge/sis/sis966/aza.c | 74 +++--- src/southbridge/sis/sis966/early_setup_car.c | 2 +- src/southbridge/sis/sis966/early_smbus.c | 171 +++++++------- src/southbridge/sis/sis966/ide.c | 35 ++- src/southbridge/sis/sis966/lpc.c | 68 +++--- src/southbridge/sis/sis966/nic.c | 302 ++++++++++++------------- src/southbridge/sis/sis966/sata.c | 53 ++--- src/southbridge/sis/sis966/sis966.c | 22 +- src/southbridge/sis/sis966/usb.c | 40 ++-- src/southbridge/sis/sis966/usb2.c | 61 +++-- src/southbridge/via/k8t890/dram.c | 2 +- src/southbridge/via/vt8237r/smihandler.c | 2 +- 130 files changed, 1548 insertions(+), 1653 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index d7cee4a..7b0232a 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -183,9 +183,9 @@ Method(_INI, 0) { Method(OSFL, 0){ - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - if(CondRefOf(\_OSI)) + if (CondRefOf(\_OSI)) { Store(1, OSVR) /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 396b7c4..2a6cf8d 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -152,7 +152,7 @@ static void acpi_init(struct device *dev) /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); - if(on) { + if (on) { pm10_bar = (pci_read_config16(dev, 0x58)&0xff00); outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); inl(pm10_bar + 0x10); diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 00f8f50..bf0b037 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -26,11 +26,11 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) if ((val & 0x800) == 0) { break; } - if(loops == (SMBUS_TIMEOUT / 2)) { + if (loops == (SMBUS_TIMEOUT / 2)) { outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); } - } while(--loops); + } while (--loops); return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; } @@ -46,7 +46,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) { break; } - } while(--loops); + } while (--loops); return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; } @@ -267,11 +267,11 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned } /* read data block */ - for(i=0; i<msglen && i<bytes; i++) { + for (i=0; i<msglen && i<bytes; i++) { buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff; } /* empty fifo */ - while(bytes++<msglen) { + while (bytes++<msglen) { inw(smbus_io_base + SMBHSTFIFO); } @@ -305,7 +305,7 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne outw(bytes, smbus_io_base + SMBHSTDAT); /* set the data block */ - for(i=0; i<bytes; i++) { + for (i=0; i<bytes; i++) { outw(buf[i], smbus_io_base + SMBHSTFIFO); } diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index ece99ed..d84ef18 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -4,16 +4,16 @@ /* by yhlu 2005.10 */ static unsigned get_sbdn(unsigned bus) { - device_t dev; + device_t dev; - /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), - bus); + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), + bus); - return (dev>>15) & 0x1f; + return (dev>>15) & 0x1f; } @@ -40,34 +40,34 @@ static void enable_cf9(void) void hard_reset(void) { - set_bios_reset(); - /* reset */ - enable_cf9(); - outb(0x0e, 0x0cf9); // make sure cf9 is enabled + set_bios_reset(); + /* reset */ + enable_cf9(); + outb(0x0e, 0x0cf9); // make sure cf9 is enabled } void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - device_t dev; + device_t dev; dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI - pci_write_config8(dev, 0x74, 4); + pci_write_config8(dev, 0x74, 4); - /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ - pci_write_config32(dev, 0x70, 2<<12); + /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ + pci_write_config32(dev, 0x70, 2<<12); } static void soft_reset_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; + device_t dev; dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA - /* Reset */ - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); + /* Reset */ + set_bios_reset(); + pci_write_config8(dev, 0x47, 1); } diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index ef0cee1..a7eee35 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -33,8 +33,8 @@ static void ide_init(struct device *dev) pci_write_config16(dev, 0x40, word); - byte = 0x20 ; // Latency: 64-->32 - pci_write_config8(dev, 0xd, byte); + byte = 0x20 ; // Latency: 64-->32 + pci_write_config8(dev, 0xd, byte); word = 0x0f; pci_write_config16(dev, 0x42, word); diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index 8824550..3cc1a0a 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -12,26 +12,26 @@ static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); } static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); } static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); } #define PCI_DEV_INVALID (0xffffffffU) @@ -40,7 +40,7 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); - for(; dev <= last; dev += PCI_DEV(0,0,1)) { + for (; dev <= last; dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); if (id == pci_id) { diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index 1587268..07f4a6a 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -19,8 +19,7 @@ static void amd8131_walk_children(struct bus *bus, void (*visit)(device_t dev, void *ptr), void *ptr) { device_t child; - for(child = bus->children; child; child = child->sibling) - { + for (child = bus->children; child; child = child->sibling) { if (child->path.type != DEVICE_PATH_PCI) { continue; } @@ -72,7 +71,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) sibs = info->master_devices - 1; /* Count how many sibling functions this device has */ sib_funcs = 0; - for(sib = dev->bus->children; sib; sib = sib->sibling) { + for (sib = dev->bus->children; sib; sib = sib->sibling) { if (sib == dev) { continue; } @@ -258,7 +257,7 @@ static void amd8131_scan_bus(struct bus *bus, /* Don't allow the 8131 or any of it's parent busses to * implement relaxed ordering. Errata #58 */ - for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) { + for (pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) { printk(BIOS_SPEW, "%s disabling relaxed ordering\n", bus_path(pbus)); pbus->disable_relaxed_ordering = 1; @@ -280,57 +279,57 @@ static void amd8131_pcix_init(device_t dev) /* Enable memory write and invalidate ??? */ byte = pci_read_config8(dev, 0x04); - byte |= 0x10; - pci_write_config8(dev, 0x04, byte); + byte |= 0x10; + pci_write_config8(dev, 0x04, byte); /* Set drive strength */ word = pci_read_config16(dev, 0xe0); - word = 0x0404; - pci_write_config16(dev, 0xe0, word); + word = 0x0404; + pci_write_config16(dev, 0xe0, word); word = pci_read_config16(dev, 0xe4); - word = 0x0404; - pci_write_config16(dev, 0xe4, word); + word = 0x0404; + pci_write_config16(dev, 0xe4, word); /* Set impedance */ word = pci_read_config16(dev, 0xe8); - word = 0x0404; - pci_write_config16(dev, 0xe8, word); + word = 0x0404; + pci_write_config16(dev, 0xe8, word); /* Set discard unrequested prefetch data */ /* Errata #51 */ word = pci_read_config16(dev, 0x4c); - word |= 1; - pci_write_config16(dev, 0x4c, word); + word |= 1; + pci_write_config16(dev, 0x4c, word); /* Set split transaction limits */ word = pci_read_config16(dev, 0xa8); - pci_write_config16(dev, 0xaa, word); + pci_write_config16(dev, 0xaa, word); word = pci_read_config16(dev, 0xac); - pci_write_config16(dev, 0xae, word); + pci_write_config16(dev, 0xae, word); /* Set up error reporting, enable all */ /* system error enable */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); - pci_write_config32(dev, 0x04, dword); + dword |= (1<<8); + pci_write_config32(dev, 0x04, dword); /* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); - dword |= (3<<16); - pci_write_config32(dev, 0x3c, dword); + dword |= (3<<16); + pci_write_config32(dev, 0x3c, dword); /* NMI enable */ nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if(nmi_option) { + if (nmi_option) { dword = pci_read_config32(dev, 0x44); - dword |= (1<<0); - pci_write_config32(dev, 0x44, dword); + dword |= (1<<0); + pci_write_config32(dev, 0x44, dword); } /* Set up CRC flood enable */ dword = pci_read_config32(dev, 0xc0); - if(dword) { /* do device A only */ + if (dword) { /* do device A only */ dword = pci_read_config32(dev, 0xc4); dword |= (1<<1); pci_write_config32(dev, 0xc4, dword); @@ -377,22 +376,22 @@ static void bridge_set_resources(struct device *dev) static struct device_operations pcix_ops = { #if BRIDGE_40_BIT_SUPPORT - .read_resources = bridge_read_resources, - .set_resources = bridge_set_resources, + .read_resources = bridge_read_resources, + .set_resources = bridge_set_resources, #else - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, #endif .enable_resources = pci_bus_enable_resources, - .init = amd8131_pcix_init, - .scan_bus = amd8131_scan_bridge, + .init = amd8131_pcix_init, + .scan_bus = amd8131_scan_bridge, .reset_bus = pci_bus_reset, }; static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7450, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7450, }; diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 6979a1e..b546ef3 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -32,8 +32,7 @@ static void amd8132_walk_children(struct bus *bus, void (*visit)(device_t dev, void *ptr), void *ptr) { device_t child; - for(child = bus->children; child; child = child->sibling) - { + for (child = bus->children; child; child = child->sibling) { if (child->path.type != DEVICE_PATH_PCI) { continue; } @@ -126,11 +125,11 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr) cmd |= max_tran << 4; } - /* Don't attempt to handle PCI-X errors */ - cmd &= ~PCI_X_CMD_DPERR_E; - if (orig_cmd != cmd) { - pci_write_config16(dev, cap + PCI_X_CMD, cmd); - } + /* Don't attempt to handle PCI-X errors */ + cmd &= ~PCI_X_CMD_DPERR_E; + if (orig_cmd != cmd) { + pci_write_config16(dev, cap + PCI_X_CMD, cmd); + } } @@ -203,18 +202,18 @@ static void amd8132_pcix_init(device_t dev) unsigned chip_rev; /* Find the revision of the 8132 */ - chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); + chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); /* Enable memory write and invalidate ??? */ dword = pci_read_config32(dev, 0x04); - dword |= 0x10; + dword |= 0x10; dword &= ~(1<<6); // PERSP Parity Error Response - pci_write_config32(dev, 0x04, dword); + pci_write_config32(dev, 0x04, dword); if (chip_rev == 0x01) { /* Errata #37 */ byte = pci_read_config8(dev, 0x0c); - if(byte == 0x08 ) + if (byte == 0x08 ) pci_write_config8(dev, 0x0c, 0x10); #if 0 @@ -229,58 +228,58 @@ static void amd8132_pcix_init(device_t dev) /* Set up error reporting, enable all */ /* system error enable */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); - pci_write_config32(dev, 0x04, dword); + dword |= (1<<8); + pci_write_config32(dev, 0x04, dword); /* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); - dword |= (3<<16); - pci_write_config32(dev, 0x3c, dword); + dword |= (3<<16); + pci_write_config32(dev, 0x3c, dword); - dword = pci_read_config32(dev, 0x40); -// dword &= ~(1<<31); /* WriteChainEnable */ + dword = pci_read_config32(dev, 0x40); +// dword &= ~(1<<31); /* WriteChainEnable */ dword |= (1<<31); dword |= (1<<7);// must set to 1 dword |= (3<<21); //PCIErrorSerrDisable - pci_write_config32(dev, 0x40, dword); + pci_write_config32(dev, 0x40, dword); - /* EXTARB = 1, COMPAT = 0 */ - dword = pci_read_config32(dev, 0x48); - dword |= (1<<3); + /* EXTARB = 1, COMPAT = 0 */ + dword = pci_read_config32(dev, 0x48); + dword |= (1<<3); dword &= ~(1<<0); dword |= (1<<15); //CLEARPCILOG_L dword |= (1<<19); //PERR FATAL Enable dword |= (1<<22); // SERR FATAL Enable dword |= (1<<23); // LPMARBENABLE dword |= (0x61<<24); //LPMARBCOUNT - pci_write_config32(dev, 0x48, dword); + pci_write_config32(dev, 0x48, dword); - dword = pci_read_config32(dev, 0x4c); - dword |= (1<<6); //Initial prefetch for memory read line request + dword = pci_read_config32(dev, 0x4c); + dword |= (1<<6); //Initial prefetch for memory read line request dword |= (1<<9); //continuous prefetch Enable for memory read line request - pci_write_config32(dev, 0x4c, dword); + pci_write_config32(dev, 0x4c, dword); - /* Disable Single-Bit-Error Correction [30] = 0 */ - dword = pci_read_config32(dev, 0x70); - dword &= ~(1<<30); - pci_write_config32(dev, 0x70, dword); + /* Disable Single-Bit-Error Correction [30] = 0 */ + dword = pci_read_config32(dev, 0x70); + dword &= ~(1<<30); + pci_write_config32(dev, 0x70, dword); //link - dword = pci_read_config32(dev, 0xd4); - dword |= (0x5c<<16); - pci_write_config32(dev, 0xd4, dword); + dword = pci_read_config32(dev, 0xd4); + dword |= (0x5c<<16); + pci_write_config32(dev, 0xd4, dword); - /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */ - dword = pci_read_config32(dev, 0xdc); + /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */ + dword = pci_read_config32(dev, 0xdc); dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE - dword |= (1<<18)|(1<<26); - dword &= ~((3<<16)|(3<<24)); - pci_write_config32(dev, 0xdc, dword); + dword |= (1<<18)|(1<<26); + dword &= ~((3<<16)|(3<<24)); + pci_write_config32(dev, 0xdc, dword); /* Set up CRC flood enable */ dword = pci_read_config32(dev, 0xc0); - if(dword) { /* do device A only */ + if (dword) { /* do device A only */ #if 0 dword = pci_read_config32(dev, 0xc4); dword |= (1<<1); @@ -290,12 +289,12 @@ static void amd8132_pcix_init(device_t dev) pci_write_config32(dev, 0xc8, dword); #endif - if (chip_rev == 0x11) { - /* [18] Clock Gate Enable = 1 */ - dword = pci_read_config32(dev, 0xf0); - dword |= 0x00040008; - pci_write_config32(dev, 0xf0, dword); - } + if (chip_rev == 0x11) { + /* [18] Clock Gate Enable = 1 */ + dword = pci_read_config32(dev, 0xf0); + dword |= 0x00040008; + pci_write_config32(dev, 0xf0, dword); + } } return; @@ -337,22 +336,22 @@ static void bridge_set_resources(struct device *dev) static struct device_operations pcix_ops = { #if BRIDGE_40_BIT_SUPPORT - .read_resources = bridge_read_resources, - .set_resources = bridge_set_resources, + .read_resources = bridge_read_resources, + .set_resources = bridge_set_resources, #else - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, #endif .enable_resources = pci_bus_enable_resources, - .init = amd8132_pcix_init, - .scan_bus = amd8132_scan_bridge, + .init = amd8132_pcix_init, + .scan_bus = amd8132_scan_bridge, .reset_bus = pci_bus_reset, }; static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7458, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7458, }; static void ioapic_enable(device_t dev) @@ -369,39 +368,39 @@ static void ioapic_enable(device_t dev) } static void amd8132_ioapic_init(device_t dev) { - uint32_t dword; - unsigned chip_rev; + uint32_t dword; + unsigned chip_rev; - /* Find the revision of the 8132 */ - chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); + /* Find the revision of the 8132 */ + chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); - if (chip_rev == 0x01) { + if (chip_rev == 0x01) { #if 0 - /* Errata #43 */ - dword = pci_read_config32(dev, 0xc8); + /* Errata #43 */ + dword = pci_read_config32(dev, 0xc8); dword |= (0x3<<23); pci_write_config32(dev, 0xc8, dword); #endif - } - - - if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { - //for b1 b2 - /* Errata #73 */ - dword = pci_read_config32(dev, 0x80); - dword |= (0x1f<<5); - pci_write_config32(dev, 0x80, dword); - dword = pci_read_config32(dev, 0x88); - dword |= (0x1f<<5); - pci_write_config32(dev, 0x88, dword); - - /* Errata #74 */ - dword = pci_read_config32(dev, 0x7c); - dword &= ~(0x3<<30); - dword |= (0x01<<30); - pci_write_config32(dev, 0x7c, dword); - } + } + + + if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { + //for b1 b2 + /* Errata #73 */ + dword = pci_read_config32(dev, 0x80); + dword |= (0x1f<<5); + pci_write_config32(dev, 0x80, dword); + dword = pci_read_config32(dev, 0x88); + dword |= (0x1f<<5); + pci_write_config32(dev, 0x88, dword); + + /* Errata #74 */ + dword = pci_read_config32(dev, 0x7c); + dword &= ~(0x3<<30); + dword |= (0x01<<30); + pci_write_config32(dev, 0x7c, dword); + } } diff --git a/src/southbridge/amd/amd8151/agp3.c b/src/southbridge/amd/amd8151/agp3.c index 57699ff..18dd6d5 100644 --- a/src/southbridge/amd/amd8151/agp3.c +++ b/src/southbridge/amd/amd8151/agp3.c @@ -66,7 +66,7 @@ static void agp3dev_enable(device_t dev) } static struct pci_operations pci_ops_pci_dev = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations agp3dev_ops = { diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h index 7562417..7476cb9 100644 --- a/src/southbridge/amd/cimx/sb700/Platform.h +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -62,7 +62,7 @@ void TraceCode ( UINT32 Level, UINT32 Code); #if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL #define TRACE(Arguments) printk Arguments #else - #define TRACE(Arguments) do {} while(0) + #define TRACE(Arguments) do {} while (0) #endif #define TRACECODE(Arguments) #endif diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c index 9a98760..a5c42b7 100644 --- a/src/southbridge/amd/cimx/sb700/reset.c +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -32,7 +32,7 @@ static inline void set_bios_reset(void) int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 2a10c0e..866353d 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -66,6 +66,6 @@ void sb800_clk_output_48Mhz(void) /* AcpiMMioDecodeEn */ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0); - *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 693190f..fa47a96 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -151,21 +151,21 @@ unsigned long acpi_fill_mcfg(unsigned long current) } static struct device_operations lpc_ops = { - .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, - .enable_resources = pci_dev_enable_resources, + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = pci_dev_enable_resources, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .init = lpc_init, - .scan_bus = scan_lpc_bus, - .ops_pci = &lops_pci, + .init = lpc_init, + .scan_bus = scan_lpc_bus, + .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_LPC, + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_LPC, }; static struct device_operations sata_ops = { @@ -226,34 +226,34 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = { static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver azalia_driver __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_HDA, + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_HDA, }; static struct device_operations gec_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver gec_driver __pci_driver = { - .ops = &gec_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_GEC, + .ops = &gec_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_GEC, }; /** diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 9a98760..a5c42b7 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -32,7 +32,7 @@ static inline void set_bios_reset(void) int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 93ac0aa..80395f1 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); return -2; /* not ready */ } @@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); return -2; /* not ready */ } @@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); return -2; /* not ready */ } @@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); return -2; /* not ready */ } diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index be54197..bc7e742 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -28,7 +28,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) { if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); return; } printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n"); @@ -257,7 +257,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) void SbPowerOnInit_Config(AMDSBCFG *sb_config) { if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); + printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); return; } printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n"); diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 10645e1..d39de4b 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -60,7 +60,7 @@ void sb_poweron_init(void) outb(0xEA, 0xCD6); data = inb(0xCD7); data &= !BIT0; - if(!CONFIG_PCIB_ENABLE) { + if (!CONFIG_PCIB_ENABLE) { data |= BIT0; } outb(data, 0xCD7); diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index f078c51..65c2446 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -121,21 +121,21 @@ unsigned long acpi_fill_mcfg(unsigned long current) } static struct device_operations lpc_ops = { - .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, - .enable_resources = lpc_enable_resources, - .init = lpc_init, + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, + .init = lpc_init, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_lpc_bus, - .ops_pci = &lops_pci, + .scan_bus = scan_lpc_bus, + .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_LPC, + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_LPC, }; @@ -239,18 +239,18 @@ static void azalia_init(struct device *dev) } static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = azalia_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_init, + .scan_bus = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver azalia_driver __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_HDA, + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_HDA, }; @@ -263,18 +263,18 @@ static void gec_init(struct device *dev) } static struct device_operations gec_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gec_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gec_init, + .scan_bus = 0, + .ops_pci = &lops_pci, }; static const struct pci_driver gec_driver __pci_driver = { - .ops = &gec_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_GEC, + .ops = &gec_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_GEC, }; @@ -286,19 +286,19 @@ static void pcie_init(device_t dev) } static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, }; static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCI, + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCI, }; @@ -315,30 +315,30 @@ struct device_operations bridge_ops = { /* 0:15:0 PCIe PortA */ static const struct pci_driver PORTA_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIEA, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEA, }; /* 0:15:1 PCIe PortB */ static const struct pci_driver PORTB_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIEB, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEB, }; /* 0:15:2 PCIe PortC */ static const struct pci_driver PORTC_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIEC, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEC, }; /* 0:15:3 PCIe PortD */ static const struct pci_driver PORTD_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIED, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIED, }; diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 9a98760..a5c42b7 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -32,7 +32,7 @@ static inline void set_bios_reset(void) int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c index 358bd48..7d11898 100644 --- a/src/southbridge/amd/cimx/sb900/smbus.c +++ b/src/southbridge/amd/cimx/sb900/smbus.c @@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); return -2; /* not ready */ } @@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); return -2; /* not ready */ } @@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); return -2; /* not ready */ } @@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte; if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); return -2; /* not ready */ } diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index 9756483..b6b2bd3 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -58,7 +58,7 @@ void write_pci_int_table (void) { u8 byte; - if(picr_data_ptr == NULL || intr_data_ptr == NULL){ + if (picr_data_ptr == NULL || intr_data_ptr == NULL){ printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); return; diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index 05fb6eb..a6c0084 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -328,7 +328,7 @@ chipsetinit(void) i = 0; csi = &SB_MASTER_CONF_TABLE[i]; - for(; csi->msrnum; csi++){ + for (; csi->msrnum; csi++){ msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; wrmsr(csi->msrnum, msr); // MSR - see table above @@ -347,7 +347,7 @@ chipsetinit(void) { csi = CS5535_CLOCK_GATING_TABLE; - for(; csi->msrnum; csi++){ + for (; csi->msrnum; csi++){ msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; wrmsr(csi->msrnum, msr); // MSR - see table above diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 70b8386..3f6e48f 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -56,9 +56,9 @@ static void dump_south(struct device *dev) { int i, j; - for(i=0; i<256; i+=16) { + for (i=0; i<256; i+=16) { printk(BIOS_DEBUG, "0x%02x: ", i); - for(j=0; j<16; j++) + for (j=0; j<16; j++) printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j)); printk(BIOS_DEBUG, "\n"); } @@ -103,9 +103,9 @@ static const struct pci_driver cs5535_pci_driver __pci_driver = { }; struct chip_operations southbridge_amd_cs5535_ops = { - CHIP_NAME("AMD Geode CS5535 Southbridge") - /* This is only called when this device is listed in the - * static device tree. - */ - .enable_dev = southbridge_enable, + CHIP_NAME("AMD Geode CS5535 Southbridge") + /* This is only called when this device is listed in the + * static device tree. + */ + .enable_dev = southbridge_enable, }; diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c index 1030aa0..935153f 100644 --- a/src/southbridge/amd/cs5535/early_setup.c +++ b/src/southbridge/amd/cs5535/early_setup.c @@ -34,7 +34,7 @@ static void cs5535_setup_idsel(void) outl(0x1 << (CS5535_DEV_NUM + 10), 0); } -static void cs5535_usb_swapsif(void) +static void cs5535_usb_swapsif (void) { msr_t msr; @@ -133,7 +133,7 @@ static void cs5535_early_setup(void) printk(BIOS_DEBUG, "Setup idsel\n"); cs5535_setup_idsel(); printk(BIOS_DEBUG, "Setup iobase\n"); - cs5535_usb_swapsif(); + cs5535_usb_swapsif (); cs5535_setup_iobase(); printk(BIOS_DEBUG, "Setup gpio\n"); cs5535_setup_gpio(); diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index 013607b..cc427b0 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -42,7 +42,7 @@ static void cs5536_setup_idsel(void) outl(0x1 << (CS5536_DEV_NUM + 10), 0); } -static void cs5536_usb_swapsif(void) +static void cs5536_usb_swapsif (void) { msr_t msr; @@ -260,7 +260,7 @@ static void cs5536_early_setup(void) //printk(BIOS_DEBUG, "Setup idsel\n"); cs5536_setup_idsel(); //printk(BIOS_DEBUG, "Setup iobase\n"); - cs5536_usb_swapsif(); + cs5536_usb_swapsif (); cs5536_setup_iobase(); //printk(BIOS_DEBUG, "Setup gpio\n"); cs5536_setup_gpio(); diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 5a433e6..0426b00 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -165,9 +165,9 @@ Method(_INI, 0) { Method(OSFL, 0){ - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ - if(CondRefOf(\_OSI)) + if (CondRefOf(\_OSI)) { Store(1, OSVR) /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c index 57d6628..bcba435 100644 --- a/src/southbridge/amd/rs690/gfx.c +++ b/src/southbridge/amd/rs690/gfx.c @@ -461,48 +461,48 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) /* done by enable_pci_bar3() before */ /* step 6 SBIOS compile flags */ - if (cfg->gfx_tmds) { - /* step 6.2.2 Clock-Muxing Control */ - /* step 6.2.2.1 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16); + if (cfg->gfx_tmds) { + /* step 6.2.2 Clock-Muxing Control */ + /* step 6.2.2.1 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16); - /* step 6.2.2.2 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10); + /* step 6.2.2.2 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10); - /* step 6.2.2.3 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26); + /* step 6.2.2.3 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26); - /* step 6.2.3 Lane-Muxing Control */ - /* step 6.2.3.1 */ - set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8); + /* step 6.2.3 Lane-Muxing Control */ + /* step 6.2.3.1 */ + set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8); - /* step 6.2.4 Received Data Control */ - /* step 6.2.4.1 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16); + /* step 6.2.4 Received Data Control */ + /* step 6.2.4.1 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16); - /* step 6.2.4.2 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18); + /* step 6.2.4.2 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18); - /* step 6.2.4.3 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20); + /* step 6.2.4.3 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20); - /* step 6.2.4.4 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22); + /* step 6.2.4.4 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22); - /* step 6.2.5 PLL Power Down Control */ - /* step 6.2.5.1 */ - set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6); + /* step 6.2.5 PLL Power Down Control */ + /* step 6.2.5.1 */ + set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6); - /* step 6.2.6 Driving Strength Control */ - /* step 6.2.6.1 */ - set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24); + /* step 6.2.6 Driving Strength Control */ + /* step 6.2.6.1 */ + set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24); - /* step 6.2.6.2 */ - set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); - } + /* step 6.2.6.2 */ + set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); + } - printk(BIOS_INFO, "rs690_gfx_init step6.\n"); + printk(BIOS_INFO, "rs690_gfx_init step6.\n"); /* step 7 compliance state, (only need if CMOS option is enabled) */ /* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */ diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index f4bdf99..bbb33ef 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -52,12 +52,12 @@ static void ht_dev_set_resources(device_t dev) printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n", __func__, dev_path(dev), rbase, rend); k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1)); // find a not assigned resource - for( reg = 0xb8; reg >= 0x80; reg -= 8 ) { + for ( reg = 0xb8; reg >= 0x80; reg -= 8 ) { base = pci_read_config32(k8_f1,reg); limit = pci_read_config32(k8_f1,reg+4); - if( !(base & 3) ) break; // found a not assigned resource + if ( !(base & 3) ) break; // found a not assigned resource } - if( !(base & 3) ) { + if ( !(base & 3) ) { u32 sblk; device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); /* Remember this resource has been stored. */ @@ -90,7 +90,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); // we report mmconf base res = probe_resource(dev, 0x1C); - if( res ) + if ( res ) mmconf_base = res->base; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ? diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index bcf4f4d..043c2ee 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -84,7 +84,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) PCIE_GFX_COMPLIANCE))) { } - if (!cfg->gfx_tmds){ + if (!cfg->gfx_tmds){ /* step 3 Power Down Control for Southbridge */ reg = nbpcie_p_read_index(dev, 0xa2); diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index da98d51..c61493d 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -335,7 +335,7 @@ static void k8_optimization(void) wrmsr(0xC001001F, msr); } #else -#define k8_optimization() do{}while(0) +#define k8_optimization() do {} while (0) #endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 @@ -400,7 +400,7 @@ static void fam10_optimization(void) } } #else -#define fam10_optimization() do{}while(0) +#define fam10_optimization() do {} while (0) #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ /***************************************** diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 6d27d56..78cb837 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -127,12 +127,10 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) { int i; MMIORANGE * TempRange; - for(i=0; i<8; i++) - { - if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) - { + for (i=0; i<8; i++) { + if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) { TempRange = AllocMMIO(pMMIO); - if(TempRange == 0) return 0x80000000; + if (TempRange == 0) return 0x80000000; TempRange->Base = Limit; TempRange->Limit = pMMIO[i].Limit; TempRange->Attribute = pMMIO[i].Attribute; @@ -140,7 +138,7 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) } } TempRange = AllocMMIO(pMMIO); - if(TempRange == 0) return 0x80000000; + if (TempRange == 0) return 0x80000000; TempRange->Base = Base; TempRange->Limit = Limit; TempRange->Attribute = Attribute; @@ -150,32 +148,25 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) static u8 FinalizeMMIO(MMIORANGE *pMMIO) { int i, j, n = 0; - for(i=0; i<8; i++) - { - if (pMMIO[i].Base == pMMIO[i].Limit) - { + for (i=0; i<8; i++) { + if (pMMIO[i].Base == pMMIO[i].Limit) { FreeMMIO(&pMMIO[i]); continue; } - for(j=0; j<i; j++) - { - if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) - { - if (pMMIO[i].Base == pMMIO[j].Limit) - { + for (j=0; j<i; j++) { + if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) { + if (pMMIO[i].Base == pMMIO[j].Limit) { pMMIO[j].Limit = pMMIO[i].Limit; FreeMMIO(&pMMIO[i]); } - if (pMMIO[i].Limit == pMMIO[j].Base) - { + if (pMMIO[i].Limit == pMMIO[j].Base) { pMMIO[j].Base = pMMIO[i].Base; FreeMMIO(&pMMIO[i]); } } } } - for (i=0; i<8; i++) - { + for (i=0; i<8; i++) { if (pMMIO[i].Limit != 0) n++; } return n; @@ -191,29 +182,23 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) Value = pci_read_config32(dev0x14, 0x18); BusStart = (Value >> 8) & 0xFF; BusEnd = (Value >> 16) & 0xFF; - for(Bus = BusStart; Bus <= BusEnd; Bus++) - { - for(Dev = 0; Dev <= 0x1f; Dev++) - { + for (Bus = BusStart; Bus <= BusEnd; Bus++) { + for (Dev = 0; Dev <= 0x1f; Dev++) { tempdev = dev_find_slot(Bus, Dev << 3); Value = pci_read_config32(tempdev, 0); printk(BIOS_DEBUG, "Dev ID %x\n", Value); - if((Value & 0xffff) == 0x1102) - {//Creative + if ((Value & 0xffff) == 0x1102) {//Creative //Found Creative SB u32 MMIOStart = 0xffffffff; u32 MMIOLimit = 0; - for(Reg = 0x10; Reg < 0x20; Reg+=4) - { + for (Reg = 0x10; Reg < 0x20; Reg+=4) { u32 BaseA, LimitA; BaseA = pci_read_config32(tempdev, Reg); Value = BaseA; - if(!(Value & 0x01)) - { + if (!(Value & 0x01)) { Value = Value & 0xffffff00; - if(Value != 0) - { - if(MMIOStart > Value) + if (Value != 0) { + if (MMIOStart > Value) MMIOStart = Value; LimitA = 0xffffffff; //WritePCI(PciAddress,AccWidthUint32,&LimitA); @@ -232,16 +217,14 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) if (MMIOStart < MMIOLimit) { Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO); - if(Status == CIM_ERROR) return Status; + if (Status == CIM_ERROR) return Status; } } } } - if(Status == CIM_SUCCESS) - { + if (Status == CIM_SUCCESS) { //Lets optimize MMIO - if(FinalizeMMIO(pMMIO) > 4) - { + if (FinalizeMMIO(pMMIO) > 4) { Status = CIM_ERROR; } } @@ -256,23 +239,18 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute) k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - for(i = 0; i < 8; i++) - { + for (i = 0; i < 8; i++) { int k = 0, MmioReg; u32 Base = 0; u32 Limit = 0; - for(j = 0; j < 8; j++) - { - if (Base < pMMIO[j].Base) - { + for (j = 0; j < 8; j++) { + if (Base < pMMIO[j].Base) { Base = pMMIO[j].Base; k = j; } } - if(pMMIO[k].Limit != 0) - { - if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) - { + if (pMMIO[k].Limit != 0) { + if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) { Base = 0; } else @@ -366,8 +344,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Clear vgainfo. */ bpointer = (unsigned char *) &vgainfo; - for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) - { + for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) { *bpointer = 0; bpointer++; } @@ -651,8 +628,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* Transfer the Table to VBIOS. */ pointer = (u32 *)&vgainfo; - for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) - { + for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { #if CONFIG_GFXUMA *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i; #else @@ -686,14 +662,12 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* clear MMIO and CreativeMMIO. */ bpointer = (unsigned char *)MMIO; - for(i=0; i<sizeof(MMIO); i++) - { + for (i=0; i<sizeof(MMIO); i++) { *bpointer = 0; bpointer++; } bpointer = (unsigned char *)CreativeMMIO; - for(i=0; i<sizeof(CreativeMMIO); i++) - { + for (i=0; i<sizeof(CreativeMMIO); i++) { *bpointer = 0; bpointer++; } @@ -708,20 +682,18 @@ static void internal_gfx_pci_dev_init(struct device *dev) temp = pci_read_config32(dev0x14, 0x20); Base32 = (temp & 0x0fff0) << 8; Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8; - if(Base32 < Limit32) - { + if (Base32 < Limit32) { Status = GetCreativeMMIO(&CreativeMMIO[0]); - if(Status != CIM_ERROR) + if (Status != CIM_ERROR) SetMMIO(Base32, Limit32, 0x0, &MMIO[0]); } /* Set MMIO for prefetchable P2P. */ - if(Status != CIM_ERROR) - { + if (Status != CIM_ERROR) { temp = pci_read_config32(dev0x14, 0x24); Base32 = (temp & 0x0fff0) <<8; Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8; - if(Base32 < Limit32) + if (Base32 < Limit32) SetMMIO(Base32, Limit32, 0x0, &MMIO[0]); } @@ -835,8 +807,7 @@ static void rs780_internal_gfx_enable(device_t dev) device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4)); - for (i = 0; i < 12; i++) - { + for (i = 0; i < 12; i++) { l_dword = pci_read_config32(k8_f2, 0x40 + i * 4); nbmc_write_index(nb_dev, 0x30 + i, l_dword); } @@ -848,10 +819,8 @@ static void rs780_internal_gfx_enable(device_t dev) set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17); l_dword = pci_read_config32(k8_f2, 0x90); set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18); - if (is_family10h()) - { - for (i = 0; i < 12; i++) - { + if (is_family10h()) { + for (i = 0; i < 12; i++) { l_dword = pci_read_config32(k8_f2, 0x140 + i * 4); nbmc_write_index(nb_dev, 0x3d + i, l_dword); } @@ -974,13 +943,11 @@ static void rs780_internal_gfx_enable(device_t dev) /* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */ /* Init PM timing. */ - for(i=0; i<4; i++) - { + for (i=0; i<4; i++) { l_dword = nbmc_read_index(nb_dev, 0xa0+i); nbmc_write_index(nb_dev, 0xc8+i, l_dword); } - for(i=0; i<4; i++) - { + for (i=0; i<4; i++) { l_dword = nbmc_read_index(nb_dev, 0xa8+i); nbmc_write_index(nb_dev, 0xcc+i, l_dword); } @@ -1538,7 +1505,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); - if((dev->path.pci.devfn >> 3) == 2) { + if ((dev->path.pci.devfn >> 3) == 2) { single_port_configuration(nb_dev, dev); } else { set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ @@ -1565,7 +1532,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) break; case 2: - if(is_dev3_present()){ + if (is_dev3_present()) { /* step 1, lane reversal (only need if CMOS option is enabled) */ if (cfg->gfx_lane_reversal) { set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); @@ -1583,7 +1550,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); dual_port_configuration(nb_dev, dev); - }else{ + } else { if (cfg->gfx_lane_reversal) { set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); @@ -1591,9 +1558,9 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) } printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); - if((dev->path.pci.devfn >> 3) == 2) + if ((dev->path.pci.devfn >> 3) == 2) single_port_configuration(nb_dev, dev); - else{ + else { set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n"); } diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index ffd0e15..31bec9a 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -101,7 +101,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 ULONG ulDockingPinCFGInfo; ULONG ulCPUCapInfo; USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform - // 1 - non inverted waveform + // 1 - non inverted waveform USHORT usMaxNBVoltage; USHORT usMinNBVoltage; USHORT usBootUpNBVoltage; diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b0e3424..cbe8b0c 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -137,7 +137,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) pmio_write(0x8b, 0x01); pmio_write(0x8a, 0x90); - if(get_sb600_revision() > 0x13) + if (get_sb600_revision() > 0x13) pmio_write(0x88, 0x10); else pmio_write(0x88, 0x06); diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c index b97bdec..748610c 100644 --- a/src/southbridge/amd/sb600/hda.c +++ b/src/southbridge/amd/sb600/hda.c @@ -175,7 +175,7 @@ static int wait_for_ready(void *base) int timeout = 50; - while(timeout--) { + while (timeout--) { u32 dword=read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; @@ -196,7 +196,7 @@ static int wait_for_valid(void *base) * same duration */ int timeout = 50; - while(timeout--) { + while (timeout--) { u32 dword = read32(base + HDA_ICII_REG); if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index 6b35ba1..dbb4ec5 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -182,7 +182,7 @@ static void sata_init(struct device *dev) printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; - if( byte == 0x1 ) { + if ( byte == 0x1 ) { /* If the drive status is 0x1 then we see it but we aren't talking to it. */ /* Try to do something about it. */ printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 353c2a4..9a988a9 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -25,16 +25,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select SMBUS_HAS_AUX_CHANNELS -config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI - bool "Enable high speed SPI clock" - default n - help - When set, the SPI clock will run at 33MHz instead - of the compatibility mode 16.5MHz. Note that not - all ROMs are capable of 33MHz operation, so you - will need to verify this option is appropriate for - the ROM you are using. - # Set for southbridge SP5100 which also uses SB700 driver config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index dfa4102..97e749c 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -20,10 +20,6 @@ #define IO_MEM_PORT_DECODE_ENABLE_5 0x48 #define IO_MEM_PORT_DECODE_ENABLE_6 0x4a -#define SPI_BASE_ADDRESS 0xa0 - -#define SPI_CONTROL_1 0xc -#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000 /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -96,37 +92,7 @@ static void sb700_enable_rom(void) pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8); } -static void sb700_configure_rom(void) -{ - pci_devfn_t dev; - uint32_t dword; - - dev = PCI_DEV(0, 0x14, 3); - - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { - uint32_t prev_spi_cfg; - volatile uint32_t *spi_mmio; - - /* Temporarily set up SPI access to change SPI speed */ - prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS); - dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */ - dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5); - dword |= (0x1 << 1); /* SpiRomEnable = 1 */ - pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword); - - spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1); - dword = *spi_mmio; - dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */ - dword |= (0x1 << 12); - *spi_mmio = dword; - - /* Restore previous SPI access */ - pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg); - } -} - static void bootblock_southbridge_init(void) { sb700_enable_rom(); - sb700_configure_rom(); } diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c index c87ab6a..8497cc5 100644 --- a/src/southbridge/amd/sb700/hda.c +++ b/src/southbridge/amd/sb700/hda.c @@ -97,7 +97,7 @@ static int wait_for_ready(void *base) int timeout = 50; - while(timeout--) { + while (timeout--) { u32 dword=read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; @@ -118,7 +118,7 @@ static int wait_for_valid(void *base) * same duration */ int timeout = 50; - while(timeout--) { + while (timeout--) { u32 dword = read32(base + HDA_ICII_REG); if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index 98429f3..d0cd4a4 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -36,7 +36,7 @@ static void set_bios_reset(void) int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 6d93b17..77ec722 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -213,7 +213,7 @@ static void sm_init(device_t dev) } /*rpr v2.13 2.22 SMBUS PCI Config */ - byte = pci_read_config8(dev, 0xE1); + byte = pci_read_config8(dev, 0xE1); if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) { byte |= 1 << 0; } @@ -222,7 +222,7 @@ static void sm_init(device_t dev) */ //byte |= 1 << 2 | 1 << 3 | 1 << 4; byte |= 1 << 3 | 1 << 4; - pci_write_config8(dev, 0xE1, byte); + pci_write_config8(dev, 0xE1, byte); /* 2.5 Enabling Non-Posted Memory Write */ axindxc_reg(0x10, 1 << 9, 1 << 9); @@ -278,7 +278,7 @@ static void sm_init(device_t dev) u16 word; /* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */ - axindxc_reg(0x02, 1 << 9, 1 << 9); + axindxc_reg(0x02, 1 << 9, 1 << 9); abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0); abcfg_reg(0x1009C, 0x00000030, 0x00000030); abcfg_reg(0x10090, 0x00001E00, 0x00001E00); @@ -287,19 +287,19 @@ static void sm_init(device_t dev) abcfg_reg(0x58, 0x0000F800, 0x0000E800); /* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */ - axindxc_reg(0x02, 1 << 10, 1 << 10); + axindxc_reg(0x02, 1 << 10, 1 << 10); /* rpr v2.13 2.38 Unconditional Shutdown */ - byte = pci_read_config8(dev, 0x43); + byte = pci_read_config8(dev, 0x43); byte &= ~(1 << 3); - pci_write_config8(dev, 0x43, byte); + pci_write_config8(dev, 0x43, byte); word = pci_read_config16(dev, 0x38); word |= 1 << 12; - pci_write_config16(dev, 0x38, word); + pci_write_config16(dev, 0x38, word); byte |= 1 << 3; - pci_write_config8(dev, 0x43, byte); + pci_write_config8(dev, 0x43, byte); /* Enable southbridge MMIO decode */ dword = pci_read_config32(dev, SB_MMIO_CFG_REG); @@ -308,12 +308,12 @@ static void sm_init(device_t dev) dword |= 0x1; pci_write_config32(dev, SB_MMIO_CFG_REG, dword); } - byte = pci_read_config8(dev, 0xAE); - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)) - byte |= 1 << 4; + byte = pci_read_config8(dev, 0xAE); + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)) + byte |= 1 << 4; byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ - pci_write_config8(dev, 0xAE, byte); + pci_write_config8(dev, 0xAE, byte); /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */ /* 4.12: Enabling AB and BIF Clock Gating */ diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c index 0b68850..2d0852e 100644 --- a/src/southbridge/amd/sb800/hda.c +++ b/src/southbridge/amd/sb800/hda.c @@ -99,7 +99,7 @@ static int wait_for_ready(void *base) int timeout = 50; - while(timeout--) { + while (timeout--) { u32 dword=read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; @@ -120,7 +120,7 @@ static int wait_for_valid(void *base) * same duration */ int timeout = 50; - while(timeout--) { + while (timeout--) { u32 dword = read32(base + HDA_ICII_REG); if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index 56a2a52..978ccec 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -177,7 +177,7 @@ static void sata_init(struct device *dev) byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; - if( byte == 0x1 ) { + if ( byte == 0x1 ) { /* If the drive status is 0x1 then we see it but we aren't talking to it. */ /* Try to do something about it. */ printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index a96b127..fce25ab 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -30,22 +30,22 @@ */ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) { - u32 tmp; - - /* read axindc to tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); + u32 tmp; + + /* read axindc to tmp */ + outl(space << 30 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(space << 30 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 30 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(space << 30 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); } @@ -327,7 +327,7 @@ void fam10_optimization(void) /* rpr Table 5-11, 5-12 */ } #else -#define fam10_optimization() do{}while(0) +#define fam10_optimization() do {} while (0) #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */ /***************************************** diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d28adfc..87845c6 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -817,8 +817,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { - res = sr5650_retrieve_cpu_mmio_resource(); - if (res) + res = sr5650_retrieve_cpu_mmio_resource(); + if (res) mmconf_base = res->base; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); diff --git a/src/southbridge/broadcom/bcm21000/pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c index ca9a225..ab52029 100644 --- a/src/southbridge/broadcom/bcm21000/pcie.c +++ b/src/southbridge/broadcom/bcm21000/pcie.c @@ -43,7 +43,7 @@ static void pcie_init(struct device *dev) } static struct pci_operations lops_pci = { - .set_subsystem = 0, + .set_subsystem = 0, }; static struct device_operations pcie_ops = { diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index be23d68..d0ff9ca 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -23,12 +23,12 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations nic_ops = { @@ -47,7 +47,7 @@ static const struct pci_driver nic_driver __pci_driver = { }; static const struct pci_driver nic1_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_BROADCOM, - .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1, + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_BROADCOM, + .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1, }; diff --git a/src/southbridge/broadcom/bcm5780/pcie.c b/src/southbridge/broadcom/bcm5780/pcie.c index 6f8493e..2ed6102 100644 --- a/src/southbridge/broadcom/bcm5780/pcie.c +++ b/src/southbridge/broadcom/bcm5780/pcie.c @@ -35,17 +35,17 @@ static void pcie_init(struct device *dev) } static struct pci_operations lops_pci = { - .set_subsystem = 0, + .set_subsystem = 0, }; static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, }; diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 22dc771..8aa37a6 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -22,22 +22,22 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations ht_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = 0 , - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = 0 , + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, }; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index efe38ab..d9a1268 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -36,17 +36,17 @@ void bcm5785_enable(device_t dev) sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn); // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && - (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X ) - { - unsigned devfn; - devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); - sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn); + (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X ) + { + unsigned devfn; + devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); + sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn); // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; - } + } else { // same bus unsigned devfn; devfn = (dev->path.pci.devfn) & ~7; - if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { + if ( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { if (dev->device == 0x0036) //PCI-X Bridge { devfn += (1<<3); } else if (dev->device == 0x0223) // USB diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h index ac39fd1..2c65734 100644 --- a/src/southbridge/broadcom/bcm5785/chip.h +++ b/src/southbridge/broadcom/bcm5785/chip.h @@ -19,10 +19,10 @@ struct southbridge_broadcom_bcm5785_config { - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int sata0_enable : 1; - unsigned int sata1_enable : 1; + unsigned int ide0_enable : 1; + unsigned int ide1_enable : 1; + unsigned int sata0_enable : 1; + unsigned int sata1_enable : 1; }; #endif /* BCM5785_CHIP_H */ diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 3ddc9ca..8aba58c 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -19,62 +19,62 @@ static void bcm5785_enable_lpc(void) { - uint8_t byte; - device_t dev; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); - - /* LPC Control 0 */ - byte = pci_read_config8(dev, 0x44); - /* Serial 0 */ - byte |= (1<<6); - pci_write_config8(dev, 0x44, byte); - - /* LPC Control 4 */ - byte = pci_read_config8(dev, 0x48); - /* superio port 0x2e/4e enable */ - byte |=(1<<1)|(1<<0); - pci_write_config8(dev, 0x48, byte); + uint8_t byte; + device_t dev; + + dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); + + /* LPC Control 0 */ + byte = pci_read_config8(dev, 0x44); + /* Serial 0 */ + byte |= (1<<6); + pci_write_config8(dev, 0x44, byte); + + /* LPC Control 4 */ + byte = pci_read_config8(dev, 0x48); + /* superio port 0x2e/4e enable */ + byte |=(1<<1)|(1<<0); + pci_write_config8(dev, 0x48, byte); } static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; - uint32_t dword; - uint32_t dword_old; + device_t dev; + uint32_t dword; + uint32_t dword_old; - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - dword_old = pci_read_config32(dev, 0x4c); - dword = dword_old | (1<<4); //enable Timer Func - if (dword != dword_old ) { - pci_write_config32(dev, 0x4c, dword); - } + dword_old = pci_read_config32(dev, 0x4c); + dword = dword_old | (1<<4); //enable Timer Func + if (dword != dword_old ) { + pci_write_config32(dev, 0x4c, dword); + } - dword_old = pci_read_config32(dev, 0x6c); - dword = dword_old | (1<<9); //unhide Timer Func in pci space - if (dword != dword_old ) { - pci_write_config32(dev, 0x6c, dword); - } + dword_old = pci_read_config32(dev, 0x6c); + dword = dword_old | (1<<9); //unhide Timer Func in pci space + if (dword != dword_old ) { + pci_write_config32(dev, 0x6c, dword); + } - dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); + dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); - /* enable cf9 */ - pci_write_config8(dev, 0x40, (1<<2)); + /* enable cf9 */ + pci_write_config8(dev, 0x40, (1<<2)); } unsigned get_sbdn(unsigned bus) { - device_t dev; + device_t dev; - /* Find the device. - * There can only be one bcm5785 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(0x1166, 0x0036), - bus); + /* Find the device. + * There can only be one bcm5785 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(0x1166, 0x0036), + bus); - return (dev>>15) & 0x1f; + return (dev>>15) & 0x1f; } @@ -89,8 +89,8 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) // set port to 0x2060 outb(0x67, 0xcd6); outb(0x60, 0xcd7); - outb(0x68, 0xcd6); - outb(0x20, 0xcd7); + outb(0x68, 0xcd6); + outb(0x20, 0xcd7); outb(0x69, 0xcd6); outb(7, 0xcd7); @@ -107,113 +107,113 @@ void ldtstop_sb(void) void hard_reset(void) { - bcm5785_enable_wdt_port_cf9(); + bcm5785_enable_wdt_port_cf9(); - set_bios_reset(); + set_bios_reset(); - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); } void soft_reset(void) { - bcm5785_enable_wdt_port_cf9(); + bcm5785_enable_wdt_port_cf9(); - set_bios_reset(); + set_bios_reset(); #if 1 - /* link reset */ -// outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); + /* link reset */ +// outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); #endif } static void bcm5785_enable_msg(void) { - device_t dev; - uint32_t dword; - uint32_t dword_old; - uint8_t byte; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - - byte = pci_read_config8(dev, 0x42); - byte = (1<<1); //enable a20 - pci_write_config8(dev, 0x42, byte); - - dword_old = pci_read_config32(dev, 0x6c); - // bit 5: enable A20 Message - // bit 4: enable interrupt messages - // bit 3: enable reset init message - // bit 2: enable keyboard init message - // bit 1: enable upsteam messages - // bit 0: enable shutdowm message to init generation - dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor - if (dword != dword_old ) { - pci_write_config32(dev, 0x6c, dword); - } + device_t dev; + uint32_t dword; + uint32_t dword_old; + uint8_t byte; + + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + + byte = pci_read_config8(dev, 0x42); + byte = (1<<1); //enable a20 + pci_write_config8(dev, 0x42, byte); + + dword_old = pci_read_config32(dev, 0x6c); + // bit 5: enable A20 Message + // bit 4: enable interrupt messages + // bit 3: enable reset init message + // bit 2: enable keyboard init message + // bit 1: enable upsteam messages + // bit 0: enable shutdowm message to init generation + dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor + if (dword != dword_old ) { + pci_write_config32(dev, 0x6c, dword); + } } static void bcm5785_early_setup(void) { - uint8_t byte; - uint32_t dword; - device_t dev; + uint8_t byte; + uint32_t dword; + device_t dev; //F0 - // enable device on bcm5785 at first - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - dword = pci_read_config32(dev, 0x64); - dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable - dword |= (1<<8); // USB enable - dword |= /* (1<<27)|*/(1<<14); // IDE enable - pci_write_config32(dev, 0x64, dword); - - byte = pci_read_config8(dev, 0x84); - byte |= (1<<0); // SATA enable - pci_write_config8(dev, 0x84, byte); + // enable device on bcm5785 at first + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + dword = pci_read_config32(dev, 0x64); + dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable + dword |= (1<<8); // USB enable + dword |= /* (1<<27)|*/(1<<14); // IDE enable + pci_write_config32(dev, 0x64, dword); + + byte = pci_read_config8(dev, 0x84); + byte |= (1<<0); // SATA enable + pci_write_config8(dev, 0x84, byte); // WDT and cf9 for later in ramstage to call hard_reset - bcm5785_enable_wdt_port_cf9(); + bcm5785_enable_wdt_port_cf9(); - bcm5785_enable_msg(); + bcm5785_enable_msg(); // IDE related //F0 - byte = pci_read_config8(dev, 0x4e); - byte |= (1<<4); //enable IDE ext regs - pci_write_config8(dev, 0x4e, byte); + byte = pci_read_config8(dev, 0x4e); + byte |= (1<<4); //enable IDE ext regs + pci_write_config8(dev, 0x4e, byte); //F1 - dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0); - byte = pci_read_config8(dev, 0x48); - byte &= ~1; // disable pri channel - pci_write_config8(dev, 0x48, byte); - pci_write_config8(dev, 0xb0, 0x01); - pci_write_config8(dev, 0xb2, 0x02); - byte = pci_read_config8(dev, 0x06); - byte |= (1<<4); // so b0, b2 can not be changed from now - pci_write_config8(dev, 0x06, byte); - byte = pci_read_config8(dev, 0x49); - byte |= 1; // enable second channel - pci_write_config8(dev, 0x49, byte); + dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0); + byte = pci_read_config8(dev, 0x48); + byte &= ~1; // disable pri channel + pci_write_config8(dev, 0x48, byte); + pci_write_config8(dev, 0xb0, 0x01); + pci_write_config8(dev, 0xb2, 0x02); + byte = pci_read_config8(dev, 0x06); + byte |= (1<<4); // so b0, b2 can not be changed from now + pci_write_config8(dev, 0x06, byte); + byte = pci_read_config8(dev, 0x49); + byte |= 1; // enable second channel + pci_write_config8(dev, 0x49, byte); //F2 - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); + dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); - byte = pci_read_config8(dev, 0x40); - byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable - pci_write_config8(dev, 0x40, byte); + byte = pci_read_config8(dev, 0x40); + byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable + pci_write_config8(dev, 0x40, byte); - pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end + pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end // USB related - pci_write_config8(dev, 0x90, 0x40); - pci_write_config8(dev, 0x92, 0x06); - pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register - pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func - pci_write_config8(dev, 0xb4, 0x40); + pci_write_config8(dev, 0x90, 0x40); + pci_write_config8(dev, 0x92, 0x06); + pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register + pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func + pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func + pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func + pci_write_config8(dev, 0xb4, 0x40); } diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 9d3d3e8..f37aed9 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -38,20 +38,20 @@ static void enable_smbus(void) static inline int smbus_recv_byte(unsigned device) { - return do_smbus_recv_byte(SMBUS_IO_BASE, device); + return do_smbus_recv_byte(SMBUS_IO_BASE, device); } static inline int smbus_send_byte(unsigned device, unsigned char val) { - return do_smbus_send_byte(SMBUS_IO_BASE, device, val); + return do_smbus_send_byte(SMBUS_IO_BASE, device, val); } static inline int smbus_read_byte(unsigned device, unsigned address) { - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 868586c..a6bb204 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -23,13 +23,13 @@ static void bcm5785_ide_read_resources(device_t dev) { - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); - /* BAR */ - pci_get_resource(dev, 0x64); + /* BAR */ + pci_get_resource(dev, 0x64); - compact_resources(dev); + compact_resources(dev); } static void ide_init(struct device *dev) @@ -38,12 +38,12 @@ static void ide_init(struct device *dev) static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations ide_ops = { diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index f0d7416..59ba798 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -74,15 +74,15 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44); for (link = dev->link_list; link; link = link->next) { - device_t child; - for (child = link->children; child; child = child->sibling) { - if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { + device_t child; + for (child = link->children; child; child = child->sibling) { + if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; - for(res = child->resource_list; res; res = res->next) { - unsigned long base, end; // don't need long long - if(!(res->flags & IORESOURCE_IO)) continue; - base = res->base; - end = resource_end(res); + for (res = child->resource_list; res; res = res->next) { + unsigned long base, end; // don't need long long + if (!(res->flags & IORESOURCE_IO)) continue; + base = res->base; + end = resource_end(res); printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x60: //KBC @@ -103,8 +103,8 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } } } - } - } + } + } pci_write_config32(dev, 0x44, reg); @@ -112,18 +112,18 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) static void bcm5785_lpc_enable_resources(device_t dev) { - pci_dev_enable_resources(dev); - bcm5785_lpc_enable_childrens_resources(dev); + pci_dev_enable_resources(dev); + bcm5785_lpc_enable_childrens_resources(dev); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations lpc_ops = { diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 7064b19..8140e01 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -18,24 +18,24 @@ #include <reset.h> #define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12)) static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); } static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); } #include "../../../northbridge/amd/amdk8/reset_test.c" @@ -43,7 +43,7 @@ static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) void hard_reset(void) { set_bios_reset(); - /* Try rebooting through port 0xcf9 */ + /* Try rebooting through port 0xcf9 */ /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 75f2d46..02331d9 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -28,41 +28,41 @@ static void sata_init(struct device *dev) uint8_t byte; u8 *mmio; - struct resource *res; - u8 *mmio_base; + struct resource *res; + u8 *mmio_base; int i; - if(!(dev->path.pci.devfn & 7)) { // only set it in Func0 + if (!(dev->path.pci.devfn & 7)) { // only set it in Func0 byte = pci_read_config8(dev, 0x78); byte |= (1<<7); - pci_write_config8(dev, 0x78, byte); + pci_write_config8(dev, 0x78, byte); res = find_resource(dev, 0x24); - mmio_base = res2mmio(res, 0, 3); + mmio_base = res2mmio(res, 0, 3); write32(mmio_base + 0x10f0, 0x40000001); write32(mmio_base + 0x8c, 0x00ff2007); - mdelay( 10 ); + mdelay( 10 ); write32(mmio_base + 0x8c, 0x78592009); - mdelay( 10 ); + mdelay( 10 ); write32(mmio_base + 0x8c, 0x00082004); - mdelay( 10 ); + mdelay( 10 ); write32(mmio_base + 0x8c, 0x00002004); - mdelay( 10 ); + mdelay( 10 ); //init PHY printk(BIOS_DEBUG, "init PHY...\n"); - for(i=0; i<4; i++) { + for (i=0; i<4; i++) { mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i); byte = read8(mmio + 0x40); printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); - if(byte & 0x4) {// bit 2 is set + if (byte & 0x4) {// bit 2 is set byte = read8(mmio+0x48); write8(mmio + 0x48, byte | 1); write8(mmio + 0x48, byte & (~1)); - byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); + byte = read8(mmio + 0x40); + printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); } } } @@ -70,12 +70,12 @@ static void sata_init(struct device *dev) static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 1898ca6..ab0cd05 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -45,7 +45,7 @@ static void sb_init(device_t dev) } else { byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } - if( byte != byte_old) { + if ( byte != byte_old) { outb(byte, 0x70); } @@ -63,101 +63,101 @@ static void bcm5785_sb_read_resources(device_t dev) compact_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Add an extra subtractive resource for both memory and I/O */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } static int lsmbus_recv_byte(device_t dev) { - unsigned device; - struct resource *res; + unsigned device; + struct resource *res; struct bus *pbus; - device = dev->path.i2c.device; + device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90); - return do_smbus_recv_byte(res->base, device); + return do_smbus_recv_byte(res->base, device); } static int lsmbus_send_byte(device_t dev, uint8_t val) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus; - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90); - return do_smbus_send_byte(res->base, device, val); + return do_smbus_send_byte(res->base, device, val); } static int lsmbus_read_byte(device_t dev, uint8_t address) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus; - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90); - return do_smbus_read_byte(res->base, device, address); + return do_smbus_read_byte(res->base, device, address); } static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus; - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90); - return do_smbus_write_byte(res->base, device, address, val); + return do_smbus_write_byte(res->base, device, address, val); } static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, }; static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x2c, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x2c, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations sb_ops = { - .read_resources = bcm5785_sb_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sb_init, - .scan_bus = scan_smbus, + .read_resources = bcm5785_sb_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sb_init, + .scan_bus = scan_smbus, // .enable = bcm5785_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, }; static const struct pci_driver sb_driver __pci_driver = { - .ops = &sb_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, + .ops = &sb_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, }; diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h index bb43269..76c593b 100644 --- a/src/southbridge/broadcom/bcm5785/smbus.h +++ b/src/southbridge/broadcom/bcm5785/smbus.h @@ -53,7 +53,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) return 0; } outb(val, smbus_io_base + SMBHSTSTAT); - } while(--loops); + } while (--loops); return -2; // time out } @@ -73,7 +73,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) outb(val, smbus_io_base + SMBHSTSTAT); // clear status return 0; // } - } while(--loops); + } while (--loops); return -3; // timeout } @@ -81,54 +81,54 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { uint8_t byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); return byte; } static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) { - uint8_t byte; + uint8_t byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } - return 0; + return 0; } static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) @@ -142,8 +142,8 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; // Clear [4:2] @@ -163,30 +163,30 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) { - uint8_t byte; + uint8_t byte; - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + } - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0); - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + } - return 0; + return 0; } diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index fa73b2f..9aa64df 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -23,7 +23,7 @@ static void usb_init(struct device *dev) { - uint32_t dword; + uint32_t dword; dword = pci_read_config32(dev, 0x04); dword |= (1<<2)|(1<<1)|(1<<0); @@ -35,12 +35,12 @@ static void usb_init(struct device *dev) static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations usb_ops = { diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index d5dcde0..c122d2a 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base) int timeout = 1000; - while(timeout--) { + while (timeout--) { u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; @@ -145,7 +145,7 @@ static int wait_for_valid(u8 *base) /* Use a 1msec timeout */ int timeout = 1000; - while(timeout--) { + while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 1106912..9041816 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -125,7 +125,7 @@ static void pch_pirq_init(device_t dev) pci_write_config8(dev, PIRQG_ROUT, pirq_routing); pci_write_config8(dev, PIRQH_ROUT, pirq_routing); - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 83c99e0..23915c3 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -445,7 +445,7 @@ static int mkhi_get_fwcaps(void) print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); print_cap("IPV6", cap.caps_sku.ipv6); print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 4dbe8ed..220a176 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -703,7 +703,7 @@ static void intel_me_init(device_t dev) if (intel_mei_setup(dev) < 0) break; - if(intel_me_read_mbp(&mbp_data)) + if (intel_me_read_mbp(&mbp_data)) break; #if CONFIG_CHROMEOS && 0 /* DISABLED */ @@ -893,7 +893,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) default: printk(BIOS_ERR, "ME: unknown mbp item id 0x%x! Skipping\n", mbp_item_id); - while(copy_size--) + while (copy_size--) read_cb(); continue; } @@ -904,7 +904,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) buffer_room, copy_size, mbp_item_id); return -1; } - while(copy_size--) + while (copy_size--) *copy_addr++ = read_cb(); } @@ -914,7 +914,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) { int cntr = 0; - while(host.interrupt_generate) { + while (host.interrupt_generate) { read_host_csr(&host); cntr++; } diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c index daabbbc..804fb81 100644 --- a/src/southbridge/intel/bd82x6x/reset.c +++ b/src/southbridge/intel/bd82x6x/reset.c @@ -19,10 +19,10 @@ void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); } void hard_reset(void) { - outb(0x06, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index bc19b78..0478285 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -271,37 +271,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } static void southbridge_gate_memory_reset_real(int offset, @@ -863,7 +863,7 @@ void southbridge_smi_handler(void) } } - if(dump) { + if (dump) { dump_smi_status(smi_sts); } diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c index 5ec708e..b64d923 100644 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c @@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base) int timeout = 50; - while(timeout--) { + while (timeout--) { u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; @@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base) * same duration */ int timeout = 50; - while(timeout--) { + while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index d12cd4e..faec69a 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev) * I am not so sure anymore he was right. */ - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0, int_line=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 68a9ee5..a951f9f 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void) print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); print_cap("IPV6", cap.caps_sku.ipv6); print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index e29d86b..0d3a01e 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -385,11 +385,10 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap) }; /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) - < 0) { + if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; - } + } *cap = cap_msg.caps_sku; return 0; } @@ -413,7 +412,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); print_cap("IPV6", cap->ipv6); print_cap("KVM Remote Control (KVM)", cap->kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap->och); @@ -702,7 +701,7 @@ static void intel_me_init(device_t dev) if (intel_mei_setup(dev) < 0) break; - if(intel_me_read_mbp(&mbp_data)) + if (intel_me_read_mbp(&mbp_data)) break; #if CONFIG_CHROMEOS && 0 /* DISABLED */ @@ -901,7 +900,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) buffer_room, copy_size, mbp_item_id); return -1; } - while(copy_size--) + while (copy_size--) *copy_addr++ = read_cb(); } @@ -911,7 +910,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) { int cntr = 0; - while(host.interrupt_generate) { + while (host.interrupt_generate) { read_host_csr(&host); cntr++; } diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c index c2e76d5..a2e8236 100644 --- a/src/southbridge/intel/fsp_bd82x6x/reset.c +++ b/src/southbridge/intel/fsp_bd82x6x/reset.c @@ -20,10 +20,10 @@ void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); } void hard_reset(void) { - outb(0x06, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 77ada10..01ace59 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } /* @@ -749,7 +749,7 @@ void southbridge_smi_handler(void) } } - if(dump) { + if (dump) { dump_smi_status(smi_sts); } diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index 5b8fdbc..1514500 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev) * I am not so sure anymore he was right. */ - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0, int_line=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c index caf24e3..7ea42d4 100644 --- a/src/southbridge/intel/fsp_i89xx/me.c +++ b/src/southbridge/intel/fsp_i89xx/me.c @@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void) print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); print_cap("IPV6", cap.caps_sku.ipv6); print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c index 090d8d0..f25843e 100644 --- a/src/southbridge/intel/fsp_i89xx/me_8.x.c +++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c @@ -413,7 +413,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); print_cap("IPV6", cap->ipv6); print_cap("KVM Remote Control (KVM)", cap->kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap->och); @@ -670,7 +670,7 @@ static void intel_me_init(device_t dev) if (intel_mei_setup(dev) < 0) break; - if(intel_me_read_mbp(&mbp_data)) + if (intel_me_read_mbp(&mbp_data)) break; #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) @@ -855,7 +855,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) buffer_room, copy_size, mbp_item_id); return -1; } - while(copy_size--) + while (copy_size--) *copy_addr++ = read_cb(); } @@ -865,7 +865,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) { int cntr = 0; - while(host.interrupt_generate) { + while (host.interrupt_generate) { read_host_csr(&host); cntr++; } diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index c5c1136..09cce59 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -203,7 +203,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { cbmem_was_initted = !cbmem_recovery(0); - if(cbmem_was_initted) { + if (cbmem_was_initted) { reset_system(); } diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index 27b8166..d4dbb22 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } /* @@ -746,7 +746,7 @@ void southbridge_smi_handler(void) } } - if(dump) { + if (dump) { dump_smi_status(smi_sts); } diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c index e57d855..2a2061c 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ b/src/southbridge/intel/fsp_rangeley/gpio.c @@ -64,7 +64,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) /* CFIO Core Well Set 1 */ if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) { write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002); - for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { + for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0)) continue; write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0); @@ -78,7 +78,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) /* CFIO SUS Well Set 1 */ if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) { write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002); - for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { + for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0)) continue; write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0); diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 11aa60d..ab61750 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -137,7 +137,7 @@ static void write_pci_config_irqs(void) * the Interrupt Route registers in the ILB */ printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { if ((irq_dev->path.type != DEVICE_PATH_PCI) || (!irq_dev->enabled)) @@ -225,7 +225,7 @@ static void soc_pirq_init(device_t dev) write16(ir_base + i, ir->pcidev[i]); /* If the entry is more than just 0, print it out */ - if(ir->pcidev[i]) { + if (ir->pcidev[i]) { printk(BIOS_SPEW, " %d: ", i); for (j = 0; j < 4; j++) { pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c index 12a9202..2cb241a 100644 --- a/src/southbridge/intel/i3100/early_smbus.c +++ b/src/southbridge/intel/i3100/early_smbus.c @@ -27,7 +27,7 @@ static void enable_smbus(void) pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); /* SMBALERT_DIS */ - outb(4, SMBUS_IO_BASE + SMBSLVCMD); + outb(4, SMBUS_IO_BASE + SMBSLVCMD); /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index 77853a8..7b319cf 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -206,19 +206,19 @@ static void i3100_pirq_init(device_t dev) if (config->pirq_e_h) pci_write_config32(dev, 0x68, config->pirq_e_h); - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin=0, int_line=0; - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - switch (int_pin) { - case 1: /* INTA# */ + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + switch (int_pin) { + case 1: /* INTA# */ int_line = config->pirq_a_d & 0xff; break; - case 2: /* INTB# */ + case 2: /* INTB# */ int_line = (config->pirq_a_d >> 8) & 0xff; break; @@ -226,17 +226,17 @@ static void i3100_pirq_init(device_t dev) int_line = (config->pirq_a_d >> 16) & 0xff; break; - case 4: /* INTD# */ + case 4: /* INTD# */ int_line = (config->pirq_a_d >> 24) & 0xff; break; - } + } - if (!int_line) - continue; + if (!int_line) + continue; printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line); - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } } diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index f4dff8b..27bd2ce 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -42,7 +42,7 @@ static void sata_init(struct device *dev) /* Enable SATA devices */ printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy"); - if(ahci) { + if (ahci) { /* AHCI mode */ pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0)); diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 5b8d0ed..59d5dea 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -28,7 +28,7 @@ static int determine_total_number_of_cores(void) { device_t cpu; int count = 0; - for(cpu = all_devices; cpu; cpu = cpu->next) { + for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { continue; diff --git a/src/southbridge/intel/i82371eb/smbus.h b/src/southbridge/intel/i82371eb/smbus.h index fd02217..de34504 100644 --- a/src/southbridge/intel/i82371eb/smbus.h +++ b/src/southbridge/intel/i82371eb/smbus.h @@ -35,12 +35,12 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) break; } #if 0 - if(loops == (SMBUS_TIMEOUT / 2)) { + if (loops == (SMBUS_TIMEOUT / 2)) { outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); } #endif - } while(--loops); + } while (--loops); return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; } @@ -62,7 +62,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) if (val & 0xfe) { break; } - } while(--loops); + } while (--loops); return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; } diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index f4ab2f6..a558169 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -233,37 +233,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } @@ -636,7 +636,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav } } - if(dump) { + if (dump) { dump_smi_status(smi_sts); } diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index 979b842..ad543e7 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -81,7 +81,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, /* setup transaction */ /* Obtain ownership */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for(stat=0;(stat&0x40)==0;) { + for (stat=0;(stat&0x40)==0;) { stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); } /* clear the done bit */ @@ -105,7 +105,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, SMBUS_IO_BASE + SMBHSTCTL); - for(i=0;i<length;i++) { + for (i=0;i<length;i++) { /* poll for transaction completion */ if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { @@ -113,7 +113,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, } /* load the next byte */ - if(i>3) + if (i>3) byte=(data2>>(i%4))&0x0ff; else byte=(data1>>(i))&0x0ff; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 630484a..7d01dbc 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -78,8 +78,8 @@ static void i82801ex_pci_dma_cfg(device_t dev) #define LPC_EN 0xe6 static void i82801ex_enable_lpc(device_t dev) { - /* lpc i/f enable */ - pci_write_config8(dev, LPC_EN, 0x0d); + /* lpc i/f enable */ + pci_write_config8(dev, LPC_EN, 0x0d); } typedef struct southbridge_intel_i82801ex_config config_t; @@ -92,7 +92,7 @@ static void set_i82801ex_gpio_use_sel( gpio_use_sel = 0x1A003180; gpio_use_sel2 = 0x00000007; - for(i = 0; i < 64; i++) { + for (i = 0; i < 64; i++) { int val; switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) { case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break; @@ -121,7 +121,7 @@ static void set_i82801ex_gpio_direction( gpio_io_sel = 0x0000ffff; gpio_io_sel2 = 0x00000300; - for(i = 0; i < 64; i++) { + for (i = 0; i < 64; i++) { int val; switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) { case ICH5R_GPIO_SEL_OUTPUT: val = 0; break; @@ -152,7 +152,7 @@ static void set_i82801ex_gpio_level( gpio_lvl = 0x1b3f0000; gpio_blink = 0x00040000; gpio_lvl2 = 0x00030207; - for(i = 0; i < 64; i++) { + for (i = 0; i < 64; i++) { int val, blink; switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) { case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break; @@ -184,7 +184,7 @@ static void set_i82801ex_gpio_inv( int i; gpio_inv = 0x00000000; - for(i = 0; i < 32; i++) { + for (i = 0; i < 32; i++) { int val; switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) { case ICH5R_GPIO_INV_OFF: val = 0; break; @@ -205,10 +205,10 @@ static void i82801ex_pirq_init(device_t dev) /* Get the chip configuration */ config = dev->chip_info; - if(config->pirq_a_d) { + if (config->pirq_a_d) { pci_write_config32(dev, 0x60, config->pirq_a_d); } - if(config->pirq_e_h) { + if (config->pirq_e_h) { pci_write_config32(dev, 0x68, config->pirq_e_h); } } @@ -292,7 +292,7 @@ static void lpc_init(struct device *dev) /* Clear SATA to non raid */ pci_write_config8(dev, 0xae, 0x00); - get_option(&pwr_on, "power_on_after_fail"); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c index 9936892..8036ffd 100644 --- a/src/southbridge/intel/i82801ex/reset.c +++ b/src/southbridge/intel/i82801ex/reset.c @@ -3,6 +3,6 @@ void hard_reset(void) { - /* Try rebooting through port 0xcf9 */ - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); + /* Try rebooting through port 0xcf9 */ + outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); } diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h index b166797..dbb7b7a 100644 --- a/src/southbridge/intel/i82801ex/smbus.h +++ b/src/southbridge/intel/i82801ex/smbus.h @@ -29,7 +29,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) if (--loops == 0) break; byte = inb(smbus_io_base + SMBHSTSTAT); - } while(byte & 1); + } while (byte & 1); return loops?0:-1; } @@ -42,7 +42,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) if (--loops == 0) break; byte = inb(smbus_io_base + SMBHSTSTAT); - } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0); + } while ((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0); return loops?0:-1; } @@ -55,7 +55,7 @@ static inline int smbus_wait_until_blk_done(unsigned smbus_io_base) if (--loops == 0) break; byte = inb(smbus_io_base + SMBHSTSTAT); - } while((byte&(1<<7)) == 0); + } while ((byte&(1<<7)) == 0); return loops?0:-1; } diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c index 28e1f5e..6aba270 100644 --- a/src/southbridge/intel/i82801ex/watchdog.c +++ b/src/southbridge/intel/i82801ex/watchdog.c @@ -6,23 +6,23 @@ void watchdog_off(void) { - device_t dev; - unsigned long value,base; + device_t dev; + unsigned long value,base; /* turn off the ICH5 watchdog */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - /* Get TCO base */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - /* Disable the watchdog timer */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + /* Get TCO base */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + /* Disable the watchdog timer */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); } diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index d28154c..b13d809 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base) int timeout = 50; - while(timeout--) { + while (timeout--) { u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; @@ -146,7 +146,7 @@ static int wait_for_valid(u8 *base) * same duration */ int timeout = 50; - while(timeout--) { + while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 50268b6..c9c19a3 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -30,22 +30,22 @@ static void store_initial_timestamp(void) static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; + u8 reg8; + pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + dev = PCI_DEV(0, 0x1f, 0); - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); } static void bootblock_southbridge_init(void) { store_initial_timestamp(); - enable_spi_prefetch(); + enable_spi_prefetch(); /* Enable RCBA */ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 03df1a3..280e207 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -108,7 +108,7 @@ static void i82801gx_pirq_init(device_t dev) * I am not so sure anymore he was right. */ - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0, int_line=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c index 39c4f31..97b8225 100644 --- a/src/southbridge/intel/i82801gx/reset.c +++ b/src/southbridge/intel/i82801gx/reset.c @@ -19,7 +19,7 @@ void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); } #if 0 @@ -32,6 +32,6 @@ void hard_reset(void) void hard_reset(void) { - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 913f68f..e6aa018 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -123,7 +123,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device, outb((inb(smbus_base + SMBHSTCTL) | 0x40), smbus_base + SMBHSTCTL); - while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + while (!(inb(smbus_base + SMBHSTSTAT) & 1)); /* Poll for transaction completion */ do { status = inb(smbus_base + SMBHSTSTAT); @@ -136,7 +136,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device, outb(*buf++, smbus_base + SMBBLKDAT); outb(status, smbus_base + SMBHSTSTAT); } - } while(status & 0x01); + } while (status & 0x01); return 0; } @@ -180,7 +180,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device, outb((inb(smbus_base + SMBHSTCTL) | 0x40), smbus_base + SMBHSTCTL); - while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + while (!(inb(smbus_base + SMBHSTSTAT) & 1)); /* Poll for transaction completion */ do { status = inb(smbus_base + SMBHSTSTAT); @@ -200,7 +200,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device, smbus_base + SMBHSTCTL); } } - } while(status & 0x01); + } while (status & 0x01); return bytes_read; } diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index e76087c..d3867a5 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -269,37 +269,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } @@ -673,7 +673,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav } } - if(dump) { + if (dump) { dump_smi_status(smi_sts); } diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index e222368..6252712 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -17,18 +17,18 @@ static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; + u8 reg8; + pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + dev = PCI_DEV(0, 0x1f, 0); - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); } static void bootblock_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetch(); } diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 4848b94..c3602c4 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base) int timeout = 50; - while(timeout--) { + while (timeout--) { u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; @@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base) * same duration */ int timeout = 50; - while(timeout--) { + while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 4415f44..e095ad8 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -110,7 +110,7 @@ static void i82801ix_pirq_init(device_t dev) * I am not so sure anymore he was right. */ - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0, int_line=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 5f1a44f..7ad00ed 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -518,7 +518,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav } } - if(dump) { + if (dump) { dump_smi_status(smi_sts); } diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 6a0f0d2..a02a2af 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -11,11 +11,10 @@ static int num_p64h2_ioapics = 0; static void p64h2_ioapic_enable(device_t dev) { - /* We have to enable MEM and Bus Master for IOAPIC */ - uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + /* We have to enable MEM and Bus Master for IOAPIC */ + uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - - pci_write_config16(dev, PCI_COMMAND, command); + pci_write_config16(dev, PCI_COMMAND, command); } /** @@ -29,70 +28,70 @@ static void p64h2_ioapic_enable(device_t dev) */ static void p64h2_ioapic_init(device_t dev) { - uint32_t memoryBase; - int apic_index, apic_id; + uint32_t memoryBase; + int apic_index, apic_id; - volatile uint32_t* pIndexRegister; /* io apic io memory space command address */ - volatile uint32_t* pWindowRegister; /* io apic io memory space data address */ + volatile uint32_t* pIndexRegister; /* io apic io memory space command address */ + volatile uint32_t* pWindowRegister; /* io apic io memory space data address */ - apic_index = num_p64h2_ioapics; - num_p64h2_ioapics++; + apic_index = num_p64h2_ioapics; + num_p64h2_ioapics++; - // A note on IOAPIC addresses: - // 0 and 1 are used for the local APICs of the dual virtual - // (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb). - // 6 and 7 are used for the local APICs of the dual virtual - // (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb). - // 2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c) + // A note on IOAPIC addresses: + // 0 and 1 are used for the local APICs of the dual virtual + // (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb). + // 6 and 7 are used for the local APICs of the dual virtual + // (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb). + // 2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c) - // Map APIC index into APIC ID - // IDs 3, 4, 5, and 8+ are available (see above note) + // Map APIC index into APIC ID + // IDs 3, 4, 5, and 8+ are available (see above note) - if (apic_index < 3) - apic_id = apic_index + 3; - else - apic_id = apic_index + 5; + if (apic_index < 3) + apic_id = apic_index + 3; + else + apic_id = apic_index + 5; - ASSERT(apic_id < 16); // ID is only 4 bits + ASSERT(apic_id < 16); // ID is only 4 bits - // Read the MBAR address for setting up the IOAPIC in memory space - // NOTE: this address was assigned during enumeration of the bus + // Read the MBAR address for setting up the IOAPIC in memory space + // NOTE: this address was assigned during enumeration of the bus - memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - pIndexRegister = (volatile uint32_t*) memoryBase; - pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10); + memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + pIndexRegister = (volatile uint32_t*) memoryBase; + pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10); - printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n", - apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister); + printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n", + apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister); - apic_id <<= 24; // Convert ID to bitmask + apic_id <<= 24; // Convert ID to bitmask - *pIndexRegister = 0; // Select APIC ID register - *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID + *pIndexRegister = 0; // Select APIC ID register + *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID - if ((*pWindowRegister & (0xF<<24)) != apic_id) - die("p64h2_ioapic_init failed"); + if ((*pWindowRegister & (0xF<<24)) != apic_id) + die("p64h2_ioapic_init failed"); - *pIndexRegister = 3; // Select Boot Configuration register - *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts + *pIndexRegister = 3; // Select Boot Configuration register + *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts - if (!(*pWindowRegister & 1)) - die("p64h2_ioapic_init failed"); + if (!(*pWindowRegister & 1)) + die("p64h2_ioapic_init failed"); } static struct device_operations ioapic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = p64h2_ioapic_init, - .scan_bus = 0, - .enable = p64h2_ioapic_enable, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = p64h2_ioapic_init, + .scan_bus = 0, + .enable = p64h2_ioapic_enable, }; static const struct pci_driver ioapic_driver __pci_driver = { - .ops = &ioapic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82870_1E0, + .ops = &ioapic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82870_1E0, }; diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c index 71d2c53..b886c52 100644 --- a/src/southbridge/intel/i82870/pci_parity.c +++ b/src/southbridge/intel/i82870/pci_parity.c @@ -5,19 +5,19 @@ void p64h2_pci_parity_enable(void) { - uint8_t reg; + uint8_t reg; - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg); + /* 2SERREN - SERR enable for PCI bridge secondary device */ + /* 2PEREN - Parity error for PCI bridge secondary device */ + pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg); + reg |= ((1 << 1) + (1 << 0)); + pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg); - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg); + /* 2SERREN - SERR enable for PCI bridge secondary device */ + /* 2PEREN - Parity error for PCI bridge secondary device */ + pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg); + reg |= ((1 << 1) + (1 << 0)); + pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg); - return; + return; } diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c index b46b338..e8d890a 100644 --- a/src/southbridge/intel/i82870/pcibridge.c +++ b/src/southbridge/intel/i82870/pcibridge.c @@ -23,16 +23,16 @@ static void p64h2_pcix_init(device_t dev) } static struct device_operations pcix_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = p64h2_pcix_init, - .scan_bus = pci_scan_bridge, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = p64h2_pcix_init, + .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, }; static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82870_1F0, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82870_1F0, }; diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index dfcbcb6..d9f635a 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -115,7 +115,7 @@ static int wait_for_ready(u8 *base) int timeout = 1000; - while(timeout--) { + while (timeout--) { u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; @@ -143,7 +143,7 @@ static int wait_for_valid(u8 *base) /* Use a 1msec timeout */ int timeout = 1000; - while(timeout--) { + while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 88ec851..23b1925 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -120,7 +120,7 @@ static void pch_pirq_init(device_t dev) pci_write_config8(dev, PIRQG_ROUT, pirq_routing); pci_write_config8(dev, PIRQH_ROUT, pirq_routing); - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index e7681fb..19ef098 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -126,7 +126,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0x28, reg32); } else { - /* IDE */ + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ diff --git a/src/southbridge/intel/ibexpeak/smbus.h b/src/southbridge/intel/ibexpeak/smbus.h index aeac573..0815bf4 100644 --- a/src/southbridge/intel/ibexpeak/smbus.h +++ b/src/southbridge/intel/ibexpeak/smbus.h @@ -171,7 +171,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device, outb((inb(smbus_base + SMBHSTCTL) | 0x40), smbus_base + SMBHSTCTL); - while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + while (!(inb(smbus_base + SMBHSTSTAT) & 1)); /* Poll for transaction completion */ do { status = inb(smbus_base + SMBHSTSTAT); @@ -184,7 +184,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device, outb(*buf++, smbus_base + SMBBLKDAT); outb(status, smbus_base + SMBHSTSTAT); } - } while(status & 0x01); + } while (status & 0x01); return 0; } @@ -214,7 +214,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device, outb((inb(smbus_base + SMBHSTCTL) | 0x40), smbus_base + SMBHSTCTL); - while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + while (!(inb(smbus_base + SMBHSTSTAT) & 1)); /* Poll for transaction completion */ do { status = inb(smbus_base + SMBHSTSTAT); @@ -234,7 +234,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device, smbus_base + SMBHSTCTL); } } - } while(status & 0x01); + } while (status & 0x01); return bytes_read; } diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index d11d531..0ad7e65 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -273,37 +273,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } static void southbridge_gate_memory_reset_real(int offset, @@ -849,7 +849,7 @@ void southbridge_smi_handler(void) } } - if(dump) { + if (dump) { dump_smi_status(smi_sts); } diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 96ab34e..a8a139c 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -94,7 +94,7 @@ static int hda_wait_for_ready(u8 *base) int timeout = 50; - while(timeout--) { + while (timeout--) { u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; @@ -122,7 +122,7 @@ static int hda_wait_for_valid(u8 *base) * same duration */ int timeout = 50; - while(timeout--) { + while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 1d20bbb..f8ec94e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -124,7 +124,7 @@ static void pch_pirq_init(device_t dev) * I am not so sure anymore he was right. */ - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0, int_line=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) @@ -194,7 +194,7 @@ static void pch_power_options(device_t dev) * If the option is not existent (Laptops), use Kconfig setting. */ get_option(&pwr_on, "power_on_after_fail"); - pwr_on = MAINBOARD_POWER_KEEP; + pwr_on = MAINBOARD_POWER_KEEP; reg16 = pci_read_config16(dev, GEN_PMCON_3); reg16 &= 0xfffe; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 43e5289..355db4b 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -485,7 +485,7 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap) &cap_msg, sizeof(cap_msg)) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; - } + } *cap = cap_msg.caps_sku; return 0; } @@ -650,7 +650,7 @@ static int me_icc_set_clock_enables(u32 mask) if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) { printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n"); return -1; - } else { + } else { printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask); } diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c index daabbbc..804fb81 100644 --- a/src/southbridge/intel/lynxpoint/reset.c +++ b/src/southbridge/intel/lynxpoint/reset.c @@ -19,10 +19,10 @@ void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); } void hard_reset(void) { - outb(0x06, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 4f0db1b..0102308 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -68,37 +68,37 @@ void southbridge_smi_set_eos(void) static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } } @@ -459,7 +459,7 @@ static void southbridge_smi_monitor(void) printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); for (i=0; i < 4; i++) - if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index ae8b6a0..6b21a3f 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -377,6 +377,6 @@ void soft_reset(void) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - /* The default value for CK804 is good. */ - /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ + /* The default value for CK804 is good. */ + /* Set VFSMAF (VID/FID System Management Action Field) to 2. */ } diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 9af2bbc..619ba4c 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -381,7 +381,7 @@ static int mcp55_early_setup_x(void) device_t dev; dev = PCI_DEV(busnx, devnx, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); - if(id == 0x036910de) { + if (id == 0x036910de) { busn[mcp55_num] = busnx; devn[mcp55_num] = devnx; diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c index 2df096a..2474ef3 100644 --- a/src/southbridge/nvidia/mcp55/nic.c +++ b/src/southbridge/nvidia/mcp55/nic.c @@ -127,26 +127,26 @@ static void nic_init(struct device *dev) struct device *dev_eeprom; dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); - if(dev_eeprom) { + if (dev_eeprom) { // if that is valid we will use that unsigned char dat[6]; int status; int i; - for(i=0;i<6;i++) { + for (i=0;i<6;i++) { status = smbus_read_byte(dev_eeprom, i); - if(status < 0) break; + if (status < 0) break; dat[i] = status & 0xff; } - if(status >= 0) { + if (status >= 0) { mac_l = 0; - for(i=3;i>=0;i--) { + for (i=3;i>=0;i--) { mac_l <<= 8; mac_l += dat[i]; } - if(mac_l != 0xffffffff) { + if (mac_l != 0xffffffff) { mac_l += nic_index; mac_h = 0; - for(i=5;i>=4;i--) { + for (i=5;i>=4;i--) { mac_h <<= 8; mac_h += dat[i]; } @@ -156,7 +156,7 @@ static void nic_init(struct device *dev) } } // if that is invalid we will read that from romstrap - if(!eeprom_valid) { + if (!eeprom_valid) { u32 *mac_pos; mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld mac_l = read32(mac_pos) + nic_index; // overflow? diff --git a/src/southbridge/nvidia/mcp55/sata.c b/src/southbridge/nvidia/mcp55/sata.c index fa761d2..4c2830e 100644 --- a/src/southbridge/nvidia/mcp55/sata.c +++ b/src/southbridge/nvidia/mcp55/sata.c @@ -35,7 +35,7 @@ static void sata_init(struct device *dev) dword = pci_read_config32(dev, 0x50); /* Ensure prefetch is disabled */ dword &= ~((1 << 15) | (1 << 13)); - if(conf) { + if (conf) { if (conf->sata1_enable) { /* Enable secondary SATA interface */ dword |= (1<<0); diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index 9db2117..8f2884a 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -48,7 +48,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) if ( (val & 0xff) != 0) { return 0; } - } while(--loops); + } while (--loops); return -3; } static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 083d064..8284ec8 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -166,7 +166,7 @@ static void rl5c476_read_resources(device_t dev) /* For CF socket we need an extra memory window for * the control structure of the CF itself */ - if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ + if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ /* fake index as it isn't in PCI config space */ resource = new_resource(dev, 1); resource->flags |= IORESOURCE_MEM; @@ -181,9 +181,9 @@ static void rl5c476_set_resources(device_t dev) { struct resource *resource; printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev)); - if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ + if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); - if( !(resource->flags & IORESOURCE_STORED) ){ + if ( !(resource->flags & IORESOURCE_STORED) ){ resource->flags |= IORESOURCE_STORED ; printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c index dfd146d..9c05cb1 100644 --- a/src/southbridge/sis/sis966/aza.c +++ b/src/southbridge/sis/sis966/aza.c @@ -56,7 +56,7 @@ static int set_bits(void *port, u32 mask, u32 val) udelay(100); } while ((dword != val) && --count); - if(!count) return -1; + if (!count) return -1; udelay(500); return 0; @@ -98,9 +98,9 @@ static int codec_detect(u8 *base) set_bits(base + 0x08, 1, 1); - do{ + do { dword = read32(base + 0x08)&0x1; - if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;} + if (idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;} } while (dword !=1); dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId @@ -184,7 +184,7 @@ static u32 verb_data[] = { static unsigned find_verb(u32 viddid, u32 **verb) { - if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; + if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; *verb = (u32 *)verb_data; return sizeof(verb_data)/sizeof(u32); } @@ -215,14 +215,14 @@ static void codec_init(u8 *base, int addr) printk(BIOS_DEBUG, "codec viddid: %08x\n", dword); verb_size = find_verb(dword, &verb); - if(!verb_size) { + if (!verb_size) { printk(BIOS_DEBUG, "No verb!\n"); return; } printk(BIOS_DEBUG, "verb_size: %d\n", verb_size); /* 3 */ - for(i=0; i<verb_size; i++) { + for (i=0; i<verb_size; i++) { send_verb(base,verb[i]); } printk(BIOS_DEBUG, "verb loaded!\n"); @@ -236,50 +236,50 @@ static void codecs_init(u8 *base, u32 codec_mask) static void aza_init(struct device *dev) { - u8 *base; - struct resource *res; - u32 codec_mask; + u8 *base; + struct resource *res; + u32 codec_mask; - printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n"); + printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n"); //-------------- enable AZA (SiS7502) ------------------------- { - u8 temp8; - int i=0; - while(SiS_SiS7502_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); - temp8 &= SiS_SiS7502_init[i][1]; - temp8 |= SiS_SiS7502_init[i][2]; - pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); - i++; - }; + u8 temp8; + int i=0; + while (SiS_SiS7502_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); + temp8 &= SiS_SiS7502_init[i][1]; + temp8 |= SiS_SiS7502_init[i][2]; + pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); + i++; + }; } //----------------------------------------------------------- - // put audio to D0 state - pci_write_config8(dev, 0x54,0x00); + // put audio to D0 state + pci_write_config8(dev, 0x54,0x00); #if DEBUG_AZA { - int i; - - printk(BIOS_DEBUG, "****** Azalia PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for (i=0;i<0xff;i+=4){ - if ((i%16)==0){ - printk(BIOS_DEBUG, "\n%02x: ", i); - } - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + int i; + + printk(BIOS_DEBUG, "****** Azalia PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for (i=0;i<0xff;i+=4){ + if ((i%16)==0){ + printk(BIOS_DEBUG, "\n%02x: ", i); + } + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } #endif res = find_resource(dev, 0x10); - if(!res) + if (!res) return; base = res2mmio(res, 0, 0); @@ -287,12 +287,12 @@ static void aza_init(struct device *dev) codec_mask = codec_detect(base); - if(codec_mask) { + if (codec_mask) { printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } - printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n"); + printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/early_setup_car.c b/src/southbridge/sis/sis966/early_setup_car.c index b9ee592..ba6d8a3 100644 --- a/src/southbridge/sis/sis966/early_setup_car.c +++ b/src/southbridge/sis/sis966/early_setup_car.c @@ -29,7 +29,7 @@ void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io dword |= 0x3f0; // disable it at first pci_write_config32(dev, 0xe4, dword); - for(i=0; i<3; i++) { + for (i=0; i<3; i++) { tgio_ctrl = inl(anactrl_io_base + 0xcc); tgio_ctrl &= ~(3<<9); tgio_ctrl |= (i<<9); diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 15d4f4c..4a2b867 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -37,7 +37,7 @@ int smbus_wait_until_ready(unsigned smbus_io_base) return 0; } outb(val,smbus_io_base + SMBHSTSTAT); - } while(--loops); + } while (--loops); return -2; } @@ -53,7 +53,7 @@ int smbus_wait_until_done(unsigned smbus_io_base) if ( (val & 0xff) != 0x02) { return 0; } - } while(--loops); + } while (--loops); return -3; } @@ -135,11 +135,10 @@ static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, un smbus_delay(); int i, j; - for(i = 0;i < 0x1000; i++) - { - if (inb(smbus_io_base + 0x00) != 0x08) - { smbus_delay(); - for(j=0;j<0xFFFF;j++); + for (i = 0;i < 0x1000; i++) { + if (inb(smbus_io_base + 0x00) != 0x08) { + smbus_delay(); + for (j=0;j<0xFFFF;j++); } } @@ -502,12 +501,13 @@ static const uint8_t SiS_SiS1183_init[44][3]={ }; /* In => Share Memory size - => 00h : 0MBytes - => 02h : 32MBytes - => 03h : 64MBytes - => 04h : 128MBytes - => Others: Reserved -*/ + * => 00h : 0MBytes + * => 02h : 32MBytes + * => 03h : 64MBytes + * => 03h : 64MBytes + * => 04h : 128MBytes + * => Others: Reserved + */ static void Init_Share_Memory(uint8_t ShareSize) { device_t dev; @@ -517,62 +517,62 @@ static void Init_Share_Memory(uint8_t ShareSize) } /* In: => Aperture size - => 00h : 32MBytes - => 01h : 64MBytes - => 02h : 128MBytes - => 03h : 256MBytes - => 04h : 512MBytes - => Others: Reserved -*/ + * => 00h : 32MBytes + * => 01h : 64MBytes + * => 02h : 128MBytes + * => 03h : 256MBytes + * => 04h : 512MBytes + * => Others: Reserved + */ static void Init_Aper_Size(uint8_t AperSize) { - device_t dev; - uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; + device_t dev; + uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); - pci_write_config8(dev, 0x90, AperSize << 1); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); + pci_write_config8(dev, 0x90, AperSize << 1); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); + pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]); } static void sis_init_stage1(void) { - device_t dev; - uint8_t temp8; - int i; - uint8_t GUI_En; + device_t dev; + uint8_t temp8; + int i; + uint8_t GUI_En; // SiS_Chipset_Initialization // ========================== NB ============================= dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); i=0; - while(SiS_NB_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_NB_init[i][0]); - temp8 &= SiS_NB_init[i][1]; - temp8 |= SiS_NB_init[i][2]; - pci_write_config8(dev, SiS_NB_init[i][0], temp8); - i++; + while (SiS_NB_init[i][0] != 0) { + temp8 = pci_read_config8(dev, SiS_NB_init[i][0]); + temp8 &= SiS_NB_init[i][1]; + temp8 |= SiS_NB_init[i][2]; + pci_write_config8(dev, SiS_NB_init[i][0], temp8); + i++; }; // ========================== LPC ============================= dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); i=0; - while(SiS_LPC_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]); - temp8 &= SiS_LPC_init[i][1]; - temp8 |= SiS_LPC_init[i][2]; - pci_write_config8(dev, SiS_LPC_init[i][0], temp8); - i++; + while (SiS_LPC_init[i][0] != 0) { + temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]); + temp8 &= SiS_LPC_init[i][1]; + temp8 |= SiS_LPC_init[i][2]; + pci_write_config8(dev, SiS_LPC_init[i][0], temp8); + i++; }; // ========================== ACPI ============================= i=0; - while(SiS_ACPI_init[i][0] != 0) - { temp8 = inb(0x800 + SiS_ACPI_init[i][0]); - temp8 &= SiS_ACPI_init[i][1]; - temp8 |= SiS_ACPI_init[i][2]; - outb(temp8, 0x800 + SiS_ACPI_init[i][0]); - i++; + while (SiS_ACPI_init[i][0] != 0) { + temp8 = inb(0x800 + SiS_ACPI_init[i][0]); + temp8 &= SiS_ACPI_init[i][1]; + temp8 |= SiS_ACPI_init[i][2]; + outb(temp8, 0x800 + SiS_ACPI_init[i][0]); + i++; }; // ========================== NBPCIE ============================= dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit @@ -582,12 +582,12 @@ static void sis_init_stage1(void) dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761_PCIE), 0); i=0; - while(SiS_NBPCIE_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]); - temp8 &= SiS_NBPCIE_init[i][1]; - temp8 |= SiS_NBPCIE_init[i][2]; - pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8); - i++; + while (SiS_NBPCIE_init[i][0] != 0) { + temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]); + temp8 &= SiS_NBPCIE_init[i][1]; + temp8 |= SiS_NBPCIE_init[i][2]; + pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8); + i++; }; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit temp8 = pci_read_config8(dev, 0x4C); @@ -608,20 +608,19 @@ static void sis_init_stage2(void) // ========================== NB_AGP ============================= - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit - pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit + pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0); - i=0; + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0); + i=0; - while(SiS_NBAGP_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]); - temp8 &= SiS_NBAGP_init[i][1]; - temp8 |= SiS_NBAGP_init[i][2]; - pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8); - i++; - }; + while (SiS_NBAGP_init[i][0] != 0) { + temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]); + temp8 &= SiS_NBAGP_init[i][1]; + temp8 |= SiS_NBAGP_init[i][2]; + pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8); + i++; + }; /** * Share Memory size @@ -640,38 +639,38 @@ static void sis_init_stage2(void) * => Others: Reserved */ - Init_Share_Memory(0x02); //0x02 : 32M - Init_Aper_Size(0x01); //0x1 : 64M + Init_Share_Memory(0x02); //0x02 : 32M + Init_Aper_Size(0x01); //0x1 : 64M // ========================== NB ============================= - printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n"); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - msr = rdmsr(0xC001001A); + printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n"); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); + msr = rdmsr(0xC001001A); printk(BIOS_DEBUG, "Memory Top Bound %x\n",msr.lo ); - temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; - temp16=0x0001<<(temp16-1); - temp16<<=8; + temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; + temp16=0x0001<<(temp16-1); + temp16<<=8; - printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); - pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); - pci_write_config8(dev, 0x7F, 0x08); // ACPI Base - outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function + printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); + pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); + pci_write_config8(dev, 0x7F, 0x08); // ACPI Base + outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function // ========================== ACPI ============================= i=0; printk(BIOS_DEBUG, "Init ACPI -------->\n"); - do - { temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]); - temp8 &= SiS_ACPI_2_init[i][1]; - temp8 |= SiS_ACPI_2_init[i][2]; - outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]); - i++; - }while(SiS_ACPI_2_init[i][0] != 0); + do { + temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]); + temp8 &= SiS_ACPI_2_init[i][1]; + temp8 |= SiS_ACPI_2_init[i][2]; + outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]); + i++; + } while (SiS_ACPI_2_init[i][0] != 0); // ========================== Misc ============================= - printk(BIOS_DEBUG, "Init Misc -------->\n"); + printk(BIOS_DEBUG, "Init Misc -------->\n"); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); /* R77h Internal PCI Device Enable 1 (Power On Value = 0h) diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index ebea6f3..5686227 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -101,15 +101,14 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); //-------------- enable IDE (SiS5513) ------------------------- { - uint8_t temp8; - int i=0; - while(SiS_SiS5513_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); - temp8 &= SiS_SiS5513_init[i][1]; - temp8 |= SiS_SiS5513_init[i][2]; - pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); - i++; + uint8_t temp8; + int i=0; + while (SiS_SiS5513_init[i][0] != 0) { + temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); + temp8 &= SiS_SiS5513_init[i][1]; + temp8 |= SiS_SiS5513_init[i][2]; + pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- @@ -143,17 +142,17 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); #if DEBUG_IDE { - int i; + int i; - printk(BIOS_DEBUG, "****** IDE PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** IDE PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for (i=0;i<0xff;i+=4){ - if ((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + for (i=0;i<0xff;i+=4) { + if ((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } #endif printk(BIOS_DEBUG, "IDE_INIT:<----------\n"); diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index ef26745..e1a356b 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -112,7 +112,7 @@ static void lpc_init(device_t dev) /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); - if(on) { + if (on) { uint16_t pm10_bar; uint32_t dword; pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); @@ -123,33 +123,33 @@ static void lpc_init(device_t dev) (on*12)+(on>>1),(on&1)*5); } - /* Enable Error reporting */ - /* Set up sync flood detected */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - - /* Set up NMI on errors */ - byte = inb(0x70); // RTC70 - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - } else { - byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW - } - if ( byte != byte_old) { - outb(byte, 0x70); - } - - /* Initialize the real time clock */ - cmos_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - printk(BIOS_DEBUG, "LPC_INIT <--------\n"); + /* Enable Error reporting */ + /* Set up sync flood detected */ + byte = pci_read_config8(dev, 0x47); + byte |= (1 << 1); + pci_write_config8(dev, 0x47, byte); + + /* Set up NMI on errors */ + byte = inb(0x70); // RTC70 + byte_old = byte; + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* set NMI */ + } else { + byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW + } + if ( byte != byte_old) { + outb(byte, 0x70); + } + + /* Initialize the real time clock */ + cmos_init(0); + + /* Initialize isa dma */ + isa_dma_init(); + + printk(BIOS_DEBUG, "LPC_INIT <--------\n"); } static void sis966_lpc_read_resources(device_t dev) @@ -195,11 +195,11 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) for (link = dev->link_list; link; link = link->next) { device_t child; for (child = link->children; child; child = child->sibling) { - if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { + if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; - for(res = child->resource_list; res; res = res->next) { + for (res = child->resource_list; res; res = res->next) { unsigned long base, end; // don't need long long - if(!(res->flags & IORESOURCE_IO)) continue; + if (!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); @@ -217,8 +217,8 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) case 0x300: // Midi 0 reg |= (1<<12); break; } - if( (base == 0x290) || (base >= 0x400)) { - if(var_num>=4) continue; // only 4 var ; compact them ? + if ( (base == 0x290) || (base >= 0x400)) { + if (var_num>=4) continue; // only 4 var ; compact them ? reg |= (1<<(28+var_num)); reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16); } @@ -227,7 +227,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) } } pci_write_config32(dev, 0xa0, reg); - for(i=0;i<var_num;i++) { + for (i=0;i<var_num;i++) { pci_write_config32(dev, 0xa8 + i*4, reg_var[i]); } diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index 0d014aa..a167848 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -51,73 +51,71 @@ u16 MacAddr[3]; static void writeApcByte(int addr, u8 value) { - outb(addr,0x78); - outb(value,0x79); + outb(addr,0x78); + outb(value,0x79); } static u8 readApcByte(int addr) { - u8 value; - outb(addr,0x78); - value=inb(0x79); - return(value); + u8 value; + outb(addr,0x78); + value=inb(0x79); + return(value); } static void readApcMacAddr(void) { - u8 i; + u8 i; // enable APC in south bridge sis966 D2F0 - outl(0x80001048,0xcf8); - outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data + outl(0x80001048,0xcf8); + outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - printk(BIOS_DEBUG, "MAC addr in APC = "); - for (i = 0x9 ; i <=0xe ; i++) - { - printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); - } - printk(BIOS_DEBUG, "\n"); + printk(BIOS_DEBUG, "MAC addr in APC = "); + for (i = 0x9 ; i <=0xe ; i++) { + printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); + } + printk(BIOS_DEBUG, "\n"); - /* Set APC Reload */ - writeApcByte(0x7,readApcByte(0x7)&0xf7); - writeApcByte(0x7,readApcByte(0x7)|0x0a); + /* Set APC Reload */ + writeApcByte(0x7,readApcByte(0x7)&0xf7); + writeApcByte(0x7,readApcByte(0x7)|0x0a); - /* disable APC in south bridge */ - outl(0x80001048,0xcf8); - outl(inl(0xcfc)&0xffffffbf,0xcfc); + /* disable APC in south bridge */ + outl(0x80001048,0xcf8); + outl(inl(0xcfc)&0xffffffbf,0xcfc); } static void set_apc(struct device *dev) { - u16 addr; - u16 i; - u8 bTmp; - - /* enable APC in south bridge sis966 D2F0 */ - outl(0x80001048,0xcf8); - outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - - for (i = 0 ; i <3; i++) - { - addr=0x9+2*i; - writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); - writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); - // printf("%x - ",readMacAddrByte(0x59+i)); - } - - /* Set APC Reload */ - writeApcByte(0x7,readApcByte(0x7)&0xf7); - writeApcByte(0x7,readApcByte(0x7)|0x0a); - - /* disable APC in south bridge */ - outl(0x80001048,0xcf8); - outl(inl(0xcfc)&0xffffffbf,0xcfc); - - // CFG reg0x73 bit=1, tell driver MAC Address load to APC - bTmp = pci_read_config8(dev, 0x73); - bTmp|=0x1; - pci_write_config8(dev, 0x73, bTmp); + u16 addr; + u16 i; + u8 bTmp; + + /* enable APC in south bridge sis966 D2F0 */ + outl(0x80001048,0xcf8); + outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data + + for (i = 0 ; i <3; i++) { + addr=0x9+2*i; + writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); + writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); + // printf("%x - ",readMacAddrByte(0x59+i)); + } + + /* Set APC Reload */ + writeApcByte(0x7,readApcByte(0x7)&0xf7); + writeApcByte(0x7,readApcByte(0x7)|0x0a); + + /* disable APC in south bridge */ + outl(0x80001048,0xcf8); + outl(inl(0xcfc)&0xffffffbf,0xcfc); + + // CFG reg0x73 bit=1, tell driver MAC Address load to APC + bTmp = pci_read_config8(dev, 0x73); + bTmp|=0x1; + pci_write_config8(dev, 0x73, bTmp); } /** @@ -131,100 +129,88 @@ static void set_apc(struct device *dev) #define LoopNum 200 static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) { - u32 data; - u32 i; - u32 ulValue; + u32 data; + u32 i; + u32 ulValue; + ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7 - ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7 + write32(base + 0x3c, ulValue); - write32(base + 0x3c, ulValue); + mdelay(10); - mdelay(10); + for (i=0 ; i <= LoopNum; i++) { + ulValue=read32(base + 0x3c); - for (i=0 ; i <= LoopNum; i++) - { - ulValue=read32(base + 0x3c); + if (!(ulValue & 0x0080)) //BIT_7 + break; - if (!(ulValue & 0x0080)) //BIT_7 - break; - - mdelay(100); - } + mdelay(100); + } - mdelay(50); + mdelay(50); - if (i==LoopNum) data=0x10000; - else{ - ulValue=read32(base + 0x3c); - data = ((ulValue & 0xffff0000) >> 16); - } + if (i==LoopNum) data=0x10000; + else { + ulValue=read32(base + 0x3c); + data = ((ulValue & 0xffff0000) >> 16); + } - return data; + return data; } static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg) { - u32 ulValue; - u32 Read_Cmd; - u16 usData; - - - - Read_Cmd = ((phy_reg << 11) | - (phy_addr << 6) | - SMI_READ | - SMI_REQUEST); - - // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC - write32(base + 0x44, Read_Cmd); - - // Polling SMI_REQ bit to be deasserted indicated read command completed - do - { - // Wait 20 usec before checking status - mdelay(20); - ulValue = read32(base + 0x44); - } while((ulValue & SMI_REQUEST) != 0); - //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); - usData=(ulValue>>16); - - + u32 ulValue; + u32 Read_Cmd; + u16 usData; + + Read_Cmd = ((phy_reg << 11) | + (phy_addr << 6) | + SMI_READ | + SMI_REQUEST); + + // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC + write32(base + 0x44, Read_Cmd); + + // Polling SMI_REQ bit to be deasserted indicated read command completed + do { + // Wait 20 usec before checking status + mdelay(20); + ulValue = read32(base + 0x44); + } while ((ulValue & SMI_REQUEST) != 0); + //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); + usData=(ulValue>>16); return usData; - } // Detect a valid PHY // If there exist a valid PHY then return TRUE, else return FALSE static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() { - int bFoundPhy = FALSE; - u16 usData; - int PhyAddress = 0; + int bFoundPhy = FALSE; + u16 usData; + int PhyAddress = 0; - // Scan all PHY address(0 ~ 31) to find a valid PHY - for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) - { + // Scan all PHY address(0 ~ 31) to find a valid PHY + for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) { usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h) - // Found a valid PHY - - if ((usData != 0x0) && (usData != 0xffff)) - { - bFoundPhy = TRUE; - break; - } - } + // Found a valid PHY + if ((usData != 0x0) && (usData != 0xffff)) { + bFoundPhy = TRUE; + break; + } + } - if (!bFoundPhy) - { - printk(BIOS_DEBUG, "PHY not found !!!!\n"); + if (!bFoundPhy) { + printk(BIOS_DEBUG, "PHY not found !!!!\n"); } - *PhyAddr=PhyAddress; + *PhyAddr=PhyAddress; return bFoundPhy; } @@ -232,59 +218,55 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() static void nic_init(struct device *dev) { - int val; - u16 PhyAddr; - u8 *base; - struct resource *res; + int val; + u16 PhyAddr; + u8 *base; + struct resource *res; - printk(BIOS_DEBUG, "NIC_INIT:---------->\n"); + printk(BIOS_DEBUG, "NIC_INIT:---------->\n"); //-------------- enable NIC (SiS19x) ------------------------- { - u8 temp8; - int i=0; - while(SiS_SiS191_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]); - temp8 &= SiS_SiS191_init[i][1]; - temp8 |= SiS_SiS191_init[i][2]; - pci_write_config8(dev, SiS_SiS191_init[i][0], temp8); - i++; + u8 temp8; + int i=0; + while (SiS_SiS191_init[i][0] != 0) { + temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]); + temp8 &= SiS_SiS191_init[i][1]; + temp8 |= SiS_SiS191_init[i][2]; + pci_write_config8(dev, SiS_SiS191_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- { - unsigned long i; - unsigned long ulValue; + unsigned long i; + unsigned long ulValue; res = find_resource(dev, 0x10); - if (!res) - { + if (!res) { printk(BIOS_DEBUG, "NIC Cannot find resource..\n"); return; } base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "NIC base address %p\n",base); + printk(BIOS_DEBUG, "NIC base address %p\n",base); - if (!(val=phy_detect(base,&PhyAddr))) - { - printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); + if (!(val=phy_detect(base,&PhyAddr))) { + printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); return; } - ulValue=read32(base + 0x38L); // check EEPROM existing + ulValue=read32(base + 0x38L); // check EEPROM existing - if ((ulValue & 0x0002)) - { + if ((ulValue & 0x0002)) { - // read MAC address from EEPROM at first + // read MAC address from EEPROM at first - // if that is valid we will use that + // if that is valid we will use that printk(BIOS_DEBUG, "EEPROM contents %lx\n",ReadEEprom( dev, base, 0LL)); - for(i=0;i<3;i++) { + for (i=0;i<3;i++) { //status = smbus_read_byte(dev_eeprom, i); ulValue=ReadEEprom( dev, base, i+3L); if (ulValue ==0x10000) break; // error @@ -292,31 +274,31 @@ static void nic_init(struct device *dev) MacAddr[i] =ulValue & 0xFFFF; } - }else{ - // read MAC address from firmware - printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue); - MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here - MacAddr[1]=read16((u16 *)0xffffffc2); - MacAddr[2]=read16((u16 *)0xffffffc4); - } + } else { + // read MAC address from firmware + printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue); + MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here + MacAddr[1]=read16((u16 *)0xffffffc2); + MacAddr[2]=read16((u16 *)0xffffffc4); + } - set_apc(dev); + set_apc(dev); - readApcMacAddr(); + readApcMacAddr(); #if DEBUG_NIC { - int i; + int i; - printk(BIOS_DEBUG, "****** NIC PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** NIC PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for (i=0;i<0xff;i+=4){ - if ((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + for (i=0;i<0xff;i+=4) { + if ((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index eb69ab0..3f114a0 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -109,22 +109,19 @@ static void sata_init(struct device *dev) { struct southbridge_sis_sis966_config *conf; - - conf = dev->chip_info; - printk(BIOS_DEBUG, "SATA_INIT:---------->\n"); + printk(BIOS_DEBUG, "SATA_INIT:---------->\n"); //-------------- enable IDE (SiS1183) ------------------------- { - uint8_t temp8; - int i=0; - while(SiS_SiS1183_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); - temp8 &= SiS_SiS1183_init[i][1]; - temp8 |= SiS_SiS1183_init[i][2]; - pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); - i++; + uint8_t temp8; + int i=0; + while (SiS_SiS1183_init[i][0] != 0) { + temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); + temp8 &= SiS_SiS1183_init[i][1]; + temp8 |= SiS_SiS1183_init[i][2]; + pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- @@ -133,33 +130,33 @@ static void sata_init(struct device *dev) uint32_t i,j; uint32_t temp32; -for (i=0;i<10;i++){ - temp32=0; - temp32= pci_read_config32(dev, 0xC0); - for ( j=0;j<0xFFFF;j++); - printk(BIOS_DEBUG, "status= %x\n",temp32); - if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break; +for (i=0;i<10;i++) { + temp32=0; + temp32= pci_read_config32(dev, 0xC0); + for ( j=0;j<0xFFFF;j++); + printk(BIOS_DEBUG, "status= %x\n",temp32); + if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break; } } #if DEBUG_SATA { - int i; + int i; - printk(BIOS_DEBUG, "****** SATA PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** SATA PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for (i=0;i<0xff;i+=4){ - if ((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + for (i=0;i<0xff;i+=4) { + if ((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } #endif - printk(BIOS_DEBUG, "SATA_INIT:<----------\n"); + printk(BIOS_DEBUG, "SATA_INIT:<----------\n"); } diff --git a/src/southbridge/sis/sis966/sis966.c b/src/southbridge/sis/sis966/sis966.c index 6ac15db..57d6498 100644 --- a/src/southbridge/sis/sis966/sis966.c +++ b/src/southbridge/sis/sis966/sis966.c @@ -70,7 +70,7 @@ void sis966_enable(device_t dev) conf = dev->chip_info; int i; - if(dev->device==0x0000) { + if (dev->device==0x0000) { reg = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (reg >> 16) & 0xffff; vendorid = reg & 0xffff; @@ -92,9 +92,9 @@ void sis966_enable(device_t dev) case PCI_DEVICE_ID_SIS_SIS966_NIC: devfn -= (7<<3); index = 10; - for(i=0;i<2;i++) { + for (i=0;i<2;i++) { lpc_dev = find_lpc_dev(dev, devfn - (i<<3)); - if(!lpc_dev) continue; + if (!lpc_dev) continue; index -= i; devfn -= (i<<3); break; @@ -112,7 +112,7 @@ void sis966_enable(device_t dev) devfn -= (4<<3); index = 22; i = (dev->path.pci.devfn) & 7; - if(i>0) { + if (i>0) { index -= (i+3); } break; @@ -124,14 +124,14 @@ void sis966_enable(device_t dev) index = 0; } - if(!lpc_dev) + if (!lpc_dev) lpc_dev = find_lpc_dev(dev, devfn); if ( !lpc_dev ) return; - if(index2!=0) { + if (index2!=0) { sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); - if(!sm_dev) return; + if (!sm_dev) return; if ( sm_dev ) { reg_old = reg = pci_read_config32(sm_dev, 0xe4); @@ -165,9 +165,9 @@ void sis966_enable(device_t dev) } - if( index == 16) { + if ( index == 16) { sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); - if(!sm_dev) return; + if (!sm_dev) return; final_reg = pci_read_config32(sm_dev, 0xe8); final_reg &= ~0x0057cf00; @@ -184,9 +184,9 @@ void sis966_enable(device_t dev) */ } - if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8 + if (index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); - if(!sm_dev) return; + if (!sm_dev) return; reg_old = pci_read_config32(sm_dev, 0xe8); if (final_reg != reg_old) { pci_write_config32(sm_dev, 0xe8, final_reg); diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c index 64398e2..3f4f98d 100644 --- a/src/southbridge/sis/sis966/usb.c +++ b/src/southbridge/sis/sis966/usb.c @@ -51,39 +51,39 @@ uint8_t SiS_SiS7001_init[16][3]={ static void usb_init(struct device *dev) { - printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n"); + printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n"); //-------------- enable USB1.1 (SiS7001) ------------------------- { - uint8_t temp8; - int i=0; + uint8_t temp8; + int i=0; - while(SiS_SiS7001_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]); - temp8 &= SiS_SiS7001_init[i][1]; - temp8 |= SiS_SiS7001_init[i][2]; - pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8); - i++; - }; + while (SiS_SiS7001_init[i][0] != 0) { + temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]); + temp8 &= SiS_SiS7001_init[i][1]; + temp8 |= SiS_SiS7001_init[i][2]; + pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8); + i++; + }; } //----------------------------------------------------------- #if DEBUG_USB { - int i; + int i; - printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for (i=0;i<0xff;i+=4){ - if ((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + for (i=0;i<0xff;i+=4) { + if ((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); } #endif - printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n"); + printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c index 8c34723..79e7d09 100644 --- a/src/southbridge/sis/sis966/usb2.c +++ b/src/southbridge/sis/sis966/usb2.c @@ -62,46 +62,45 @@ static const u8 SiS_SiS7002_init[22][3]={ static void usb2_init(struct device *dev) { - u8 *base; - struct resource *res; - int i; - u8 temp8; + u8 *base; + struct resource *res; + int i; + u8 temp8; - printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n"); + printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n"); //-------------- enable USB2.0 (SiS7002) ---------------------- i = 0; - while (SiS_SiS7002_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); - temp8 &= SiS_SiS7002_init[i][1]; - temp8 |= SiS_SiS7002_init[i][2]; - pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); - i++; - }; - - res = find_resource(dev, 0x10); - if (!res) - return; - - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "base = 0x%p\n", base); - write32(base + 0x20, 0x2); + while (SiS_SiS7002_init[i][0] != 0) { + temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); + temp8 &= SiS_SiS7002_init[i][1]; + temp8 |= SiS_SiS7002_init[i][2]; + pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); + i++; + }; + + res = find_resource(dev, 0x10); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "base = 0x%p\n", base); + write32(base + 0x20, 0x2); //------------------------------------------------------------- #if DEBUG_USB2 - printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); - printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for (i=0;i<0xff;i+=4){ - if ((i%16)==0) - printk(BIOS_DEBUG, "\n%02x: ", i); - printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); - } - printk(BIOS_DEBUG, "\n"); + printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for (i=0;i<0xff;i+=4) { + if ((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); + } + printk(BIOS_DEBUG, "\n"); #endif - printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n"); + printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 308efbe..e907528 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -107,7 +107,7 @@ k8m890_host_fb_size_get(void) { struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - if(!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA, + if (!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); unsigned char tmp; diff --git a/src/southbridge/via/vt8237r/smihandler.c b/src/southbridge/via/vt8237r/smihandler.c index fff3656..805c96e 100644 --- a/src/southbridge/via/vt8237r/smihandler.c +++ b/src/southbridge/via/vt8237r/smihandler.c @@ -245,7 +245,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav } } - if(dump) { + if (dump) { dump_smi_status(smi_sts); }

1 0

Patch merged into coreboot/master: src/drivers: Add required space before opening parenthesis '('
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit 2e4d80687dd79890c7c9edad8dbaf6e89edf2afc Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Aug 25 20:50:50 2016 +0200 src/drivers: Add required space before opening parenthesis '(' Change-Id: I4d0087b2557862d04be54cf42f01b3223cb723ac Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16321 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16321 for details. -gerrit

1 0

Patch merged into coreboot/master: northbridge/via: Add required space before opening parenthesis '('
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit d75b04f2b3baf75fdc52b06a319dddf0386f8e59 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Aug 23 21:24:38 2016 +0200 northbridge/via: Add required space before opening parenthesis '(' Change-Id: Ic644cf6792a5d360527e48e04c74ae92be0d1d4f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16284 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16284 for details. -gerrit

1 0

Patch merged into coreboot/master: src/soc: Add required space before opening parenthesis '('
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit 4a83f1cf24b793db40606febb8e27cee90452590 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Aug 25 21:07:59 2016 +0200 src/soc: Add required space before opening parenthesis '(' Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16324 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16324 for details. -gerrit

1 0

Patch merged into coreboot/master: src/console: Add required space before opening parenthesis '('
by gerrit＠coreboot.org 31 Aug '16

31 Aug '16

the following patch was just integrated into master: commit 3c80408fc8aa7b4099493acd7420f8d62ce65a48 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Aug 25 21:02:20 2016 +0200 src/console: Add required space before opening parenthesis '(' Change-Id: Ibb2ce383322c174bdb3bcc88ae35c17f179f6d21 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16323 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16323 for details. -gerrit

1 0

Patch set updated for coreboot: soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK.
by Martin Roth 31 Aug '16

31 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16343 -gerrit commit 0ffd4ca19c6ffdcb18d4c3978e924c14502044d7 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 28 19:18:38 2016 +0200 soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK. Change-Id: I5b69a8429eb2f7add08bc134d5d2366a1afe6a4f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/soc/broadcom/cygnus/ddr_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index 7fa2a56..7488750 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -317,14 +317,14 @@ int cygnus_phy_powerup(void) if(reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0) { - /* Step 1: POWRON */ + /* Step 1: POWER ON */ data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL); data |= 0x8;// assert power ON reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data); __udelay(2); - /* Step 2: POWROK */ + /* Step 2: POWER OK */ data |= 0x10;// assert power OK reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box
by Brandon Breitenstein 31 Aug '16

31 Aug '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16308 -gerrit commit e9ef6ebb6886a67423a3c63c0e39a4422e2df9ea Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Wed Jul 27 17:34:45 2016 -0700 drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box The following patch is based off of the UEFI 2.6 patch that I uploaded. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com># --- src/drivers/intel/fsp2_0/Kconfig | 2 +- src/drivers/intel/fsp2_0/debug.c | 14 +- src/drivers/intel/fsp2_0/include/fsp/api.h | 32 +- src/drivers/intel/fsp2_0/include/fsp/debug.h | 26 +- src/drivers/intel/fsp2_0/include/fsp/soc_binding.h | 31 ++ src/drivers/intel/fsp2_0/include/fsp/util.h | 10 +- src/drivers/intel/fsp2_0/memory_init.c | 12 +- src/drivers/intel/fsp2_0/notify.c | 3 +- src/drivers/intel/fsp2_0/silicon_init.c | 6 +- src/drivers/intel/fsp2_0/upd_display.c | 12 +- src/drivers/intel/fsp2_0/util.c | 4 +- src/mainboard/google/reef/romstage.c | 2 +- src/mainboard/intel/amenia/romstage.c | 6 +- src/soc/intel/apollolake/chip.c | 8 +- src/soc/intel/apollolake/include/FspUpd.h | 48 ++ src/soc/intel/apollolake/include/soc/fsp/FspUpd.h | 6 + src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 282 +++++------ src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 552 +++++++++++---------- src/soc/intel/apollolake/include/soc/meminit.h | 9 +- src/soc/intel/apollolake/include/soc/romstage.h | 2 +- src/soc/intel/apollolake/meminit.c | 18 +- src/soc/intel/apollolake/reset.c | 2 +- src/soc/intel/apollolake/romstage.c | 6 +- 23 files changed, 580 insertions(+), 513 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index af0706a..3ffb402 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -15,7 +15,7 @@ config PLATFORM_USES_FSP2_0 bool - select UEFI_2_4_BINDING + select UDK_2015_BINDING help Include FSP 2.0 wrappers and functionality diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index a003569..f36f6de 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -25,8 +25,8 @@ asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes) *----------- */ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, - const struct FSPM_UPD *fspm_old_upd, - const struct FSPM_UPD *fspm_new_upd) + const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) { /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) @@ -44,7 +44,7 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, printk(BIOS_SPEW, "\t0x%p: &hob_list_ptr\n", fsp_get_hob_list_ptr()); } -void fsp_debug_after_memory_init(enum fsp_status status) +void fsp_debug_after_memory_init(uint32_t status) { if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspMemoryInit returned 0x%08x\n", status); @@ -72,8 +72,8 @@ void fsp_debug_after_memory_init(enum fsp_status status) *----------- */ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init, - const struct FSPS_UPD *fsps_old_upd, - const struct FSPS_UPD *fsps_new_upd) + const FSPS_UPD *fsps_old_upd, + const FSPS_UPD *fsps_new_upd) { /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) @@ -90,7 +90,7 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init, printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd); } -void fsp_debug_after_silicon_init(enum fsp_status status) +void fsp_debug_after_silicon_init(uint32_t status) { if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); @@ -120,7 +120,7 @@ void fsp_before_debug_notify(fsp_notify_fn notify, printk(BIOS_SPEW, "\t0x%p: notify_params\n", notify_params); } -void fsp_debug_after_notify(enum fsp_status status) +void fsp_debug_after_notify(uint32_t status) { if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status); diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index a6228f2..b0436e8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -14,33 +14,9 @@ #define _FSP2_0_API_H_ #include <stddef.h> -#include <fsp/info_header.h> -#include <soc/fsp/FspmUpd.h> -#include <soc/fsp/FspsUpd.h> +#include <fsp/soc_binding.h> -enum fsp_status { - FSP_SUCCESS = 0x00000000, - FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001, - FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002, - FSP_STATUS_RESET_REQUIRED_3 = 0x40000003, - FSP_STATUS_RESET_REQUIRED_4 = 0x40000004, - FSP_STATUS_RESET_REQUIRED_5 = 0x40000005, - FSP_STATUS_RESET_REQUIRED_6 = 0x40000006, - FSP_STATUS_RESET_REQUIRED_7 = 0x40000007, - FSP_STATUS_RESET_REQUIRED_8 = 0x40000008, - FSP_INVALID_PARAMETER = 0x80000002, - FSP_UNSUPPORTED = 0x80000003, - FSP_NOT_READY = 0x80000006, - FSP_DEVICE_ERROR = 0x80000007, - FSP_OUT_OF_RESOURCES = 0x80000009, - FSP_VOLUME_CORRUPTED = 0x8000000a, - FSP_NOT_FOUND = 0x8000000a, - FSP_TIMEOUT = 0x80000012, - FSP_ABORTED = 0x80000015, - FSP_INCOMPATIBLE_VERSION = 0x80000010, - FSP_SECURITY_VIOLATION = 0x8000001a, - FSP_CRC_ERROR = 0x8000001b, -}; +#define FSP_SUCCESS EFI_SUCCESS enum fsp_boot_mode { FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00, @@ -64,8 +40,8 @@ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); /* Callbacks for updating stage-specific parameters */ -void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); -void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd); +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); /* Callback after processing FSP notify */ void platform_fsp_notify_status(enum fsp_notify_phase phase); diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 2f1d806..ef7131e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -16,18 +16,18 @@ /* FSP debug API */ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, - const struct FSPM_UPD *fspm_old_upd, - const struct FSPM_UPD *fspm_new_upd); -void fsp_debug_after_memory_init(enum fsp_status status); + const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd); +void fsp_debug_after_memory_init(uint32_t status); void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init, - const struct FSPS_UPD *fsps_old_upd, - const struct FSPS_UPD *fsps_new_upd); -void fsp_debug_after_silicon_init(enum fsp_status status); + const FSPS_UPD *fsps_old_upd, + const FSPS_UPD *fsps_new_upd); +void fsp_debug_after_silicon_init(uint32_t status); void fsp_before_debug_notify(fsp_notify_fn notify, const struct fsp_notify_params *notify_params); -void fsp_debug_after_notify(enum fsp_status status); -void fspm_display_upd_values(const struct FSPM_UPD *old, - const struct FSPM_UPD *new); +void fsp_debug_after_notify(uint32_t status); +void fspm_display_upd_values(const FSPM_UPD *old, + const FSPM_UPD *new); void fsp_display_hobs(void); void fsp_verify_memory_init_hobs(void); void fsp_print_header_info(const struct fsp_header *hdr); @@ -35,10 +35,10 @@ void fsp_print_header_info(const struct fsp_header *hdr); /* Callbacks for displaying UPD parameters - place in a separate file * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. */ -void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, - const struct FSPM_UPD *fspm_new_upd); -void soc_display_fsps_upd_params(const struct FSPS_UPD *fsps_old_upd, - const struct FSPS_UPD *fsps_new_upd); +void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd); +void soc_display_fsps_upd_params(const FSPS_UPD *fsps_old_upd, + const FSPS_UPD *fsps_new_upd); /* Callbacks for displaying HOBs - place in a separate file that is * conditionally build with CONFIG_DISPLAY_HOBS. diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h new file mode 100644 index 0000000..cfe5a02 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _FSP2_0_SOC_BINDING_H_ +#define _FSP2_0_SOC_BINDING_H_ + +#pragma pack(push) +/* + * This file is found in the soc / chipset directory. It is + * a per implementation specific header. i.e. different FSP implementations + * for different chipsets. + */ +#include <Base.h> +#include <soc/fsp/FspmUpd.h> +#include <soc/fsp/FspsUpd.h> + +#pragma pack(pop) + +#endif diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 269bb02..1c8dbba 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -83,15 +83,15 @@ uintptr_t fsp_load_vbt(void); * SoC. If the requested status is not a reboot status or unhandled, this * function does nothing. */ -void fsp_handle_reset(enum fsp_status status); +void fsp_handle_reset(uint32_t status); /* SoC/chipset must provide this to handle platform-specific reset codes */ -void chipset_handle_reset(enum fsp_status status); +void chipset_handle_reset(uint32_t status); -typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) +typedef asmlinkage uint32_t (*fsp_memory_init_fn) (void *raminit_upd, void **hob_list); -typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn)(void *silicon_upd); -typedef asmlinkage enum fsp_status (*fsp_notify_fn)(struct fsp_notify_params *); +typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); +typedef asmlinkage uint32_t (*fsp_notify_fn)(struct fsp_notify_params *); #include <fsp/debug.h> #endif /* _FSP2_0_UTIL_H_ */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 1957cdb..d0a22ce 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -103,7 +103,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) printk(BIOS_SPEW, "Romstage handoff structure not added!\n"); } -static void fsp_fill_mrc_cache(struct FSPM_ARCH_UPD *arch_upd, bool s3wake, +static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake, uint32_t fsp_version) { const struct mrc_saved_data *mrc_cache; @@ -152,7 +152,7 @@ static enum cb_err check_region_overlap(const struct memranges *ranges, return CB_SUCCESS; } -static enum cb_err fsp_fill_common_arch_params(struct FSPM_ARCH_UPD *arch_upd, +static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, bool s3wake, uint32_t fsp_version, const struct memranges *memmap) { @@ -183,14 +183,14 @@ static enum cb_err fsp_fill_common_arch_params(struct FSPM_ARCH_UPD *arch_upd, static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, const struct memranges *memmap) { - enum fsp_status status; + uint32_t status; fsp_memory_init_fn fsp_raminit; - struct FSPM_UPD fspm_upd, *upd; - struct FSPM_ARCH_UPD *arch_upd; + FSPM_UPD fspm_upd, *upd; + FSPM_ARCH_UPD *arch_upd; post_code(0x34); - upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); + upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) { die("Invalid FSPM signature!\n"); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 9879de0..8401653 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -13,7 +13,6 @@ #include <arch/cpu.h> #include <bootstate.h> #include <console/console.h> -#include <fsp/api.h> #include <fsp/util.h> #include <soc/intel/common/util.h> #include <string.h> @@ -21,7 +20,7 @@ static void fsp_notify(enum fsp_notify_phase phase) { - enum fsp_status ret; + uint32_t ret; fsp_notify_fn fspnotify; struct fsp_notify_params notify_params = { .phase = phase }; diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 562fec5..b911553 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -25,11 +25,11 @@ struct fsp_header fsps_hdr; static void do_silicon_init(struct fsp_header *hdr) { - struct FSPS_UPD upd, *supd; + FSPS_UPD upd, *supd; fsp_silicon_init_fn silicon_init; - enum fsp_status status; + uint32_t status; - supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); + supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) { die("Invalid FSPS signature\n"); diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index 694a66e..a588358 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -51,15 +51,15 @@ static void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old, /* Display the UPD parameters for MemoryInit */ __attribute__((weak)) void soc_display_fspm_upd_params( - const struct FSPM_UPD *fspm_old_upd, - const struct FSPM_UPD *fspm_new_upd) + const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) { printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); } -void fspm_display_upd_values(const struct FSPM_UPD *old, - const struct FSPM_UPD *new) +void fspm_display_upd_values(const FSPM_UPD *old, + const FSPM_UPD *new) { /* Display the UPD data */ fspm_display_arch_params(&old->FspmArchUpd, &new->FspmArchUpd); @@ -68,8 +68,8 @@ void fspm_display_upd_values(const struct FSPM_UPD *old, /* Display the UPD parameters for SiliconInit */ __attribute__((weak)) void soc_display_fsps_upd_params( - const struct FSPS_UPD *fsps_old_upd, - const struct FSPS_UPD *fsps_new_upd) + const FSPS_UPD *fsps_old_upd, + const FSPS_UPD *fsps_new_upd) { printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index aaa239e..e7e4f16 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -92,13 +92,13 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, return CB_SUCCESS; } -static bool fsp_reset_requested(enum fsp_status status) +static bool fsp_reset_requested(uint32_t status) { return (status >= FSP_STATUS_RESET_REQUIRED_COLD && status <= FSP_STATUS_RESET_REQUIRED_8); } -void fsp_handle_reset(enum fsp_status status) +void fsp_handle_reset(uint32_t status) { if (!fsp_reset_requested(status)) return; diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index 964dee4..4434890 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -142,7 +142,7 @@ static int get_mem_sku(void) return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); } -void mainboard_memory_init_params(struct FSPM_UPD *memupd) +void mainboard_memory_init_params(FSPM_UPD *memupd) { int mem_sku = get_mem_sku(); diff --git a/src/mainboard/intel/amenia/romstage.c b/src/mainboard/intel/amenia/romstage.c index d08b343..6719472 100644 --- a/src/mainboard/intel/amenia/romstage.c +++ b/src/mainboard/intel/amenia/romstage.c @@ -43,7 +43,7 @@ static const uint8_t swizzling_ch3_amenia[] = { 17, 23, 19, 16, 21, 22, 20, 18, 31, 29, 26, 25, 28, 27, 24, 30, }; -static void amenia_fill_memory_params(struct FSP_M_CONFIG *cfg) +static void amenia_fill_memory_params(FSP_M_CONFIG *cfg) { cfg->Profile = 11; /* 0xB:LPDDR4_2400_24_22_22 */ cfg->DIMM0SPDAddress = 0; @@ -87,9 +87,9 @@ static void amenia_fill_memory_params(struct FSP_M_CONFIG *cfg) sizeof(swizzling_ch3_amenia)); } -void mainboard_memory_init_params(struct FSPM_UPD *memupd) +void mainboard_memory_init_params(FSPM_UPD *memupd) { - struct FSP_M_CONFIG *cfg = &memupd->FspmConfig; + FSP_M_CONFIG *cfg = &memupd->FspmConfig; cfg->Package = 1; /* 0x1:BGA */ cfg->MemoryDown = 1; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1b109d0..9cec08d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -231,7 +231,7 @@ static void soc_final(void *data) global_reset_lock(); } -static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) { +static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) { switch (dev->path.pci.devfn) { case ISH_DEVFN: @@ -335,7 +335,7 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) { } } -static void parse_devicetree(struct FSP_S_CONFIG *silconfig) +static void parse_devicetree(FSP_S_CONFIG *silconfig) { struct device *dev = NB_DEV_ROOT; @@ -350,9 +350,9 @@ static void parse_devicetree(struct FSP_S_CONFIG *silconfig) } } -void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) { - struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; + FSP_S_CONFIG *silconfig = &silupd->FspsConfig; static struct soc_intel_apollolake_config *cfg; /* Load VBT before devicetree-specific config. */ diff --git a/src/soc/intel/apollolake/include/FspUpd.h b/src/soc/intel/apollolake/include/FspUpd.h new file mode 100644 index 0000000..a7114ce --- /dev/null +++ b/src/soc/intel/apollolake/include/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(push, 1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ + +#pragma pack(pop) + +#endif diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h index 4d865f5..a7114ce 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h @@ -33,10 +33,16 @@ are permitted provided that the following conditions are met: #ifndef __FSPUPD_H__ #define __FSPUPD_H__ +#include <FspEas.h> + +#pragma pack(push, 1) + #define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ #define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ #define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ +#pragma pack(pop) + #endif diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index 88d4c42..48225e0 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -33,87 +33,89 @@ are permitted provided that the following conditions are met: #ifndef __FSPMUPD_H__ #define __FSPMUPD_H__ -#include "FspUpd.h" -#include <fsp/upd.h> +#include <FspUpd.h> + +#pragma pack(push, 1) + #define MAX_CHANNELS_NUM 4 #define MAX_DIMMS_NUM 1 -struct DIMM_INFO { - uint8_t DimmId; - uint32_t SizeInMb; - uint16_t MfgId; +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; /** Module part number for DRR3 is 18 bytes but DRR4 is 20 bytes as per JEDEC Spec, so reserving 20 bytes **/ - uint8_t ModulePartNum[20]; -} __attribute__((packed)); - -struct CHANNEL_INFO { - uint8_t ChannelId; - uint8_t DimmCount; - struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} __attribute__((packed)); - -struct FSP_SMBIOS_MEMORY_INFO { - uint8_t Revision; - uint8_t DataWidth; + UINT8 ModulePartNum[20]; +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT8 DataWidth; /** As defined in SMBIOS 3.0 spec Section 7.18.2 and Table 75 **/ - uint16_t MemoryType; - uint16_t MemoryFrequencyInMHz; + UINT16 MemoryType; + UINT16 MemoryFrequencyInMHz; /** As defined in SMBIOS 3.0 spec Section 7.17.3 and Table 72 **/ - uint8_t ErrorCorrectionType; - uint8_t ChannelCount; - struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} __attribute__((packed)); + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; /** Fsp M Configuration **/ -struct FSP_M_CONFIG { +typedef struct { /** Offset 0x0040 - Debug Serial Port Base address Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. 0x00000000(Default). **/ - uint32_t SerialDebugPortAddress; + UINT32 SerialDebugPortAddress; /** Offset 0x0044 - Debug Serial Port Type 16550 compatible debug serial port resource type. NONE means no serial port support. 0x02:MMIO(Default). 0:NONE, 1:I/O, 2:MMIO **/ - uint8_t SerialDebugPortType; + UINT8 SerialDebugPortType; /** Offset 0x0045 - Serial Port Debug Device Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. 0x02:SOC UART2(Default). 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device **/ - uint8_t SerialDebugPortDevice; + UINT8 SerialDebugPortDevice; /** Offset 0x0046 - Debug Serial Port Stride Size Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). 0:1, 2:4 **/ - uint8_t SerialDebugPortStrideSize; + UINT8 SerialDebugPortStrideSize; /** Offset 0x0047 - Memory Fast Boot Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ - uint8_t MrcFastBoot; + UINT8 MrcFastBoot; /** Offset 0x0048 - Integrated Graphics Device Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ - uint8_t Igd; + UINT8 Igd; /** Offset 0x0049 - DVMT Pre-Allocated Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal @@ -122,35 +124,35 @@ struct FSP_M_CONFIG { MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, 0x0F:480 MB, 0x10:512 MB **/ - uint8_t IgdDvmt50PreAlloc; + UINT8 IgdDvmt50PreAlloc; /** Offset 0x004A - Aperture Size Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), 0x2:256 MB, 0x3:512 MB. 0x1:128 MB, 0x2:256 MB, 0x3:512 MB **/ - uint8_t IgdApertureSize; + UINT8 IgdApertureSize; /** Offset 0x004B - GTT Size Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 MB(Default). 0x1:2 MB, 0x2:4 MB, 0x3:8 MB **/ - uint8_t GttSize; + UINT8 GttSize; /** Offset 0x004C - Primary Display Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), 0x2:IGD, 0x3:PCI 0x0:AUTO, 0x2:IGD, 0x3:PCI **/ - uint8_t PrimaryVideoAdaptor; + UINT8 PrimaryVideoAdaptor; /** Offset 0x004D - Package NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. 0x00(Default). 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD **/ - uint8_t Package; + UINT8 Package; /** Offset 0x004E - Profile Profile list. 0x19(Default). @@ -167,127 +169,127 @@ struct FSP_M_CONFIG { 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 **/ - uint8_t Profile; + UINT8 Profile; /** Offset 0x004F - MemoryDown Memory Down. 0x0(Default). 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 **/ - uint8_t MemoryDown; + UINT8 MemoryDown; /** Offset 0x0050 - DDR3LPageSize NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB. 0x1:1KB, 0x2:2KB **/ - uint8_t DDR3LPageSize; + UINT8 DDR3LPageSize; /** Offset 0x0051 - DDR3LASR NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported. 0x0:Not Supported, 0x1:Supported **/ - uint8_t DDR3LASR; + UINT8 DDR3LASR; /** Offset 0x0052 - ScramblerSupport Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default). $EN_DIS **/ - uint8_t ScramblerSupport; + UINT8 ScramblerSupport; /** Offset 0x0053 - ChannelHashMask Channel Hash Mask. 0x00(Default). **/ - uint16_t ChannelHashMask; + UINT16 ChannelHashMask; /** Offset 0x0055 - SliceHashMask Slice Hash Mask. 0x00(Default). **/ - uint16_t SliceHashMask; + UINT16 SliceHashMask; /** Offset 0x0057 - InterleavedMode Interleaved Mode. 0x00:Disable(Default), 0x02:Enable. 0x0:Disable, 0x2:Enable **/ - uint8_t InterleavedMode; + UINT8 InterleavedMode; /** Offset 0x0058 - ChannelsSlicesEnable Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ - uint8_t ChannelsSlicesEnable; + UINT8 ChannelsSlicesEnable; /** Offset 0x0059 - MinRefRate2xEnable Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ - uint8_t MinRefRate2xEnable; + UINT8 MinRefRate2xEnable; /** Offset 0x005A - DualRankSupportEnable Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). $EN_DIS **/ - uint8_t DualRankSupportEnable; + UINT8 DualRankSupportEnable; /** Offset 0x005B - RmtMode Rank Margin Tool Mode. 0x00(Default). $EN_DIS **/ - uint8_t RmtMode; + UINT8 RmtMode; /** Offset 0x005C - MemorySizeLimit Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) **/ - uint16_t MemorySizeLimit; + UINT16 MemorySizeLimit; /** Offset 0x005E - LowMemoryMaxValue Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). **/ - uint16_t LowMemoryMaxValue; + UINT16 LowMemoryMaxValue; /** Offset 0x0060 - DisableFastBoot 00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train of memory. $EN_DIS **/ - uint8_t DisableFastBoot; + UINT8 DisableFastBoot; /** Offset 0x0061 - HighMemoryMaxValue High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). **/ - uint16_t HighMemoryMaxValue; + UINT16 HighMemoryMaxValue; /** Offset 0x0063 - DIMM0SPDAddress DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). **/ - uint8_t DIMM0SPDAddress; + UINT8 DIMM0SPDAddress; /** Offset 0x0064 - DIMM1SPDAddress DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). **/ - uint8_t DIMM1SPDAddress; + UINT8 DIMM1SPDAddress; /** Offset 0x0065 - Ch0_RankEnable NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default). **/ - uint8_t Ch0_RankEnable; + UINT8 Ch0_RankEnable; /** Offset 0x0066 - Ch0_DeviceWidth NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ - uint8_t Ch0_DeviceWidth; + UINT8 Ch0_DeviceWidth; /** Offset 0x0067 - Ch0_DramDensity NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ - uint8_t Ch0_DramDensity; + UINT8 Ch0_DramDensity; /** Offset 0x0068 - Ch0_Option Rank Select Interleaving Enable. See Address Mapping section for full description. @@ -297,22 +299,22 @@ struct FSP_M_CONFIG { This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B). 0x03(Default). **/ - uint8_t Ch0_Option; + UINT8 Ch0_Option; /** Offset 0x0069 - Ch0_OdtConfig ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. **/ - uint8_t Ch0_OdtConfig; + UINT8 Ch0_OdtConfig; /** Offset 0x006A - Ch0_TristateClk1 Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ - uint8_t Ch0_TristateClk1; + UINT8 Ch0_TristateClk1; /** Offset 0x006B - Ch0_Mode2N 2N Mode. 0x00(Default). **/ - uint8_t Ch0_Mode2N; + UINT8 Ch0_Mode2N; /** Offset 0x006C - Ch0_OdtLevels Rank Select Interleaving Enable. See Address Mapping section for full description. @@ -321,24 +323,24 @@ struct FSP_M_CONFIG { 0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved. [5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B). **/ - uint8_t Ch0_OdtLevels; + UINT8 Ch0_OdtLevels; /** Offset 0x006D - Ch1_RankEnable NOTE: Only for memory down. Set to 1 to enable Ch1 rank. **/ - uint8_t Ch1_RankEnable; + UINT8 Ch1_RankEnable; /** Offset 0x006E - Ch1_DeviceWidth NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default). 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ - uint8_t Ch1_DeviceWidth; + UINT8 Ch1_DeviceWidth; /** Offset 0x006F - Ch1_DramDensity NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default). 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ - uint8_t Ch1_DramDensity; + UINT8 Ch1_DramDensity; /** Offset 0x0070 - Ch1_Option Rank Select Interleaving Enable. See Address Mapping section for full description. @@ -348,45 +350,45 @@ struct FSP_M_CONFIG { [5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B), 0x03(Default). **/ - uint8_t Ch1_Option; + UINT8 Ch1_Option; /** Offset 0x0071 - Ch1_OdtConfig ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. **/ - uint8_t Ch1_OdtConfig; + UINT8 Ch1_OdtConfig; /** Offset 0x0072 - Ch1_TristateClk1 Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ - uint8_t Ch1_TristateClk1; + UINT8 Ch1_TristateClk1; /** Offset 0x0073 - Ch1_Mode2N 2N Mode. 0x00(Default). **/ - uint8_t Ch1_Mode2N; + UINT8 Ch1_Mode2N; /** Offset 0x0074 - Ch1_OdtLevels Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW. **/ - uint8_t Ch1_OdtLevels; + UINT8 Ch1_OdtLevels; /** Offset 0x0075 - Ch2_RankEnable NOTE: Only for memory down. Set to 1 to enable Ch2 rank. **/ - uint8_t Ch2_RankEnable; + UINT8 Ch2_RankEnable; /** Offset 0x0076 - Ch2_DeviceWidth NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ - uint8_t Ch2_DeviceWidth; + UINT8 Ch2_DeviceWidth; /** Offset 0x0077 - Ch2_DramDensity NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default). 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ - uint8_t Ch2_DramDensity; + UINT8 Ch2_DramDensity; /** Offset 0x0078 - Ch2_Option Rank Select Interleaving Enable. See Address Mapping section for full description.. @@ -396,47 +398,47 @@ struct FSP_M_CONFIG { [5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default). 01:2KB (B). **/ - uint8_t Ch2_Option; + UINT8 Ch2_Option; /** Offset 0x0079 - Ch2_OdtConfig ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG. **/ - uint8_t Ch2_OdtConfig; + UINT8 Ch2_OdtConfig; /** Offset 0x007A - Ch2_TristateClk1 Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ - uint8_t Ch2_TristateClk1; + UINT8 Ch2_TristateClk1; /** Offset 0x007B - Ch2_Mode2N 2N Mode. 0x00(Default). **/ - uint8_t Ch2_Mode2N; + UINT8 Ch2_Mode2N; /** Offset 0x007C - Ch2_OdtLevels Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. **/ - uint8_t Ch2_OdtLevels; + UINT8 Ch2_OdtLevels; /** Offset 0x007D - Ch3_RankEnable NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default). **/ - uint8_t Ch3_RankEnable; + UINT8 Ch3_RankEnable; /** Offset 0x007E - Ch3_DeviceWidth NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default), 0x01:x16, 0x02:x32, 0x03:x64. 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 **/ - uint8_t Ch3_DeviceWidth; + UINT8 Ch3_DeviceWidth; /** Offset 0x007F - Ch3_DramDensity NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default), 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb. 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb **/ - uint8_t Ch3_DramDensity; + UINT8 Ch3_DramDensity; /** Offset 0x0080 - Ch3_Option Rank Select Interleaving Enable. See Address Mapping section for full description.. @@ -446,272 +448,274 @@ struct FSP_M_CONFIG { [5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01 - 2KB (B). **/ - uint8_t Ch3_Option; + UINT8 Ch3_Option; /** Offset 0x0081 - Ch3_OdtConfig ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG. **/ - uint8_t Ch3_OdtConfig; + UINT8 Ch3_OdtConfig; /** Offset 0x0082 - Ch3_TristateClk1 Parameter used to determine whether to tristate CLK1. 0x00(Default). **/ - uint8_t Ch3_TristateClk1; + UINT8 Ch3_TristateClk1; /** Offset 0x0083 - Ch3_Mode2N 2N Mode. 0x00(Default). **/ - uint8_t Ch3_Mode2N; + UINT8 Ch3_Mode2N; /** Offset 0x0084 - Ch3_OdtLevels Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default), 1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW. **/ - uint8_t Ch3_OdtLevels; + UINT8 Ch3_OdtLevels; /** Offset 0x0085 - RmtCheckRun RmtCheckRun: 0x00(Default). **/ - uint8_t RmtCheckRun; + UINT8 RmtCheckRun; /** Offset 0x0086 - Ch0_Bit_swizzling Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. **/ - uint8_t Ch0_Bit_swizzling[32]; + UINT8 Ch0_Bit_swizzling[32]; /** Offset 0x00A6 - Ch1_Bit_swizzling Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. **/ - uint8_t Ch1_Bit_swizzling[32]; + UINT8 Ch1_Bit_swizzling[32]; /** Offset 0x00C6 - Ch2_Bit_swizzling Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. **/ - uint8_t Ch2_Bit_swizzling[32]; + UINT8 Ch2_Bit_swizzling[32]; /** Offset 0x00E6 - Ch3_Bit_swizzling Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. **/ - uint8_t Ch3_Bit_swizzling[32]; + UINT8 Ch3_Bit_swizzling[32]; /** Offset 0x0106 - RmtMarginCheckScaleHighThreshold RmtMarginCheckScaleHighThreshold. 0x0000(Default). **/ - uint16_t RmtMarginCheckScaleHighThreshold; + UINT16 RmtMarginCheckScaleHighThreshold; /** Offset 0x0108 - MsgLevelMask MsgLevelMask. 0x00000000(Default). **/ - uint32_t MsgLevelMask; + UINT32 MsgLevelMask; /** Offset 0x010C **/ - uint32_t UnusedUpdSpace0; + UINT32 UnusedUpdSpace0; /** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4 Number of Entries in PreMem GPIO Table. 0(Default). **/ - uint8_t PreMemGpioTableEntryNum; + UINT8 PreMemGpioTableEntryNum; /** Offset 0x0111 - PreMem GPIO Pin Number for each table Number of Pins in each PreMem GPIO Table. 0(Default). **/ - uint8_t PreMemGpioTablePinNum[4]; + UINT8 PreMemGpioTablePinNum[4]; /** Offset 0x0115 - PreMem GPIO Table Pointer Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default). **/ - uint32_t PreMemGpioTablePtr; + UINT32 PreMemGpioTablePtr; /** Offset 0x0119 - Enhance the port 8xh decoding Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t EnhancePort8xhDecoding; + UINT8 EnhancePort8xhDecoding; /** Offset 0x011A - OEM File Loading Address Determine the memory base address to load a specified file from CSE file system after memory is available. **/ - uint32_t OemLoadingBase; + UINT32 OemLoadingBase; /** Offset 0x011E - OEM File Name to Load Specify a file name to load from CSE file system after memory is available. Empty indicates no file needs to be loaded. **/ - uint8_t OemFileName[16]; + UINT8 OemFileName[16]; /** Offset 0x012E - SPD Data Write Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ - uint8_t SpdWriteEnable; + UINT8 SpdWriteEnable; /** Offset 0x012F - MRC Training Data Saving Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ - uint8_t MrcDataSaving; + UINT8 MrcDataSaving; /** Offset 0x0130 - eMMC Trace Length Select eMMC trace length to load OEM file from when loading OEM file name is specified. 0x0:Long(Default), 0x1:Short. 0x0:Long, 0x1:Short **/ - uint8_t eMMCTraceLen; + UINT8 eMMCTraceLen; /** Offset 0x0131 **/ - void* MrcBootDataPtr; + VOID* MrcBootDataPtr; /** Offset 0x0135 - Skip CSE RBP to support zero sized IBB Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of CSE. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ - uint8_t SkipCseRbp; + UINT8 SkipCseRbp; /** Offset 0x0136 - Npk Enable Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default). 0:Disable, 1:Enable, 2:Debugger, 3:Auto **/ - uint8_t NpkEn; + UINT8 NpkEn; /** Offset 0x0137 - FW Trace Enable Enable/Disable FW Trace. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t FwTraceEn; + UINT8 FwTraceEn; /** Offset 0x0138 - FW Trace Destination FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB, 4-NPK_TRACE_TO_PTI(Default). **/ - uint8_t FwTraceDestination; + UINT8 FwTraceDestination; /** Offset 0x0139 - NPK Recovery Dump Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t RecoverDump; + UINT8 RecoverDump; /** Offset 0x013A - Memory Region 0 Buffer WrapAround - Memory Region 0 Buffer WrapAround. 0-n0-wrap, 1-warp(Default). + Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). **/ - uint8_t Msc0Wrap; + UINT8 Msc0Wrap; /** Offset 0x013B - Memory Region 1 Buffer WrapAround Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). **/ - uint8_t Msc1Wrap; + UINT8 Msc1Wrap; /** Offset 0x013C - Memory Region 0 Buffer Size Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ - uint32_t Msc0Size; + UINT32 Msc0Size; /** Offset 0x0140 - Memory Region 1 Buffer Size Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ - uint32_t Msc1Size; + UINT32 Msc1Size; /** Offset 0x0144 - PTI Mode PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. **/ - uint8_t PtiMode; + UINT8 PtiMode; /** Offset 0x0145 - PTI Training PTI Training. 0-off(Default), 1-6=1-6. **/ - uint8_t PtiTraining; + UINT8 PtiTraining; /** Offset 0x0146 - PTI Speed PTI Speed. 0-full, 1-half, 2-quarter(Default). **/ - uint8_t PtiSpeed; + UINT8 PtiSpeed; /** Offset 0x0147 - Punit Message Level Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. **/ - uint8_t PunitMlvl; + UINT8 PunitMlvl; /** Offset 0x0148 - PMC Message Level PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. **/ - uint8_t PmcMlvl; + UINT8 PmcMlvl; /** Offset 0x0149 - SW Trace Enable Enable/Disable SW Trace. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SwTraceEn; + UINT8 SwTraceEn; /** Offset 0x014A - Periodic Retraining Disable Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. $EN_DIS **/ - uint8_t PeriodicRetrainingDisable; + UINT8 PeriodicRetrainingDisable; /** Offset 0x014B **/ - uint8_t ReservedFspmUpd[5]; -} __attribute__((packed)); + UINT8 ReservedFspmUpd[5]; +} FSP_M_CONFIG; /** Fsp M Test Configuration **/ -struct FSP_M_TEST_CONFIG { +typedef struct { /** Offset 0x0150 **/ - uint32_t Signature; + UINT32 Signature; /** Offset 0x0154 **/ - uint8_t ReservedFspmTestUpd[28]; -} __attribute__((packed)); + UINT8 ReservedFspmTestUpd[28]; +} FSP_M_TEST_CONFIG; /** Fsp M Restricted Configuration **/ -struct FSP_M_RESTRICTED_CONFIG { +typedef struct { /** Offset 0x0170 **/ - uint32_t Signature; + UINT32 Signature; /** Offset 0x0174 **/ - uint8_t ReservedFspmRestrictedUpd[138]; -} __attribute__((packed)); + UINT8 ReservedFspmRestrictedUpd[138]; +} FSP_M_RESTRICTED_CONFIG; /** Fsp M UPD Configuration **/ -struct FSPM_UPD { +typedef struct { /** Offset 0x0000 **/ - struct FSP_UPD_HEADER FspUpdHeader; + FSP_UPD_HEADER FspUpdHeader; /** Offset 0x0020 **/ - struct FSPM_ARCH_UPD FspmArchUpd; + FSPM_ARCH_UPD FspmArchUpd; /** Offset 0x0040 **/ - struct FSP_M_CONFIG FspmConfig; + FSP_M_CONFIG FspmConfig; /** Offset 0x0150 **/ - struct FSP_M_TEST_CONFIG FspmTestConfig; + FSP_M_TEST_CONFIG FspmTestConfig; /** Offset 0x0170 **/ - struct FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; + FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; /** Offset 0x01FE **/ - uint16_t UpdTerminator; -} __attribute__((packed)); + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack(pop) #endif diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index 26f70a7..553eba3 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -33,516 +33,518 @@ are permitted provided that the following conditions are met: #ifndef __FSPSUPD_H__ #define __FSPSUPD_H__ -#include "FspUpd.h" -#include <fsp/upd.h> +#include <FspUpd.h> + +#pragma pack(push, 1) + /** Fsp S Configuration **/ -struct FSP_S_CONFIG { +typedef struct { /** Offset 0x0020 - ActiveProcessorCores Number of active cores. 0:Disable(Default), 1:Enable. **/ - uint8_t ActiveProcessorCores; + UINT8 ActiveProcessorCores; /** Offset 0x0021 - Disable Core1 Disable/Enable Core1. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t DisableCore1; + UINT8 DisableCore1; /** Offset 0x0022 - Disable Core2 Disable/Enable Core2. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t DisableCore2; + UINT8 DisableCore2; /** Offset 0x0023 - Disable Core3 Disable/Enable Core3. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t DisableCore3; + UINT8 DisableCore3; /** Offset 0x0024 - VMX Enable Enable or Disable VMX. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t VmxEnable; + UINT8 VmxEnable; /** Offset 0x0025 - Memory region allocation for Processor Trace Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default) **/ - uint8_t ProcTraceMemSize; + UINT8 ProcTraceMemSize; /** Offset 0x0026 - Enable Processor Trace Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t ProcTraceEnable; + UINT8 ProcTraceEnable; /** Offset 0x0027 - Eist Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t Eist; + UINT8 Eist; /** Offset 0x0028 - Boot PState Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. **/ - uint8_t BootPState; + UINT8 BootPState; /** Offset 0x0029 - CPU power states (C-states) Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t EnableCx; + UINT8 EnableCx; /** Offset 0x002A - Enhanced C-states Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t C1e; + UINT8 C1e; /** Offset 0x002B - Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t BiProcHot; + UINT8 BiProcHot; /** Offset 0x002C - Max Pkg Cstate Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. **/ - uint8_t PkgCStateLimit; + UINT8 PkgCStateLimit; /** Offset 0x002D **/ - uint8_t UnusedUpdSpace0; + UINT8 UnusedUpdSpace0; /** Offset 0x002E - C-State auto-demotion C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion to C1 and C3. **/ - uint8_t CStateAutoDemotion; + UINT8 CStateAutoDemotion; /** Offset 0x002F - C-State un-demotion C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. **/ - uint8_t CStateUnDemotion; + UINT8 CStateUnDemotion; /** Offset 0x0030 - Max Core C-State Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). **/ - uint8_t MaxCoreCState; + UINT8 MaxCoreCState; /** Offset 0x0031 - Package C-State Demotion Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PkgCStateDemotion; + UINT8 PkgCStateDemotion; /** Offset 0x0032 - Package C-State Un-demotion Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PkgCStateUnDemotion; + UINT8 PkgCStateUnDemotion; /** Offset 0x0033 - Turbo Mode Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t TurboMode; + UINT8 TurboMode; /** Offset 0x0034 - SC HDA Verb Table Entry Number Number of Entries in Verb Table. 0(Default). **/ - uint8_t HdaVerbTableEntryNum; + UINT8 HdaVerbTableEntryNum; /** Offset 0x0035 - SC HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. 0x00000000(Default). **/ - uint32_t HdaVerbTablePtr; + UINT32 HdaVerbTablePtr; /** Offset 0x0039 - Enable/Disable P2SB device hidden. Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t P2sbUnhide; + UINT8 P2sbUnhide; /** Offset 0x003A - IPU Enable/Disable Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t IpuEn; + UINT8 IpuEn; /** Offset 0x003B - IMGU ACPI mode selection 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. 0:Disable, 1:IGFX Child device, 2:ACPI device **/ - uint8_t IpuAcpiMode; + UINT8 IpuAcpiMode; /** Offset 0x003C - GttMmAdr GttMmAdr structure for initialization. 0xBF000000(Default). **/ - uint32_t GttMmAdr; + UINT32 GttMmAdr; /** Offset 0x0040 - GmAdr GmAdr structure for initialization. 0xA0000000(Default). **/ - uint32_t GmAdr; + UINT32 GmAdr; /** Offset 0x0044 - Enable ForceWake Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t ForceWake; + UINT8 ForceWake; /** Offset 0x0045 - Enable PavpLock Enable/disable PavpLock. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PavpLock; + UINT8 PavpLock; /** Offset 0x0046 - Enable GraphicsFreqModify Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t GraphicsFreqModify; + UINT8 GraphicsFreqModify; /** Offset 0x0047 - Enable GraphicsFreqReq Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t GraphicsFreqReq; + UINT8 GraphicsFreqReq; /** Offset 0x0048 - Enable GraphicsVideoFreq Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t GraphicsVideoFreq; + UINT8 GraphicsVideoFreq; /** Offset 0x0049 - Enable PmLock Enable/disable PmLock. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PmLock; + UINT8 PmLock; /** Offset 0x004A - Enable DopClockGating Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t DopClockGating; + UINT8 DopClockGating; /** Offset 0x004B - Enable UnsolicitedAttackOverride Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t UnsolicitedAttackOverride; + UINT8 UnsolicitedAttackOverride; /** Offset 0x004C - Enable WOPCMSupport Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t WOPCMSupport; + UINT8 WOPCMSupport; /** Offset 0x004D - Enable WOPCMSize Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t WOPCMSize; + UINT8 WOPCMSize; /** Offset 0x004E - Enable PowerGating Enable/disable PowerGating. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PowerGating; + UINT8 PowerGating; /** Offset 0x004F - Enable UnitLevelClockGating Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t UnitLevelClockGating; + UINT8 UnitLevelClockGating; /** Offset 0x0050 - Enable FastBoot Enable/disable FastBoot. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t FastBoot; + UINT8 FastBoot; /** Offset 0x0051 - Enable DynSR Enable/disable DynSR. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t DynSR; + UINT8 DynSR; /** Offset 0x0052 - Enable SaIpuEnable Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SaIpuEnable; + UINT8 SaIpuEnable; /** Offset 0x0053 - BMP Logo Data Size BMP logo data buffer size. 0x00000000(Default). **/ - uint32_t LogoSize; + UINT32 LogoSize; /** Offset 0x0057 - BMP Logo Data Pointer BMP logo data pointer to a BMP format buffer. 0x00000000(Default). **/ - uint32_t LogoPtr; + UINT32 LogoPtr; /** Offset 0x005B - Graphics Configuration Data Pointer Graphics configuration data used for initialization. 0x00000000(Default). **/ - uint32_t GraphicsConfigPtr; + UINT32 GraphicsConfigPtr; /** Offset 0x005F - GT PM Support Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PmSupport; + UINT8 PmSupport; /** Offset 0x0060 - RC6(Render Standby) Enable/Disable render standby support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t EnableRenderStandby; + UINT8 EnableRenderStandby; /** Offset 0x0061 - PAVP Enable Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PavpEnable; + UINT8 PavpEnable; /** Offset 0x0062 - PAVP PR3 Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PavpPr3; + UINT8 PavpPr3; /** Offset 0x0063 - CdClock Frequency selection 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz **/ - uint8_t CdClock; + UINT8 CdClock; /** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PeiGraphicsPeimInit; + UINT8 PeiGraphicsPeimInit; /** Offset 0x0065 - Write Protection Support Enable/disable Write Protection. 0:Disable, 1:Enable(Default). **/ - uint8_t WriteProtectionEnable[5]; + UINT8 WriteProtectionEnable[5]; /** Offset 0x006A - Read Protection Support Enable/disable Read Protection. 0:Disable, 1:Enable(Default). **/ - uint8_t ReadProtectionEnable[5]; + UINT8 ReadProtectionEnable[5]; /** Offset 0x006F - Protected Range Limitation The address of the upper limit of protection, 0x0FFFh(Default). **/ - uint16_t ProtectedRangeLimit[5]; + UINT16 ProtectedRangeLimit[5]; /** Offset 0x0079 - Protected Range Base The base address of the upper limit of protection. 0x0000(Default). **/ - uint16_t ProtectedRangeBase[5]; + UINT16 ProtectedRangeBase[5]; /** Offset 0x0083 - Enable SC Gaussian Mixture Models Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t Gmm; + UINT8 Gmm; /** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingPgcbClkTrunk; + UINT8 ClkGatingPgcbClkTrunk; /** Offset 0x0085 - GMM Clock Gating - Sideband Enable/disable Sideband. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingSb; + UINT8 ClkGatingSb; /** Offset 0x0086 - GMM Clock Gating - Sideband Enable/disable Sideband. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingSbClkTrunk; + UINT8 ClkGatingSbClkTrunk; /** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingSbClkPartition; + UINT8 ClkGatingSbClkPartition; /** Offset 0x0088 - GMM Clock Gating - Core Enable/disable Core. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingCore; + UINT8 ClkGatingCore; /** Offset 0x0089 - GMM Clock Gating - DMA Enable/disable DMA. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingDma; + UINT8 ClkGatingDma; /** Offset 0x008A - GMM Clock Gating - Register Access Enable/disable Register Access. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingRegAccess; + UINT8 ClkGatingRegAccess; /** Offset 0x008B - GMM Clock Gating - Host Enable/disable Host. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingHost; + UINT8 ClkGatingHost; /** Offset 0x008C - GMM Clock Gating - Partition Enable/disable Partition. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingPartition; + UINT8 ClkGatingPartition; /** Offset 0x008D - Clock Gating - Trunk Enable/disable Trunk. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ClkGatingTrunk; + UINT8 ClkGatingTrunk; /** Offset 0x008E - HD Audio Support Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t HdaEnable; + UINT8 HdaEnable; /** Offset 0x008F - HD Audio DSP Support Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t DspEnable; + UINT8 DspEnable; /** Offset 0x0090 - Azalia wake-on-ring Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t Pme; + UINT8 Pme; /** Offset 0x0091 - HD-Audio I/O Buffer Ownership Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default) 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers **/ - uint8_t HdAudioIoBufferOwnership; + UINT8 HdAudioIoBufferOwnership; /** Offset 0x0092 - HD-Audio I/O Buffer Voltage HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. 0: 3.3V, 1: 1.8V **/ - uint8_t HdAudioIoBufferVoltage; + UINT8 HdAudioIoBufferVoltage; /** Offset 0x0093 - HD-Audio Virtual Channel Type HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. 0: VC0, 1: VC1 **/ - uint8_t HdAudioVcType; + UINT8 HdAudioVcType; /** Offset 0x0094 - HD-Audio Link Frequency HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid. 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid **/ - uint8_t HdAudioLinkFrequency; + UINT8 HdAudioLinkFrequency; /** Offset 0x0095 - HD-Audio iDisp-Link Frequency HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, 4:96MHz, 5:Invalid. 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid **/ - uint8_t HdAudioIDispLinkFrequency; + UINT8 HdAudioIDispLinkFrequency; /** Offset 0x0096 - HD-Audio iDisp-Link T-Mode HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. 0: 2T, 1: 1T **/ - uint8_t HdAudioIDispLinkTmode; + UINT8 HdAudioIDispLinkTmode; /** Offset 0x0097 - HD-Audio Disp DMIC HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. 0: Disable, 1: 2ch array, 2: 4ch array **/ - uint8_t DspEndpointDmic; + UINT8 DspEndpointDmic; /** Offset 0x0098 - HD-Audio Bluetooth Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t DspEndpointBluetooth; + UINT8 DspEndpointBluetooth; /** Offset 0x0099 - HD-Audio I2S SHK Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t DspEndpointI2sSkp; + UINT8 DspEndpointI2sSkp; /** Offset 0x009A - HD-Audio I2S HP Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t DspEndpointI2sHp; + UINT8 DspEndpointI2sHp; /** Offset 0x009B - HD-Audio Controller Power Gating Enable/Disable HD-Audio Controller Power Gating. This option is deprecated. $EN_DIS **/ - uint8_t AudioCtlPwrGate; + UINT8 AudioCtlPwrGate; /** Offset 0x009C - HD-Audio ADSP Power Gating Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated. $EN_DIS **/ - uint8_t AudioDspPwrGate; + UINT8 AudioDspPwrGate; /** Offset 0x009D - HD-Audio CSME Memory Transfers Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. 0: VC0, 1: VC2 **/ - uint8_t Mmt; + UINT8 Mmt; /** Offset 0x009E - HD-Audio Host Memory Transfers Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. 0: VC0, 1: VC2 **/ - uint8_t Hmt; + UINT8 Hmt; /** Offset 0x009F - HD-Audio BIOS Configuration Lock Down Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t BiosCfgLockDown; + UINT8 BiosCfgLockDown; /** Offset 0x00A0 - HD-Audio Power Gating Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t HDAudioPwrGate; + UINT8 HDAudioPwrGate; /** Offset 0x00A1 - HD-Audio Clock Gatingn Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t HDAudioClkGate; + UINT8 HDAudioClkGate; /** Offset 0x00A2 - Bitmask of DSP Feature Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). @@ -550,7 +552,7 @@ struct FSP_S_CONFIG { - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: Intel WoV, 1: Windows Voice Activation **/ - uint32_t DspFeatureMask; + UINT32 DspFeatureMask; /** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). @@ -558,726 +560,726 @@ struct FSP_S_CONFIG { - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: Intel WoV, 1: Windows Voice Activation **/ - uint32_t DspPpModuleMask; + UINT32 DspPpModuleMask; /** Offset 0x00AA - Enable High Precision Timer Enable/Disable Hpet. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t Hpet; + UINT8 Hpet; /** Offset 0x00AB - Hpet Valid BDF Value Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t HpetBdfValid; + UINT8 HpetBdfValid; /** Offset 0x00AC - Bus Number of Hpet Completer ID of Bus Number of Hpet. Default = 0xFA(Default). **/ - uint8_t HpetBusNumber; + UINT8 HpetBusNumber; /** Offset 0x00AD - Device Number of Hpet Completer ID of Device Number of Hpet. 0x1F(Default). **/ - uint8_t HpetDeviceNumber; + UINT8 HpetDeviceNumber; /** Offset 0x00AE - Function Number of Hpet Completer ID of Function Number of Hpet. 0x00(Default). **/ - uint8_t HpetFunctionNumber; + UINT8 HpetFunctionNumber; /** Offset 0x00AF **/ - uint32_t UnusedUpdSpace1; + UINT32 UnusedUpdSpace1; /** Offset 0x00B3 - IoApic Valid BDF Value Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t IoApicBdfValid; + UINT8 IoApicBdfValid; /** Offset 0x00B4 - Bus Number of IoApic Completer ID of Bus Number of IoApic. 0xFA(Default). **/ - uint8_t IoApicBusNumber; + UINT8 IoApicBusNumber; /** Offset 0x00B5 - Device Number of IoApic Completer ID of Device Number of IoApic. 0x0F(Default). **/ - uint8_t IoApicDeviceNumber; + UINT8 IoApicDeviceNumber; /** Offset 0x00B6 - Function Number of IoApic Completer ID of Function Number of IoApic. 0x00(Default). **/ - uint8_t IoApicFunctionNumber; + UINT8 IoApicFunctionNumber; /** Offset 0x00B7 - IOAPIC Entry 24-119 Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t IoApicEntry24_119; + UINT8 IoApicEntry24_119; /** Offset 0x00B8 - IO APIC ID This member determines IOAPIC ID. 0x01(Default). **/ - uint8_t IoApicId; + UINT8 IoApicId; /** Offset 0x00B9 - IoApic Range Define address bits 19:12 for the IOxAPIC range. 0x00(Default). **/ - uint8_t IoApicRangeSelect; + UINT8 IoApicRangeSelect; /** Offset 0x00BA - ISH Controller Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t IshEnable; + UINT8 IshEnable; /** Offset 0x00BB - BIOS Interface Lock Down Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t BiosInterface; + UINT8 BiosInterface; /** Offset 0x00BC - Bios LockDown Enable Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t BiosLock; + UINT8 BiosLock; /** Offset 0x00BD - SPI EISS Status Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t SpiEiss; + UINT8 SpiEiss; /** Offset 0x00BE - BiosLock SWSMI Number This member describes the SwSmi value for Bios Lock. 0xA9(Default). **/ - uint8_t BiosLockSwSmiNumber; + UINT8 BiosLockSwSmiNumber; /** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t LPSS_S0ixEnable; + UINT8 LPSS_S0ixEnable; /** Offset 0x00C0 - LPSS I2C Clock Gating Configuration Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). **/ - uint8_t I2cClkGateCfg[8]; + UINT8 I2cClkGateCfg[8]; /** Offset 0x00C8 - PSS HSUART Clock Gating Configuration Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). **/ - uint8_t HsuartClkGateCfg[4]; + UINT8 HsuartClkGateCfg[4]; /** Offset 0x00CC - LPSS SPI Clock Gating Configuration Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). **/ - uint8_t SpiClkGateCfg[3]; + UINT8 SpiClkGateCfg[3]; /** Offset 0x00CF - I2C Device 0 Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t I2c0Enable; + UINT8 I2c0Enable; /** Offset 0x00D0 - I2C Device 1 Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t I2c1Enable; + UINT8 I2c1Enable; /** Offset 0x00D1 - I2C Device 2 Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t I2c2Enable; + UINT8 I2c2Enable; /** Offset 0x00D2 - I2C Device 3 Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t I2c3Enable; + UINT8 I2c3Enable; /** Offset 0x00D3 - I2C Device 4 Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t I2c4Enable; + UINT8 I2c4Enable; /** Offset 0x00D4 - I2C Device 5 Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t I2c5Enable; + UINT8 I2c5Enable; /** Offset 0x00D5 - I2C Device 6 Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t I2c6Enable; + UINT8 I2c6Enable; /** Offset 0x00D6 - I2C Device 7 Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t I2c7Enable; + UINT8 I2c7Enable; /** Offset 0x00D7 - UART Device 0 Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t Hsuart0Enable; + UINT8 Hsuart0Enable; /** Offset 0x00D8 - UART Device 1 Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t Hsuart1Enable; + UINT8 Hsuart1Enable; /** Offset 0x00D9 - UART Device 2 Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t Hsuart2Enable; + UINT8 Hsuart2Enable; /** Offset 0x00DA - UART Device 3 Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t Hsuart3Enable; + UINT8 Hsuart3Enable; /** Offset 0x00DB - SPI UART Device 0 Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t Spi0Enable; + UINT8 Spi0Enable; /** Offset 0x00DC - SPI UART Device 1 Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t Spi1Enable; + UINT8 Spi1Enable; /** Offset 0x00DD - SPI UART Device 2 Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. 0: Disabled, 1: PCI Mode, 2: ACPI Mode **/ - uint8_t Spi2Enable; + UINT8 Spi2Enable; /** Offset 0x00DE - UART Debug Base Address UART Debug Base Address. 0x00000000(Default). **/ - uint32_t Uart2KernelDebugBaseAddress; + UINT32 Uart2KernelDebugBaseAddress; /** Offset 0x00E2 - OS Debug Feature Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. $EN_DIS **/ - uint8_t OsDbgEnable; + UINT8 OsDbgEnable; /** Offset 0x00E3 - DCI Feature Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable. $EN_DIS **/ - uint8_t DciEn; + UINT8 DciEn; /** Offset 0x00E4 - Enable PCIE Clock Gating Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). 0:Enable, 1:Disable **/ - uint8_t PcieClockGatingDisabled; + UINT8 PcieClockGatingDisabled; /** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t PcieRootPort8xhDecode; + UINT8 PcieRootPort8xhDecode; /** Offset 0x00E6 - PCIE 8xh Decode Port Index PCIE 8xh Decode Port Index. 0x00(Default). **/ - uint8_t Pcie8xhDecodePortIndex; + UINT8 Pcie8xhDecodePortIndex; /** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PcieRootPortPeerMemoryWriteEnable; + UINT8 PcieRootPortPeerMemoryWriteEnable; /** Offset 0x00E8 - PCIE SWSMI Number This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). **/ - uint8_t PcieAspmSwSmiNumber; + UINT8 PcieAspmSwSmiNumber; /** Offset 0x00E9 - PCI Express Root Port Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). **/ - uint8_t PcieRootPortEn[6]; + UINT8 PcieRootPortEn[6]; /** Offset 0x00EF - Hide PCIE Root Port Configuration Space Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. **/ - uint8_t PcieRpHide[6]; + UINT8 PcieRpHide[6]; /** Offset 0x00F5 - PCIE Root Port Slot Implement Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). **/ - uint8_t PcieRpSlotImplemented[6]; + UINT8 PcieRpSlotImplemented[6]; /** Offset 0x00FB - Hot Plug PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). **/ - uint8_t PcieRpHotPlug[6]; + UINT8 PcieRpHotPlug[6]; /** Offset 0x0101 - PCIE PM SCI Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. **/ - uint8_t PcieRpPmSci[6]; + UINT8 PcieRpPmSci[6]; /** Offset 0x0107 - PCIE Root Port Extended Sync Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). **/ - uint8_t PcieRpExtSync[6]; + UINT8 PcieRpExtSync[6]; /** Offset 0x010D - Transmitter Half Swing Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). **/ - uint8_t PcieRpTransmitterHalfSwing[6]; + UINT8 PcieRpTransmitterHalfSwing[6]; /** Offset 0x0113 - ACS Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). **/ - uint8_t PcieRpAcsEnabled[6]; + UINT8 PcieRpAcsEnabled[6]; /** Offset 0x0119 - Clock Request Support Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). **/ - uint8_t PcieRpClkReqSupported[6]; + UINT8 PcieRpClkReqSupported[6]; /** Offset 0x011F - Configure CLKREQ Number Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, 0x01, 0x02, 0x03. **/ - uint8_t PcieRpClkReqNumber[6]; + UINT8 PcieRpClkReqNumber[6]; /** Offset 0x0125 - CLKREQ# Detection Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. **/ - uint8_t PcieRpClkReqDetect[6]; + UINT8 PcieRpClkReqDetect[6]; /** Offset 0x012B - Advanced Error Reporting Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. **/ - uint8_t AdvancedErrorReporting[6]; + UINT8 AdvancedErrorReporting[6]; /** Offset 0x0131 - PME Interrupt Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. **/ - uint8_t PmeInterrupt[6]; + UINT8 PmeInterrupt[6]; /** Offset 0x0137 - URR PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. **/ - uint8_t UnsupportedRequestReport[6]; + UINT8 UnsupportedRequestReport[6]; /** Offset 0x013D - FER PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. **/ - uint8_t FatalErrorReport[6]; + UINT8 FatalErrorReport[6]; /** Offset 0x0143 - NFER PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. **/ - uint8_t NoFatalErrorReport[6]; + UINT8 NoFatalErrorReport[6]; /** Offset 0x0149 - CER PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. **/ - uint8_t CorrectableErrorReport[6]; + UINT8 CorrectableErrorReport[6]; /** Offset 0x014F - SEFE Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. **/ - uint8_t SystemErrorOnFatalError[6]; + UINT8 SystemErrorOnFatalError[6]; /** Offset 0x0155 - SENFE Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. **/ - uint8_t SystemErrorOnNonFatalError[6]; + UINT8 SystemErrorOnNonFatalError[6]; /** Offset 0x015B - SECE Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. **/ - uint8_t SystemErrorOnCorrectableError[6]; + UINT8 SystemErrorOnCorrectableError[6]; /** Offset 0x0161 - PCIe Speed Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. **/ - uint8_t PcieRpSpeed[6]; + UINT8 PcieRpSpeed[6]; /** Offset 0x0167 - Physical Slot Number Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. **/ - uint8_t PhysicalSlotNumber[6]; + UINT8 PhysicalSlotNumber[6]; /** Offset 0x016D - CTO Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. **/ - uint8_t PcieRpCompletionTimeout[6]; + UINT8 PcieRpCompletionTimeout[6]; /** Offset 0x0173 - PTM Support Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. **/ - uint8_t PtmEnable[6]; + UINT8 PtmEnable[6]; /** Offset 0x0179 - ASPM PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, 4:Auto(Default). **/ - uint8_t PcieRpAspm[6]; + UINT8 PcieRpAspm[6]; /** Offset 0x017F - L1 Substates PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). **/ - uint8_t PcieRpL1Substates[6]; + UINT8 PcieRpL1Substates[6]; /** Offset 0x0185 - PCH PCIe LTR PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). **/ - uint8_t PcieRpLtrEnable[6]; + UINT8 PcieRpLtrEnable[6]; /** Offset 0x018B - PCIE LTR Lock PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. **/ - uint8_t PcieRpLtrConfigLock[6]; + UINT8 PcieRpLtrConfigLock[6]; /** Offset 0x0191 - PME_B0_S5 Disable bit PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PmeB0S5Dis; + UINT8 PmeB0S5Dis; /** Offset 0x0192 - PCI Clock Run This member describes whether or not the PCI ClockRun feature of SC should be enabled. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t PciClockRun; + UINT8 PciClockRun; /** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t Timer8254ClkSetting; + UINT8 Timer8254ClkSetting; /** Offset 0x0194 - Chipset SATA Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t EnableSata; + UINT8 EnableSata; /** Offset 0x0195 - SATA Mode Selection Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. 0:AHCI, 1:RAID **/ - uint8_t SataMode; + UINT8 SataMode; /** Offset 0x0196 - Aggressive LPM Support Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t SataSalpSupport; + UINT8 SataSalpSupport; /** Offset 0x0197 - SATA Power Optimization Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SataPwrOptEnable; + UINT8 SataPwrOptEnable; /** Offset 0x0198 - eSATA Speed Limit Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t eSATASpeedLimit; + UINT8 eSATASpeedLimit; /** Offset 0x0199 - SATA Speed Limit SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) **/ - uint8_t SpeedLimit; + UINT8 SpeedLimit; /** Offset 0x019A - SATA Port Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). **/ - uint8_t SataPortsEnable[2]; + UINT8 SataPortsEnable[2]; /** Offset 0x019C - SATA Port DevSlp Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. **/ - uint8_t SataPortsDevSlp[2]; + UINT8 SataPortsDevSlp[2]; /** Offset 0x019E - SATA Port HotPlug Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. **/ - uint8_t SataPortsHotPlug[2]; + UINT8 SataPortsHotPlug[2]; /** Offset 0x01A0 - Mechanical Presence Switch Controls reporting if this port has an Mechanical Presence Switch.\n Note:Requires hardware support. 0:Disable, 1:Enable(Default). **/ - uint8_t SataPortsInterlockSw[2]; + UINT8 SataPortsInterlockSw[2]; /** Offset 0x01A2 - External SATA Ports Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. **/ - uint8_t SataPortsExternal[2]; + UINT8 SataPortsExternal[2]; /** Offset 0x01A4 - Spin Up Device Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. **/ - uint8_t SataPortsSpinUp[2]; + UINT8 SataPortsSpinUp[2]; /** Offset 0x01A6 - SATA Solid State Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard Disk Drive(Default), 1:Solid State Drive. **/ - uint8_t SataPortsSolidStateDrive[2]; + UINT8 SataPortsSolidStateDrive[2]; /** Offset 0x01A8 - DITO Configuration Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. **/ - uint8_t SataPortsEnableDitoConfig[2]; + UINT8 SataPortsEnableDitoConfig[2]; /** Offset 0x01AA - DM Value DM Value. 0:Minimum, 0x0F:Maximum(Default). **/ - uint8_t SataPortsDmVal[2]; + UINT8 SataPortsDmVal[2]; /** Offset 0x01AC - DITO Value DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). **/ - uint16_t SataPortsDitoVal[2]; + UINT16 SataPortsDitoVal[2]; /** Offset 0x01B0 - Subsystem Vendor ID Subsystem Vendor ID. 0x8086(Default). **/ - uint16_t SubSystemVendorId; + UINT16 SubSystemVendorId; /** Offset 0x01B2 - Subsystem ID Subsystem ID. 0x7270(Default). **/ - uint16_t SubSystemId; + UINT16 SubSystemId; /** Offset 0x01B4 **/ - uint8_t UnusedUpdSpace2[10]; + UINT8 UnusedUpdSpace2[10]; /** Offset 0x01BE - CRIDSettings PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. **/ - uint8_t CRIDSettings; + UINT8 CRIDSettings; /** Offset 0x01BF - ResetSelect ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. **/ - uint8_t ResetSelect; + UINT8 ResetSelect; /** Offset 0x01C0 - SD Card Support (D27:F0) Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t SdcardEnabled; + UINT8 SdcardEnabled; /** Offset 0x01C1 - SeMMC Support (D28:F0) Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t eMMCEnabled; + UINT8 eMMCEnabled; /** Offset 0x01C2 - eMMC Max Speed Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. 0:HS400, 1: HS200, 2:DDR50 **/ - uint8_t eMMCHostMaxSpeed; + UINT8 eMMCHostMaxSpeed; /** Offset 0x01C3 - UFS Support (D29:F0) Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t UfsEnabled; + UINT8 UfsEnabled; /** Offset 0x01C4 - SDIO Support (D30:F0) Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t SdioEnabled; + UINT8 SdioEnabled; /** Offset 0x01C5 - GPP Lock Feature Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t GppLock; + UINT8 GppLock; /** Offset 0x01C6 - Serial IRQ Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t SirqEnable; + UINT8 SirqEnable; /** Offset 0x01C7 - Serial IRQ Mode Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. $EN_DIS **/ - uint8_t SirqMode; + UINT8 SirqMode; /** Offset 0x01C8 - Start Frame Pulse Width Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk **/ - uint8_t StartFramePulse; + UINT8 StartFramePulse; /** Offset 0x01C9 - Enable SMBus Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t SmbusEnable; + UINT8 SmbusEnable; /** Offset 0x01CA - SMBus ARP Support Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t ArpEnable; + UINT8 ArpEnable; /** Offset 0x01CB **/ - uint16_t UnusedUpdSpace3; + UINT16 UnusedUpdSpace3; /** Offset 0x01CD - SMBus Table Elements The number of elements in the Reserved SMBus Address Table. 0x0080(Default). **/ - uint16_t NumRsvdSmbusAddresses; + UINT16 NumRsvdSmbusAddresses; /** Offset 0x01CF - Reserved SMBus Address Table Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). **/ - uint8_t RsvdSmbusAddressTable[128]; + UINT8 RsvdSmbusAddressTable[128]; /** Offset 0x024F - XHCI Disable Compliance Mode Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. $EN_DIS **/ - uint8_t DisableComplianceMode; + UINT8 DisableComplianceMode; /** Offset 0x0250 - USB Per-Port Control Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t UsbPerPortCtl; + UINT8 UsbPerPortCtl; /** Offset 0x0251 - xHCI Mode Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) 0:Disable, 1:Enable, 2:Auto **/ - uint8_t Usb30Mode; + UINT8 Usb30Mode; /** Offset 0x0252 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default). **/ - uint8_t PortUsb20Enable[8]; + UINT8 PortUsb20Enable[8]; /** Offset 0x025A - USB20 Over Current Pin Over Current Pin number of USB 2.0 Port. 0x00(Default). **/ - uint8_t PortUs20bOverCurrentPin[8]; + UINT8 PortUs20bOverCurrentPin[8]; /** Offset 0x0262 - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. 0x01(Default). **/ - uint8_t PortUsb30Enable[6]; + UINT8 PortUsb30Enable[6]; /** Offset 0x0268 - USB20 Over Current Pin Over Current Pin number of USB 3.0 Port. 0x01(Default). **/ - uint8_t PortUs30bOverCurrentPin[6]; + UINT8 PortUs30bOverCurrentPin[6]; /** Offset 0x026E - XDCI Support Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. 0:Disable, 1:PCI_Mode, 2:ACPI_mode **/ - uint8_t UsbOtg; + UINT8 UsbOtg; /** Offset 0x026F - Enable XHCI HSIC Support Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t HsicSupportEnable; + UINT8 HsicSupportEnable; /** Offset 0x0270 - Enable XHCI SSIC Support Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. 0x00(Default). **/ - uint8_t SsicPortEnable[2]; + UINT8 SsicPortEnable[2]; /** Offset 0x0272 - SSIC Dlane PowerGating Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint16_t DlanePwrGating; + UINT16 DlanePwrGating; /** Offset 0x0274 - VT-d Enable/Disable VT-d. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t VtdEnable; + UINT8 VtdEnable; /** Offset 0x0275 - HDAudio Delay Timer The delay timer after Azalia reset. 0x012C(Default). **/ - uint16_t ResetWaitTimer; + UINT16 ResetWaitTimer; /** Offset 0x0277 - SMI Lock bit Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t LockDownGlobalSmi; + UINT8 LockDownGlobalSmi; /** Offset 0x0278 - RTC Lock Bits Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t RtcLock; + UINT8 RtcLock; /** Offset 0x0279 - XHCI SSIC RATE Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. **/ - uint8_t SsicRate[2]; + UINT8 SsicRate[2]; /** Offset 0x027B - SATA Test Mode Selection Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t SataTestMode; + UINT8 SataTestMode; /** Offset 0x027C - SMBus Dynamic Power Gating Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint16_t DynamicPowerGating; + UINT16 DynamicPowerGating; /** Offset 0x027E - Max Snoop Latency Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). **/ - uint16_t PcieRpLtrMaxSnoopLatency[6]; + UINT16 PcieRpLtrMaxSnoopLatency[6]; /** Offset 0x028A - Snoop Latency Override Snoop Latency Override for PCH PCIE. \n @@ -1285,23 +1287,23 @@ struct FSP_S_CONFIG { Manual:Manually enter override values.\n Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ - uint8_t PcieRpSnoopLatencyOverrideMode[6]; + UINT8 PcieRpSnoopLatencyOverrideMode[6]; /** Offset 0x0290 - Snoop Latency Value LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). **/ - uint16_t PcieRpSnoopLatencyOverrideValue[6]; + UINT16 PcieRpSnoopLatencyOverrideValue[6]; /** Offset 0x029C - Snoop Latency Multiplier LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns. **/ - uint8_t PcieRpSnoopLatencyOverrideMultiplier[6]; + UINT8 PcieRpSnoopLatencyOverrideMultiplier[6]; /** Offset 0x02A2 - Max Non-Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). **/ - uint16_t PcieRpLtrMaxNonSnoopLatency[6]; + UINT16 PcieRpLtrMaxNonSnoopLatency[6]; /** Offset 0x02AE - Non Snoop Latency Override Non Snoop Latency Override for PCH PCIE. \n @@ -1309,229 +1311,231 @@ struct FSP_S_CONFIG { Manual:Manually enter override values.\n Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). **/ - uint8_t PcieRpNonSnoopLatencyOverrideMode[6]; + UINT8 PcieRpNonSnoopLatencyOverrideMode[6]; /** Offset 0x02B4 - Non Snoop Latency Value LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). **/ - uint16_t PcieRpNonSnoopLatencyOverrideValue[6]; + UINT16 PcieRpNonSnoopLatencyOverrideValue[6]; /** Offset 0x02C0 - Non Snoop Latency Multiplier LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, 4:1048576ns, 5:33554432ns. **/ - uint8_t PcieRpNonSnoopLatencyOverrideMultiplier[6]; + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6]; /** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale Specifies scale used for slot power limit value. 0x00(Default). **/ - uint8_t PcieRpSlotPowerLimitScale[6]; + UINT8 PcieRpSlotPowerLimitScale[6]; /** Offset 0x02CC - PCIE Root Port Slot Power Limit Value Specifies upper limit on power supplie by slot. 0x00(Default). **/ - uint8_t PcieRpSlotPowerLimitValue[6]; + UINT8 PcieRpSlotPowerLimitValue[6]; /** Offset 0x02D2 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize(Default), 1: Skip $EN_DIS **/ - uint8_t SkipMpInit; + UINT8 SkipMpInit; /** Offset 0x02D3 - DCI Auto Detect Enable/disable DCI AUTO mode. Enabled(Default). $EN_DIS **/ - uint8_t DciAutoDetect; + UINT8 DciAutoDetect; /** Offset 0x02D4 - Halt and Lock TCO Timer Halt and Lock the TCO Timer (Watchdog). 0:No, 1:Yes (default) **/ - uint8_t TcoTimerHaltLock; + UINT8 TcoTimerHaltLock; /** Offset 0x02D5 - Power Button Override Period specifies how long will PMC wait before initiating a global reset. 000b-4s(default), 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s **/ - uint8_t PwrBtnOverridePeriod; + UINT8 PwrBtnOverridePeriod; /** Offset 0x02D6 - Power Button Native Mode Disable Disable power button native mode, when 1, this will result in the PMC logic constantly seeing the power button as de-asserted. 0 (default)) $EN_DIS **/ - uint8_t DisableNativePowerButton; + UINT8 DisableNativePowerButton; /** Offset 0x02D7 - Power Button Debounce Mode Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default) $EN_DIS **/ - uint8_t PowerButterDebounceMode; + UINT8 PowerButterDebounceMode; /** Offset 0x02D8 - SDIO_TX_CMD_DLL_CNTL SDIO_TX_CMD_DLL_CNTL. 0x505(Default). **/ - uint32_t SdioTxCmdCntl; + UINT32 SdioTxCmdCntl; /** Offset 0x02DC - SDIO_TX_DATA_DLL_CNTL1 SDIO_TX_DATA_DLL_CNTL1. 0xE(Default). **/ - uint32_t SdioTxDataCntl1; + UINT32 SdioTxDataCntl1; /** Offset 0x02E0 - SDIO_TX_DATA_DLL_CNTL2 SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default). **/ - uint32_t SdioTxDataCntl2; + UINT32 SdioTxDataCntl2; /** Offset 0x02E4 - SDIO_RX_CMD_DATA_DLL_CNTL1 SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default). **/ - uint32_t SdioRxCmdDataCntl1; + UINT32 SdioRxCmdDataCntl1; /** Offset 0x02E8 - SDIO_RX_CMD_DATA_DLL_CNTL2 SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). **/ - uint32_t SdioRxCmdDataCntl2; + UINT32 SdioRxCmdDataCntl2; /** Offset 0x02EC - SDCARD_TX_CMD_DLL_CNTL SDCARD_TX_CMD_DLL_CNTL. 0x505(Default). **/ - uint32_t SdcardTxCmdCntl; + UINT32 SdcardTxCmdCntl; /** Offset 0x02F0 - SDCARD_TX_DATA_DLL_CNTL1 SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default). **/ - uint32_t SdcardTxDataCntl1; + UINT32 SdcardTxDataCntl1; /** Offset 0x02F4 - SDCARD_TX_DATA_DLL_CNTL2 SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default). **/ - uint32_t SdcardTxDataCntl2; + UINT32 SdcardTxDataCntl2; /** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL1 SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default). **/ - uint32_t SdcardRxCmdDataCntl1; + UINT32 SdcardRxCmdDataCntl1; /** Offset 0x02FC - SDCARD_RX_STROBE_DLL_CNTL SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default). **/ - uint32_t SdcardRxStrobeCntl; + UINT32 SdcardRxStrobeCntl; /** Offset 0x0300 - SDCARD_RX_CMD_DATA_DLL_CNTL2 SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). **/ - uint32_t SdcardRxCmdDataCntl2; + UINT32 SdcardRxCmdDataCntl2; /** Offset 0x0304 - EMMC_TX_CMD_DLL_CNTL EMMC_TX_CMD_DLL_CNTL. 0x505(Default). **/ - uint32_t EmmcTxCmdCntl; + UINT32 EmmcTxCmdCntl; /** Offset 0x0308 - EMMC_TX_DATA_DLL_CNTL1 EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default). **/ - uint32_t EmmcTxDataCntl1; + UINT32 EmmcTxDataCntl1; /** Offset 0x030C - EMMC_TX_DATA_DLL_CNTL2 EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default). **/ - uint32_t EmmcTxDataCntl2; + UINT32 EmmcTxDataCntl2; /** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL1 EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default). **/ - uint32_t EmmcRxCmdDataCntl1; + UINT32 EmmcRxCmdDataCntl1; /** Offset 0x0314 - EMMC_RX_STROBE_DLL_CNTL EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default). **/ - uint32_t EmmcRxStrobeCntl; + UINT32 EmmcRxStrobeCntl; /** Offset 0x0318 - EMMC_RX_CMD_DATA_DLL_CNTL2 EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default). **/ - uint32_t EmmcRxCmdDataCntl2; + UINT32 EmmcRxCmdDataCntl2; /** Offset 0x031C - EMMC_MASTER_DLL_CNTL EMMC_MASTER_DLL_CNTL. 0x001(Default). **/ - uint32_t EmmcMasterSwCntl; + UINT32 EmmcMasterSwCntl; /** Offset 0x0320 - PCIe Selectable De-emphasis When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). **/ - uint8_t PcieRpSelectableDeemphasis[6]; + UINT8 PcieRpSelectableDeemphasis[6]; /** Offset 0x0326 **/ - uint8_t UnusedUpdSpace4; + UINT8 UnusedUpdSpace4; /** Offset 0x0327 - Monitor Mwait Enable Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux based OS, this should be Disabled. 0:Disable, 1:Enable(Default). $EN_DIS **/ - uint8_t MonitorMwaitEnable; + UINT8 MonitorMwaitEnable; /** Offset 0x0328 **/ - uint8_t ReservedFspsUpd[8]; -} __attribute__((packed)); + UINT8 ReservedFspsUpd[8]; +} FSP_S_CONFIG; /** Fsp S Test Configuration **/ -struct FSP_S_TEST_CONFIG { +typedef struct { /** Offset 0x0330 **/ - uint32_t Signature; + UINT32 Signature; /** Offset 0x0334 **/ - uint8_t ReservedFspsTestUpd[12]; -} __attribute__((packed)); + UINT8 ReservedFspsTestUpd[12]; +} FSP_S_TEST_CONFIG; /** Fsp S Restricted Configuration **/ -struct FSP_S_RESTRICTED_CONFIG { +typedef struct { /** Offset 0x0340 **/ - uint32_t Signature; + UINT32 Signature; /** Offset 0x0344 **/ - uint8_t ReservedFspsRestrictedUpd[12]; -} __attribute__((packed)); + UINT8 ReservedFspsRestrictedUpd[12]; +} FSP_S_RESTRICTED_CONFIG; /** Fsp S UPD Configuration **/ -struct FSPS_UPD { +typedef struct { /** Offset 0x0000 **/ - struct FSP_UPD_HEADER FspUpdHeader; + FSP_UPD_HEADER FspUpdHeader; /** Offset 0x0020 **/ - struct FSP_S_CONFIG FspsConfig; + FSP_S_CONFIG FspsConfig; /** Offset 0x0330 **/ - struct FSP_S_TEST_CONFIG FspsTestConfig; + FSP_S_TEST_CONFIG FspsTestConfig; /** Offset 0x0340 **/ - struct FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; + FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; /** Offset 0x0350 **/ - uint16_t UpdTerminator; -} __attribute__((packed)); + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack(pop) #endif diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 06d2b58..5561363 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -18,6 +18,7 @@ #include <stddef.h> #include <stdint.h> +#include <soc/fsp/FspmUpd.h> /* * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. @@ -77,13 +78,11 @@ struct lpddr4_swizzle_cfg { struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS]; }; -struct FSP_M_CONFIG; - /* * Initialize default LPDDR4 settings with provided speed. No logical channels * are enabled. Subsequent calls to logical channel enabling are required. */ -void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed); +void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed); /* * Enable logical channel providing the full lpddr4_swizzle_config to @@ -91,7 +90,7 @@ void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed); * memory width per logical channel -- i.e. 2 physical channels are configured * to the memory reference code. */ -void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan, +void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan, int rank_density, int dual_rank, const struct lpddr4_swizzle_cfg *scfg); @@ -115,7 +114,7 @@ struct lpddr4_cfg { * Initialize LPDDR4 settings by the provided lpddr4_cfg information and sku id. * The sku id is an index into the sku array within the lpddr4_cfg struct. */ -void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, +void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg, const struct lpddr4_cfg *lpcfg, size_t sku_id); void save_lpddr4_dimm_info(const struct lpddr4_cfg *lpcfg, size_t mem_sku); diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index 5b76f65..6ae46b6 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -21,7 +21,7 @@ #include <arch/cpu.h> #include <fsp/api.h> -void mainboard_memory_init_params(struct FSPM_UPD *mupd); +void mainboard_memory_init_params(FSPM_UPD *mupd); void mainboard_save_dimm_info(void); #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index d0e7683..7a19e69 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -22,7 +22,7 @@ #include <soc/fsp/FspmUpd.h> #include <string.h> -static void set_lpddr4_defaults(struct FSP_M_CONFIG *cfg) +static void set_lpddr4_defaults(FSP_M_CONFIG *cfg) { /* Enable memory down BGA since it's the only LPDDR4 packaging. */ cfg->Package = 1; @@ -80,7 +80,7 @@ static void set_lpddr4_defaults(struct FSP_M_CONFIG *cfg) cfg->Ch3_OdtConfig = 0; } -void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed) +void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed) { uint8_t profile; @@ -107,7 +107,7 @@ void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed) set_lpddr4_defaults(cfg); } -static void enable_logical_chan0(struct FSP_M_CONFIG *cfg, +static void enable_logical_chan0(FSP_M_CONFIG *cfg, int rank_density, int dual_rank, const struct lpddr4_swizzle_cfg *scfg) { @@ -152,7 +152,7 @@ static void enable_logical_chan0(struct FSP_M_CONFIG *cfg, memcpy(&cfg->Ch1_Bit_swizzling[24], &chan->dqs[LP4_DQS3], sz); } -static void enable_logical_chan1(struct FSP_M_CONFIG *cfg, +static void enable_logical_chan1(FSP_M_CONFIG *cfg, int rank_density, int dual_rank, const struct lpddr4_swizzle_cfg *scfg) { @@ -197,7 +197,7 @@ static void enable_logical_chan1(struct FSP_M_CONFIG *cfg, memcpy(&cfg->Ch3_Bit_swizzling[24], &chan->dqs[LP4_DQS3], sz); } -void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan, +void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan, int rank_density, int dual_rank, const struct lpddr4_swizzle_cfg *scfg) { @@ -220,7 +220,7 @@ void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan, } } -void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, +void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg, const struct lpddr4_cfg *lpcfg, size_t sku_id) { const struct lpddr4_sku *sku; @@ -262,11 +262,11 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku) { int channel, dimm, dimm_max, index; size_t hob_size; - const struct DIMM_INFO *src_dimm; + const DIMM_INFO *src_dimm; struct dimm_info *dest_dimm; struct memory_info *mem_info; - const struct CHANNEL_INFO *channel_info; - const struct FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + const CHANNEL_INFO *channel_info; + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; if (mem_sku >= lp4cfg->num_skus) { printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c index 4bfdee4..3e62d81 100644 --- a/src/soc/intel/apollolake/reset.c +++ b/src/soc/intel/apollolake/reset.c @@ -59,7 +59,7 @@ void reset_prepare(void) printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw)); } -void chipset_handle_reset(enum fsp_status status) +void chipset_handle_reset(uint32_t status) { switch(status) { case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 6b58aa5..ebd6287 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -133,7 +133,7 @@ asmlinkage void car_stage_entry(void) run_postcar_phase(&pcf); } -static void fill_console_params(struct FSPM_UPD *mupd) +static void fill_console_params(FSPM_UPD *mupd) { if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; @@ -148,7 +148,7 @@ static void fill_console_params(struct FSPM_UPD *mupd) } } -void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) { fill_console_params(mupd); mainboard_memory_init_params(mupd); @@ -167,7 +167,7 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) } __attribute__ ((weak)) -void mainboard_memory_init_params(struct FSPM_UPD *mupd) +void mainboard_memory_init_params(FSPM_UPD *mupd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); }

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Patch set updated for coreboot: commonlib: update fsp_relocate to make it compatible with UEFI 2.6
by Brandon Breitenstein 31 Aug '16

31 Aug '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16309 -gerrit commit e9dcdc56cfa6cc6e5136e10d1e5a4018c9b56a8e Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Tue Aug 23 14:55:13 2016 -0700 commonlib: update fsp_relocate to make it compatible with UEFI 2.6 UEFI 2.6 spec casts the return of FFS_FILE2_SIZE to a UINT32 which cannot be read using read_le32(&returnval). Add in a cast in order to safeguard for any non x86 architecture that may use this relocate. The proper change will be to get the UEFI header files changed to not cast this return value. Change-Id: Ie1b50d99576ac42a0413204bbd599bab9f01828e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/commonlib/fsp_relocate.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 7f1e49a..57c0ac9 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -258,8 +258,15 @@ static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh) { size_t size; - if (IS_FFS_FILE2(ffsfh)) - size = read_le32(&FFS_FILE2_SIZE(ffsfh)); + if (IS_FFS_FILE2(ffsfh)) { + /* + * this cast is needed with UEFI 2.6 headers in order + * to read the UINT32 value that FFS_FILE2_SIZE converts + * the return into + */ + uint32_t file2_size = FFS_FILE2_SIZE(ffsfh); + size = read_le32(&file2_size); + } else { size = read_le8(&ffsfh->Size[0]) << 0; size |= read_le8(&ffsfh->Size[1]) << 8;

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coreboot-gerrit August 2016