coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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1551 discussions

New patch to review for coreboot: soc/intel/apollolake: Use consistent convention for community names
by Furquan Shaikh 30 Aug '16

30 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16353 -gerrit commit 6870d01d673969d1cc153c1e7a40b15bcb084880 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Aug 29 22:51:41 2016 -0700 soc/intel/apollolake: Use consistent convention for community names Instead of using a mix of _N and _NORTH, _NW and _NORTHWEST for gpio community names, follow one single convention. This allows for re-using macros easily. Change-Id: Icd9cf9ef70d03576d864688cf5d6946124c259c3 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/acpi/gpio.asl | 8 ++++---- src/soc/intel/apollolake/gpio.c | 24 ++++++++++++------------ src/soc/intel/apollolake/include/soc/gpio_defs.h | 10 +++++----- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 030d3eb..03b8edd 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -38,7 +38,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_NORTH, 16, Local0) + ShiftLeft (GPIO_N, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -69,7 +69,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_NORTHWEST, 16, Local0) + ShiftLeft (GPIO_NW, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -100,7 +100,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_WEST, 16, Local0) + ShiftLeft (GPIO_W, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } @@ -131,7 +131,7 @@ scope (\_SB) { Method (_CRS, 0x0, NotSerialized) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - ShiftLeft (GPIO_SOUTHWEST, 16, Local0) + ShiftLeft (GPIO_SW, 16, Local0) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Return (^RBUF) } diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index 1073e16..e56f147 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -31,25 +31,25 @@ static const struct pad_community { const char *grp_name; } gpio_communities[] = { { - .port = GPIO_SOUTHWEST, + .port = GPIO_SW, .first_pad = SW_OFFSET, .num_gpi_regs = NUM_SW_GPI_REGS, .gpi_offset = 0, .grp_name = "GPIO_GPE_SW", }, { - .port = GPIO_WEST, + .port = GPIO_W, .first_pad = W_OFFSET, .num_gpi_regs = NUM_W_GPI_REGS, .gpi_offset = NUM_SW_GPI_REGS, .grp_name = "GPIO_GPE_W", }, { - .port = GPIO_NORTHWEST, + .port = GPIO_NW, .first_pad = NW_OFFSET, .num_gpi_regs = NUM_NW_GPI_REGS, .gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS, .grp_name = "GPIO_GPE_NW", }, { - .port = GPIO_NORTH, + .port = GPIO_N, .first_pad = N_OFFSET, .num_gpi_regs = NUM_N_GPI_REGS, .gpi_offset = NUM_NW_GPI_REGS+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS, @@ -229,13 +229,13 @@ const char *gpio_acpi_path(gpio_t gpio_num) const struct pad_community *comm = gpio_get_community(gpio_num); switch (comm->port) { - case GPIO_NORTH: + case GPIO_N: return "\\_SB.GPO0"; - case GPIO_NORTHWEST: + case GPIO_NW: return "\\_SB.GPO1"; - case GPIO_WEST: + case GPIO_W: return "\\_SB.GPO2"; - case GPIO_SOUTHWEST: + case GPIO_SW: return "\\_SB.GPO3"; } @@ -247,13 +247,13 @@ uint16_t gpio_acpi_pin(gpio_t gpio_num) const struct pad_community *comm = gpio_get_community(gpio_num); switch (comm->port) { - case GPIO_NORTH: + case GPIO_N: return PAD_N(gpio_num); - case GPIO_NORTHWEST: + case GPIO_NW: return PAD_NW(gpio_num); - case GPIO_WEST: + case GPIO_W: return PAD_W(gpio_num); - case GPIO_SOUTHWEST: + case GPIO_SW: return PAD_SW(gpio_num); } diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 88fa475..d4e52be 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -130,11 +130,11 @@ #define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8)) /* IOSF port numbers for GPIO comminuties*/ -#define GPIO_SOUTHWEST 0xc0 -#define GPIO_SOUTH 0xc2 -#define GPIO_NORTHWEST 0xc4 -#define GPIO_NORTH 0xc5 -#define GPIO_WEST 0xc7 +#define GPIO_SW 0xc0 +#define GPIO_S 0xc2 +#define GPIO_NW 0xc4 +#define GPIO_N 0xc5 +#define GPIO_W 0xc7 #define GPI_SMI_STS_0 0x140 #define GPI_SMI_EN_0 0x150

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Patch set updated for coreboot: fsp_broadwell_de: Refactor code for SPI debug messages
by Werner Zeh 30 Aug '16

30 Aug '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16347 -gerrit commit 5af102e620a276edd817d3211e5f9a9d45e25589 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Aug 29 08:00:50 2016 +0200 fsp_broadwell_de: Refactor code for SPI debug messages Currently boards based on fsp_broadwell_de fail to compile if the config switch CONFIG_DEBUG_SPI_FLASH is selected. The error is caused by the usage of const for the address pointer in the functions writeb_, writew_ and writel_. The reason why it stayed hidden for so long is the fact that the switch is used with the preprocessor and nobody really selects it until there is a bug one want to find in this area. This patch fixes the parameter type definition which solves the error. In addition the config switch is not used on preprocessor level anymore but instead on compiler level. This ensures that at least the code syntax is checked on build time even if the config option is not selected. Also prefix the messages with "SPI:" to make them more meaningful in a full log. Change-Id: I3514b0d4c08bf5a4740f2632641e09af1b3aaf3a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_broadwell_de/spi.c | 56 ++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index f98ab97..57f7951 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -1,6 +1,7 @@ /* * Copyright (c) 2013 Google Inc. * Copyright (C) 2015-2016 Intel Corp. + * Copyright (C) 2016 Siemens AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -158,64 +159,63 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) - static u8 readb_(const void *addr) { u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + } return v; } static u16 readw_(const void *addr) { u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + } return v; } static u32 readl_(const void *addr) { u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + } return v; } -static void writeb_(u8 b, const void *addr) +static void writeb_(u8 b, void *addr) { write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); + } } -static void writew_(u16 b, const void *addr) +static void writew_(u16 b, void *addr) { write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); + } } -static void writel_(u32 b, const void *addr) +static void writel_(u32 b, void *addr) { write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { + printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); + } } -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - static void write_reg(const void *value, void *dest, uint32_t size) { const uint8_t *bvalue = value;

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Patch merged into coreboot/master: mainboard/google/reef: set SLP_S3_L assertion width to 28ms
by gerrit＠coreboot.org 30 Aug '16

30 Aug '16

the following patch was just integrated into master: commit c3d74273a748c0cfc78b258369451c35c122372b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 25 15:44:39 2016 -0500 mainboard/google/reef: set SLP_S3_L assertion width to 28ms The reef board needs at least ~28ms for its S0 rails to discharge when S3 is entered. Because of the granularity in the chipset the effective SLP_S3_L assertion width is 50ms. BUG=chrome-os-partner:56581 Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16327 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16327 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: add option for SLP_S3_L assertion width
by gerrit＠coreboot.org 30 Aug '16

30 Aug '16

the following patch was just integrated into master: commit 41a3fa66a0d8a6b134ceb17b8f34520cad7643a4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 25 15:42:04 2016 -0500 soc/intel/apollolake: add option for SLP_S3_L assertion width In order to provide time for the S0 rails to discharge one needs to be able to set the SLP_S3_L assertion width. The hardware default is 60 microcseconds which is not slow enough on most boards. Therefore provide a devicetree option for the mainboard to set accordingly for its needs. An unset value in devicetree results in a conservative 2 second SLP_S3_L duration. BUG=chrome-os-partner:56581 Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16326 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/16326 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Gather microcode revision
by John Zhao 30 Aug '16

30 Aug '16

John Zhao (john.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16311 -gerrit commit c9b18a8f8582c06eac489a5846df641b5047de7e Author: John Zhao <john.zhao(a)intel.com> Date: Tue Aug 23 16:38:05 2016 -0700 soc/intel/apollolake: Gather microcode revision Expose get_microcode_info in cpu initialization. Microcode revision is retrieved and stored into log file at verstage. BUG=chrome-os-partner:56544 BRANCH=None TEST=Built coreboot image and validate log file Change-Id: I1e792e70f1318df64b4b85a319700013f3757952 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- src/soc/intel/apollolake/cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 4f74def..86fe3e1 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -20,6 +20,7 @@ #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/mp.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <device/device.h> @@ -42,7 +43,6 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; - /* * MP and SMM loading initialization. */ @@ -88,6 +88,12 @@ static int get_cpu_count(void) return num_virt_cores; } +static void get_microcode_info(const void **microcode, int *parallel) +{ + *microcode = intel_microcode_find(); + *parallel = 1; +} + static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { @@ -135,6 +141,7 @@ static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, + .get_microcode_info = get_microcode_info, .pre_mp_smm_init = southbridge_smm_clear_state, .relocation_handler = relocation_handler, .post_mp_init = southbridge_smm_enable_smi,

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Patch set updated for coreboot: soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3
by Brandon Breitenstein 30 Aug '16

30 Aug '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16352 -gerrit commit 4f8847987ee9adda46476f5adec3462ae2eef24c Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Aug 29 16:24:24 2016 -0700 soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3 Updated FSP Header files to provide upd for periodic training disable. This is for the SIC 1.1.3/150_11 FSP release. There is a related patch submitted by Andrey to implement the functionality of this UPD. BUG=chrome-os-partner:54100 BRANCH=none TEST=built coreboot image with new headers Change-Id: I2ba11aa3d2d664c1d34e39c4c8144fb1c4f2149a Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 35 +++++++++++++--------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index bb53497..994357c 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -36,6 +36,7 @@ are permitted provided that the following conditions are met: #include "FspUpd.h" #include <fsp/upd.h> + #define MAX_CHANNELS_NUM 4 #define MAX_DIMMS_NUM 1 @@ -595,28 +596,28 @@ struct FSP_M_CONFIG { **/ uint8_t RecoverDump; -/** Offset 0x013A - Memory Region 0 Buffer Size +/** Offset 0x013A - Memory Region 0 Buffer WrapAround + Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + uint8_t Msc0Wrap; + +/** Offset 0x013B - Memory Region 1 Buffer WrapAround + Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + uint8_t Msc1Wrap; + +/** Offset 0x013C - Memory Region 0 Buffer Size Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ uint32_t Msc0Size; -/** Offset 0x013E - Memory Region 0 Buffer WrapAround - Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - uint8_t Msc0Wrap; - -/** Offset 0x013F - Memory Region 1 Buffer Size +/** Offset 0x0140 - Memory Region 1 Buffer Size Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ uint32_t Msc1Size; -/** Offset 0x0143 - Memory Region 1 Buffer WrapAround - Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - uint8_t Msc1Wrap; - /** Offset 0x0144 - PTI Mode PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. **/ @@ -648,9 +649,15 @@ struct FSP_M_CONFIG { **/ uint8_t SwTraceEn; -/** Offset 0x014A +/** Offset 0x014A - Periodic Retraining Disable + Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t PeriodicRetrainingDisable; + +/** Offset 0x014B **/ - uint8_t ReservedFspmUpd[6]; + uint8_t ReservedFspmUpd[5]; } __attribute__((packed)); /** Fsp M Test Configuration

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New patch to review for coreboot: soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3
by Brandon Breitenstein 30 Aug '16

30 Aug '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16352 -gerrit commit 358b44de65fb9a5415a860a965477d20df9e3f57 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Aug 29 16:24:24 2016 -0700 soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3 Updated FSP Header files to provide upd for periodic training disable. This is for the SIC 1.1.3/150_11 FSP release. There is a related patch submitted by Andrey to implement the functionality of this UPD. BUG=chrome-os-partner:54100 BRANCH=none TEST=built coreboot image with new headers Change-Id: I2ba11aa3d2d664c1d34e39c4c8144fb1c4f2149a Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 35 +++++++++++++--------- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 1 + 2 files changed, 22 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index bb53497..994357c 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -36,6 +36,7 @@ are permitted provided that the following conditions are met: #include "FspUpd.h" #include <fsp/upd.h> + #define MAX_CHANNELS_NUM 4 #define MAX_DIMMS_NUM 1 @@ -595,28 +596,28 @@ struct FSP_M_CONFIG { **/ uint8_t RecoverDump; -/** Offset 0x013A - Memory Region 0 Buffer Size +/** Offset 0x013A - Memory Region 0 Buffer WrapAround + Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + uint8_t Msc0Wrap; + +/** Offset 0x013B - Memory Region 1 Buffer WrapAround + Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + uint8_t Msc1Wrap; + +/** Offset 0x013C - Memory Region 0 Buffer Size Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ uint32_t Msc0Size; -/** Offset 0x013E - Memory Region 0 Buffer WrapAround - Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - uint8_t Msc0Wrap; - -/** Offset 0x013F - Memory Region 1 Buffer Size +/** Offset 0x0140 - Memory Region 1 Buffer Size Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ uint32_t Msc1Size; -/** Offset 0x0143 - Memory Region 1 Buffer WrapAround - Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - uint8_t Msc1Wrap; - /** Offset 0x0144 - PTI Mode PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. **/ @@ -648,9 +649,15 @@ struct FSP_M_CONFIG { **/ uint8_t SwTraceEn; -/** Offset 0x014A +/** Offset 0x014A - Periodic Retraining Disable + Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t PeriodicRetrainingDisable; + +/** Offset 0x014B **/ - uint8_t ReservedFspmUpd[6]; + uint8_t ReservedFspmUpd[5]; } __attribute__((packed)); /** Fsp M Test Configuration diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index 26f70a7..cb13f64 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -36,6 +36,7 @@ are permitted provided that the following conditions are met: #include "FspUpd.h" #include <fsp/upd.h> + /** Fsp S Configuration **/ struct FSP_S_CONFIG {

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New patch to review for coreboot: soc/intel/apollolake: Add PM methods to power gate PCIe
by Vaibhav Shankar 30 Aug '16

30 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16351 -gerrit commit 62204b4c2be666290806ecf7ea77523e014fe931 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Tue Aug 23 17:56:17 2016 -0700 soc/intel/apollolake: Add PM methods to power gate PCIe Implement _ON/_OFF methods to power gate PCIe during S0ix entry. BUG=chrome-os-partner:55877 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/pcie.asl | 153 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 + 2 files changed, 156 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl new file mode 100644 index 0000000..3a8bc8c --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pcie.asl @@ -0,0 +1,153 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "gpiolib.asl" + +Device (RP01) +{ + Name (_ADR, 0x00140000) + Name (_DDN, "PCIe-B 0") + Name (PWRG,1) /* power status */ + Name (PDST, 0) /* present Detect status */ + + + Method(_S0W, 0) + { + /* This method returns the lowest D-state supported by + * PCIe root port during S0 state + */ + + /* PMEs can be generated from D3Cold */ + Return(4) + } /* End _S0W */ + + /* Dynamic Opregion needed to access registers + * when the controller is in D3 cold + */ + OperationRegion(PX02, PCI_Config, 0x0, 0x380) + Field(PX02,AnyAcc, NoLock, Preserve) + { + Offset(0x5A), /* SLSTS- SLot status Register */ + , 6, + PDS, 1, /* 6, Presence detect Change */ + Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ + Offset(0xF4), /* BLKPLLEN */ + , 10, + BPLL, 1, + Offset(0x338), + , 26, + BDQA, 1 /* BLKDQDA */ + } + + PowerResource(PXP, 0, 0) + { + /* Define the PowerResource for PCIe slot */ + /*Method: _STA(), _ON(), _OFF() */ + + Method(_STA, 0, Serialized) + { + Store(PDS, PDST) /* store PDS */ + If(LEqual(PDS,1)) + { + If(LEqual(PWRG,1)) + { + Return (1) + } + Else + { + Return (0) + } + } + Else + { + Return (0) + } + } + + Method(_ON,0,Serialized) /* Turn on core power to PCIe Slot */ + { + If(LEqual(PDST,1)) + { /* enter this condition if device is connected */ + /* + * De-assert PERST + /* loccal2 - PERST GPIO address + * local1 - to toggle Tx pin of Dw0 + */ + Store(\_SB.PRAD, Local2) + Store(\_SB.GPC0(Local2), Local1) + And(Local1, 0xFFFFFFFE , Local1) + \_SB.SPC0 (Local2, Local1) + + Store(0, BDQA) /* Set BLKDQDA to 0 */ + Store(0, BPLL) /* Set BLKPLLEN to 0 */ + /* Set L23_Rdy to Detect Transition (L23R2DT) */ + Store(1, L23R) + Sleep(16) + Store(0, Local0) + /* Wait up to 16ms for transition to Detect */ + While(L23R) { + If(Lgreater(Local0, 4)) + { + Break + } + Sleep(16) + Increment(Local0) + } + Store(1, PWRG) /* Set 1 PWRG to indicate the device is on */ + } /* End PDS condition check */ + } + + Method(_OFF,0,Serialized) /* Turn off core power to PCIe Slot */ + { + + /* Set L23_Rdy Entry Request (L23ER) */ + If(LEqual(PDST,1)) + { /* enter this condition if device is connected */ + Store(1, L23E) + Sleep(16) /* Delay for Link to transition */ + Store(0, Local0) + While(L23E) { + If(Lgreater(Local0, 4)) + { + Break + } + Sleep(16) + Increment(Local0) + } + Store(1, BDQA) /* Set BLKDQDA to 1 */ + Store(1, BPLL) /* Set BLKPLLEN to 1 */ + + /* + * Assert PERST + /* loccal2 - PERST GPIO address + * local1 - to toggle Tx pin of Dw0 + */ + Store(\_SB.PRAD, Local2) + Store(\_SB.GPC0(Local2), Local1) + Or(Local1, 0x1 , Local1) + \_SB.SPC0 (Local2, Local1) + + /* Set 0 PWRG to indicate the device is off */ + Store(0, PWRG) + } /* End PDS condition check */ + } /* End of Method_OFF */ + } /* End PXP */ + + Name(_PR0, Package(){PXP}) + Name(_PR3, Package(){PXP}) +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 391a531..d7ced0f 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,6 +17,9 @@ #include <soc/gpe.h> +/* PCIE device */ +#include "pcie.asl" + /* LPSS device */ #include "lpss.asl"

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New patch to review for coreboot: mainboard/intel/amenia: Configure PERST_0 for PCIe
by Vaibhav Shankar 30 Aug '16

30 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16350 -gerrit commit 8c87a95d2d05769bfcda3bbce1c480c3e412430f Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Fri Aug 26 19:10:21 2016 -0700 mainboard/intel/amenia: Configure PERST_0 for PCIe Added a variable to store the address of GPIO_122. Program GPIO_122 for PERST_0 assertion during S0ix. BUG=chrome-os-partner:55877 Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/mainboard/intel/amenia/acpi/mainboard.asl | 11 +++++++++++ src/mainboard/intel/amenia/gpio.h | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl index 80f8f26..293580b 100644 --- a/src/mainboard/intel/amenia/acpi/mainboard.asl +++ b/src/mainboard/intel/amenia/acpi/mainboard.asl @@ -17,8 +17,19 @@ #include <on_board.h> #include "../ec.h" +/* GPIO for PERST */ +#define PERST_0 GPIO_122 + +#define GPIO_SW GPIO_SOUTHWEST +#define GPIO_NW GPIO_NORTHWEST +#define GPIO_N GPIO_NORTH +#define GPIO_W GPIO_WEST + Scope (\_SB) { + /* PRAD - Pass the address of PERST_0 to pcie.asl */ + Name (PRAD, PAD_IOSF_MMIO(NW, PERST_0)) + Device (LID0) { Name (_HID, EisaId ("PNP0C0D")) diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h index 4a4d08f..3eb4103 100644 --- a/src/mainboard/intel/amenia/gpio.h +++ b/src/mainboard/intel/amenia/gpio.h @@ -223,7 +223,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPIO_119, DN_20K), /* GP_SSP_2_FS0 */ PAD_NC(GPIO_120, DN_20K), /* GP_SSP_2_FS1 */ PAD_NC(GPIO_121, DN_20K), /* GP_SSP_2_FS2 */ - PAD_NC(GPIO_122, DN_20K), /* GP_SSP_2_RXD */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* WIFI PERST_0 */ PAD_NC(GPIO_123, DN_20K), /* GP_SSP_2_TXD */ /** end of North West Community */ /** North Community */

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New patch to review for coreboot: soc/intel/apollolake: Configure DW0 and DW1 GPIO registers
by Vaibhav Shankar 30 Aug '16

30 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16349 -gerrit commit 5dcc43e37e4d14df55592987e4cbb2c59a62f553 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Aug 29 14:03:38 2016 -0700 soc/intel/apollolake: Configure DW0 and DW1 GPIO registers Implement a macro to calculate DW0 register address for GPIOs. Implement GPIO methods to configure DW0 and DW1 registers. BUG=chrome-os-partner:55877 Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/gpiolib.asl | 71 ++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 5 ++ 2 files changed, 76 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl new file mode 100644 index 0000000..a021e1f --- /dev/null +++ b/src/soc/intel/apollolake/acpi/gpiolib.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_SB) +{ + + /* Get Pad Configuration DW0 register value */ + Method(GPC0, 0x1, Serialized) + { + /* Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) */ + Store(Arg0, Local0) + OperationRegion(PDW0, SystemMemory, Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Return(TEMP) + } + + /* Set Pad Configuration DW0 register value */ + Method(SPC0, 0x2, Serialized) + { + /* Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) */ + /* Arg1 - Value for DW0 register */ + Store(Arg0, Local0) + OperationRegion(PDW0, SystemMemory, Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store(Arg1,TEMP) + } + + /* Get Pad Configuration DW1 register value */ + Method(GPC1, 0x1, Serialized) + { + + /* Arg0 = (GpioCommunityAddress + Gpio MMIO_Offset) + 0x4 */ + Store( Add( Arg0, 0x4), Local0) + OperationRegion(PDW1, SystemMemory, Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Return(TEMP) + } + + + /* Set Pad Configuration DW1 register value */ + Method(SPC1, 0x2, Serialized) + { + /* Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) + 0x4 */ + /* Arg1 - Value for DW1 register */ + + Store( Add( Arg0, 0x4), Local0) + OperationRegion(PDW1, SystemMemory, Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store(Arg1,TEMP) + } +} diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 88fa475..c4e6782 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -426,6 +426,11 @@ #define PAD_W(pad) (pad - W_OFFSET) #define PAD_SW(pad) (pad - SW_OFFSET) +/* calculate GPIO DW0 register address */ +#define PAD_IOSF_MMIO(community, pin) \ + ((GPIO_##community << 16) | \ + (PAD_CFG_BASE | PAD_##community(pin) * 8)) + /* Linux names of the GPIO devices. */ #define GPIO_COMM_N_NAME "INT3452:00" #define GPIO_COMM_NW_NAME "INT3452:01"

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coreboot-gerrit August 2016