coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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1820 discussions

New patch to review for coreboot: soc/intel/common: Fix build error in reset.c
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15988 -gerrit commit 27c74c5b1456606137b0f8e747e3497d23567bce Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 10:29:37 2016 -0700 soc/intel/common: Fix build error in reset.c Fix build error when the Kconfig value HAVE_HARD_RESET is not selected. TEST=Build and run on Galileo Gen2 Change-Id: I793570e62a0e46cca86cc540c243e363896ceac7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/common/reset.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index 08f36b6..e9be185 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -33,6 +33,7 @@ void WEAK reset_prepare(void) { /* do nothing */ } +#if IS_ENABLED(CONFIG_HAVE_HARD_RESET) void hard_reset(void) { reset_prepare(); @@ -41,6 +42,7 @@ void hard_reset(void) while (1) hlt(); } +#endif void soft_reset(void) {

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Patch set updated for coreboot: mainboard/intel/galileo: Add FSP 2.0 Kconfig support
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15864 -gerrit commit 9b7181c73c38cc32774d038f02d3ba1cf0f6b610 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:18:13 2016 -0700 mainboard/intel/galileo: Add FSP 2.0 Kconfig support Add and adjust the Kconfig flags to support both FSP 1.1 and FSP 2.0 builds for Quark. TEST=Build and run on Galileo Gen2 Change-Id: I7c5b7efd2635180edcfe4e1a98bb292030117bc8 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index cba65ea..d06b0ba 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -50,5 +50,12 @@ config USE_FSP1_1 bool default n select PLATFORM_USES_FSP1_1 +# select ADD_FSP_RAW_BIN + +config USE_FSP2_0 + bool + default n + select PLATFORM_USES_FSP2_0 + select POSTCAR_STAGE endif # BOARD_INTEL_QUARK

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Patch set updated for coreboot: soc/intel/quark: Add FSP 2.0 boot block support
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15865 -gerrit commit aa614bf57b5afe2a56725e6f5fde6e55bac64f62 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:41:54 2016 -0700 soc/intel/quark: Add FSP 2.0 boot block support Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Bulid and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 1 + src/mainboard/intel/galileo/Makefile.inc | 3 +++ src/mainboard/intel/galileo/gpio.c | 4 ++++ src/mainboard/intel/galileo/romstage.c | 2 ++ src/soc/intel/quark/Kconfig | 1 + src/soc/intel/quark/Makefile.inc | 10 +++++++++ src/soc/intel/quark/fsp2_0.c | 26 +++++++++++++++++++++ src/soc/intel/quark/include/soc/car.h | 29 ++++++++++++++++++++++++ src/soc/intel/quark/include/soc/ramstage.h | 6 +++++ src/soc/intel/quark/include/soc/romstage.h | 4 ++++ src/soc/intel/quark/memmap.c | 4 +++- src/soc/intel/quark/reset.c | 31 ++++++++++++++++++++++++++ src/soc/intel/quark/romstage/Makefile.inc | 3 +++ src/soc/intel/quark/romstage/car_stage_entry.S | 2 ++ src/soc/intel/quark/romstage/fsp2_0.c | 26 +++++++++++++++++++++ 15 files changed, 151 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index d06b0ba..f043474 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -55,6 +55,7 @@ config USE_FSP1_1 config USE_FSP2_0 bool default n + select HAVE_HARD_RESET select PLATFORM_USES_FSP2_0 select POSTCAR_STAGE diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 5aad308..efaf007 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -23,5 +23,8 @@ bootblock-y += reg_access.c romstage-y += gpio.c romstage-y += reg_access.c +postcar-y += gpio.c +postcar-y += reg_access.c + ramstage-y += gpio.c ramstage-y += reg_access.c diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index 8f3c2e3..f654d19 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -15,7 +15,11 @@ #include <arch/io.h> #include <console/console.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> +#else +#include <soc/car.h> +#endif #include <soc/ramstage.h> #include "reg_access.h" #include "gen1.h" diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c index dfae772..baf9af3 100644 --- a/src/mainboard/intel/galileo/romstage.c +++ b/src/mainboard/intel/galileo/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> /* All FSP specific code goes in this block */ @@ -22,3 +23,4 @@ void mainboard_romstage_entry(struct romstage_params *rp) /* Call back into chipset code with platform values updated. */ romstage_common(rp); } +#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */ diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index b2473dc..244cc30 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select REG_SCRIPT select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_RESET select SOC_SETS_MSRS select TSC_CONSTANT_RATE select UART_OVERRIDE_REFCLK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 4740ec7..52d77bf 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -31,22 +31,32 @@ romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c +postcar-y += fsp2_0.c +postcar-y += i2c.c +postcar-y += memmap.c +postcar-y += reg_access.c +postcar-y += tsc_freq.c +postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += reg_access.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include +CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c new file mode 100644 index 0000000..126e131 --- /dev/null +++ b/src/soc/intel/quark/fsp2_0.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <fsp/util.h> +#include <soc/ramstage.h> + +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +{ +} + +asmlinkage void chipset_teardown_car(void) +{ + console_init(); +} diff --git a/src/soc/intel/quark/include/soc/car.h b/src/soc/intel/quark/include/soc/car.h new file mode 100644 index 0000000..23c6a24 --- /dev/null +++ b/src/soc/intel/quark/include/soc/car.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CAR_H_ +#define _SOC_CAR_H_ + +#include <fsp/util.h> + +/* Mainboard and SoC initialization prior to console. */ +void car_mainboard_pre_console_init(void); +void car_soc_pre_console_init(void); + +/* Mainboard and SoC initialization post console initialization. */ +void car_mainboard_post_console_init(void); +void car_soc_post_console_init(void); + +#endif /* _SOC_CAR_H_ */ diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 9f201a0..b5e15ae 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -19,10 +19,16 @@ #include <chip.h> #include <device/device.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/ramstage.h> +#endif #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(device_t dev); +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) void fsp_silicon_init(void); +#else +asmlinkage void chipset_teardown_car(void); +#endif #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index fcac3e2..d6f9186 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,7 +22,11 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> +#else +#include <soc/car.h> +#endif #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index f880443..28f8852 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -14,15 +14,17 @@ */ #include <cbmem.h> +#include <soc/reg_access.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/memmap.h> #include <soc/QuarkNcSocId.h> -#include <soc/reg_access.h> size_t mmap_region_granularity(void) { /* Align to 8 MiB by default */ return 8 << 20; } +#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */ void *cbmem_top(void) { diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c new file mode 100644 index 0000000..e898432 --- /dev/null +++ b/src/soc/intel/quark/reset.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <reset.h> + +void chipset_handle_reset(enum fsp_status status) +{ + switch(status) { + case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ + hard_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 635da83..329138b 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,7 +16,10 @@ romstage-y += car.c romstage-y += car_stage_entry.S romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c + +postcar-y += mtrr.c diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index d0a0db0..b820711 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,9 +29,11 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #if !ENV_VERSTAGE #include "src/drivers/intel/fsp1_1/after_raminit.S" #endif +#endif /* The code should never reach this point */ movb $0x69, %ah diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c new file mode 100644 index 0000000..494f84a --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/romstage.h> + +asmlinkage void *car_stage_c_entry(void) +{ + post_code(0x20); + console_init(); + return NULL; +}

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Patch set updated for coreboot: soc/intel/quark: Add FSP 2.0 romstage support
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15866 -gerrit commit 188a614117677ed7a80aa17b452a5c78f0f92b60 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 10:14:07 2016 -0700 soc/intel/quark: Add FSP 2.0 romstage support Add the pieces necessary to successfully build adn run romstage using the FSP 2.0 build. TEST=Build and run on Galileo Gen2 Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/debug.c | 60 +++++++++++++ src/soc/intel/quark/Kconfig | 16 +++- src/soc/intel/quark/Makefile.inc | 4 + src/soc/intel/quark/include/soc/pm.h | 6 +- src/soc/intel/quark/romstage/Makefile.inc | 5 +- src/soc/intel/quark/romstage/debug.c | 86 ++++++++++++++++++ src/soc/intel/quark/romstage/fsp2_0.c | 140 ++++++++++++++++++++++++++++++ 7 files changed, 313 insertions(+), 4 deletions(-) diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c new file mode 100644 index 0000000..b128bbe --- /dev/null +++ b/src/drivers/intel/fsp2_0/debug.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> +#include <reset.h> +#include <string.h> + +void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new) +{ + size *= 2; + if (old == new) { + printk(BIOS_SPEW, " 0x%0*llx: %s", size, new, name); + } else { + printk(BIOS_SPEW, " 0x%0*llx --> 0x%0*llx: %s", size, size, + old, new, name); + } +} + +void verify_hobs(struct range_entry *fsp_mem, void *hob_list_ptr) +{ + struct range_entry tolum; + + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + fsp_find_bootloader_tolum(&tolum, hob_list_ptr); + if ((tolum.begin == 0) && (tolum.begin == (tolum.end + 1))) + die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + if (range_entry_size(&tolum) < cbmem_overhead_size()) { + printk(BIOS_ERR, "FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08lx\n", + range_entry_size(&tolum), cbmem_overhead_size()); + die("ERROR: FSP_BOOTLOADER_TOLUM_HOB too small!\n"); + } + + /* Locate the FSP reserved memory area */ + fsp_find_reserved_memory(fsp_mem, hob_list_ptr); + if ((fsp_mem->begin == 0) && (fsp_mem->begin == (fsp_mem->end + 1))) + die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + + /* Verify the the bootloader tolum is above the FSP reserved area */ + if (tolum.end <= fsp_mem->begin) + die("ERROR - FSP reserved region after BIOS TOLUM!\n"); + if (tolum.begin <= fsp_mem->end) + die("ERROR - FSP reserved region overlaps BIOS TOLUM!\n"); + if (tolum.begin != (fsp_mem->end + 1)) + die("ERROR - Space between FSP reserved region and BIOS TOLUM!\n"); +} diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 244cc30..2f5bb98 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -127,11 +127,13 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT config DCACHE_RAM_BASE hex + default 0x80000000 if PLATFORM_USES_FSP2_0 default 0x80070000 config DCACHE_RAM_SIZE hex - default 0x00008000 + default 0x40000 if PLATFORM_USES_FSP2_0 + default 0x8000 ##### # Flash layout @@ -194,8 +196,8 @@ config FSP_LOC config FSP_ESRAM_LOC hex + default 0x80040000 if PLATFORM_USES_FSP2_0 default 0x80000000 - depends on PLATFORM_USES_FSP1_1 help The location in ESRAM where a copy of the FSP binary is placed. @@ -206,6 +208,16 @@ config RELOCATE_FSP_INTO_DRAM help Relocate the FSP binary into DRAM before the call to SiliconInit. +config FSP_M_FILE + string + depends on PLATFORM_USES_FSP2_0 + default "3rdparty/blobs/soc/intel/quark/FSP_M.fd" + +config FSP_S_FILE + string + depends on PLATFORM_USES_FSP2_0 + default "3rdparty/blobs/soc/intel/quark/FSP_S.fd" + ##### # RMU binary # The following options control the Quark chipset microcode file diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 52d77bf..bd297ed 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += memmap.c romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c postcar-y += fsp2_0.c postcar-y += i2c.c @@ -61,6 +62,9 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark +# Since FSP-M runs in CAR we need to relocate it to a specific address +$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_ESRAM_LOC) + # Add the FSP binary to the CBFS image cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 7547a53..55e5e95 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -25,6 +25,10 @@ struct chipset_power_state { } __attribute__ ((packed)); struct chipset_power_state *get_power_state(void); +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) struct chipset_power_state *fill_power_state(void); - +#else +int fill_power_state(void); #endif + +#endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 329138b..3a33f43 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -15,8 +15,11 @@ romstage-y += car.c romstage-y += car_stage_entry.S -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c +endif # CONFIG_PLATFORM_USES_FSP2_0 +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c new file mode 100644 index 0000000..6e85a5c --- /dev/null +++ b/src/soc/intel/quark/romstage/debug.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> + +void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd) +{ + const struct FSP_M_CONFIG *new; + const struct FSP_M_CONFIG *old; + + old = &fspm_old_upd->FspmConfig; + new = &fspm_new_upd->FspmConfig; + + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), + old->AddrMode, new->AddrMode); + fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), + old->ChanMask, new->ChanMask); + fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), + old->ChanWidth, new->ChanWidth); + fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), + old->DramDensity, new->DramDensity); + fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), + old->DramRonVal, new->DramRonVal); + fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), + old->DramRttNomVal, new->DramRttNomVal); + fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), + old->DramRttWrVal, new->DramRttWrVal); + fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), + old->DramSpeed, new->DramSpeed); + fsp_display_upd_value("DramType", sizeof(old->DramType), + old->DramType, new->DramType); + fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), + old->DramWidth, new->DramWidth); + fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), + old->EccScrubBlkSize, new->EccScrubBlkSize); + fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), + old->EccScrubInterval, new->EccScrubInterval); + fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, + new->Flags); + fsp_display_upd_value("FspReservedMemoryLength", + sizeof(old->FspReservedMemoryLength), + old->FspReservedMemoryLength, new->FspReservedMemoryLength); + fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, + new->RankMask); + fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), + old->RmuBaseAddress, new->RmuBaseAddress); + fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), + old->RmuLength, new->RmuLength); + fsp_display_upd_value("SerialPortBaseAddress", + sizeof(old->SerialPortBaseAddress), + old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), + old->SmmTsegSize, new->SmmTsegSize); + fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), + old->SocRdOdtVal, new->SocRdOdtVal); + fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), + old->SocWrRonVal, new->SocWrRonVal); + fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), + old->SocWrSlewRate, new->SocWrSlewRate); + fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, + new->SrInt); + fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, + new->SrTemp); + fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); + fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); + fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); + fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); + fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); +} diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 494f84a..073c61a 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -14,13 +14,153 @@ */ #define __SIMPLE_DEVICE__ +#include <arch/early_variables.h> #include <console/console.h> +#include <cbfs.h> +#include <cbmem.h> +#include "../chip.h" #include <fsp/util.h> +#include <lib.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void) { + struct postcar_frame pcf; + bool s3wake; + uintptr_t top_of_ram; + post_code(0x20); console_init(); + + /* Initialize DRAM */ + s3wake = fill_power_state() == ACPI_S3; + fsp_memory_init(s3wake); + + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + disable_rom_shadow(); + + /* Initialize the PCIe bridges */ + pcie_init(); + + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN_DOWN(top_of_ram, 16*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); return NULL; } + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *get_power_state(void) +{ + return (struct chipset_power_state *)car_get_var_ptr(&power_state); +} + +int fill_power_state(void) +{ + struct chipset_power_state *ps = get_power_state(); + + ps->prev_sleep_state = 0; + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps->prev_sleep_state; +} + +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd) +{ + struct FSPM_ARCH_UPD *aupd; + const struct device *dev; + const struct soc_intel_quark_config *config; + char *rmu_file; + size_t rmu_file_len; + struct FSP_M_CONFIG *upd; + + /* Display the ROM shadow data */ + hexdump((void *)0x000ffff0, 0x10); + + /* Clear SMI and wake events */ + clear_smi_and_wake_events(); + + /* Locate the RMU data file in flash */ + rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, + &rmu_file_len); + if (!rmu_file) + die("Microcode file (rmu.bin) not found."); + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + die("ERROR - LPC device not found!"); + } + config = dev->chip_info; + + /* Update the architectural UPD values. */ + printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", + fspm_upd); + aupd = &fspm_upd->FspmArchUpd; + aupd->BootLoaderTolumSize = cbmem_overhead_size(); + aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize); + aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; + + /* Display the ESRAM layout */ + printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); + printk(BIOS_SPEW, "+-------------------+ 0x80080000 - ESRAM end\n"); + printk(BIOS_SPEW, "| FSP binary |\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", + CONFIG_FSP_ESRAM_LOC); + printk(BIOS_SPEW, "| FSP stack |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", aupd->StackBase); + printk(BIOS_SPEW, "| |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + _car_relocatable_data_end); + printk(BIOS_SPEW, "| coreboot data |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", _car_stack_end); + printk(BIOS_SPEW, "| coreboot stack |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x80000000 - ESRAM start\n\n"); + + /* Update the UPD data for MemoryInit */ + upd = &fspm_upd->FspmConfig; + upd->AddrMode = config->AddrMode; + upd->ChanMask = config->ChanMask; + upd->ChanWidth = config->ChanWidth; + upd->DramDensity = config->DramDensity; + upd->DramRonVal = config->DramRonVal; + upd->DramRttNomVal = config->DramRttNomVal; + upd->DramRttWrVal = config->DramRttWrVal; + upd->DramSpeed = config->DramSpeed; + upd->DramType = config->DramType; + upd->DramWidth = config->DramWidth; + upd->EccScrubBlkSize = config->EccScrubBlkSize; + upd->EccScrubInterval = config->EccScrubInterval; + upd->Flags = config->Flags; + upd->FspReservedMemoryLength = config->FspReservedMemoryLength; + upd->RankMask = config->RankMask; + upd->RmuBaseAddress = (uintptr_t)rmu_file; + upd->RmuLength = rmu_file_len; + upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->SmmTsegSize : 0; + upd->SocRdOdtVal = config->SocRdOdtVal; + upd->SocWrRonVal = config->SocWrRonVal; + upd->SocWrSlewRate = config->SocWrSlewRate; + upd->SrInt = config->SrInt; + upd->SrTemp = config->SrTemp; + upd->tCL = config->tCL; + upd->tFAW = config->tFAW; + upd->tRAS = config->tRAS; + upd->tRRD = config->tRRD; + upd->tWTR = config->tWTR; +}

1 0

Patch set updated for coreboot: soc/intel/quark: Fix car_stage_entry routine name.
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15857 -gerrit commit 28f51dec782504812195d270018e1cc97a1ade26 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jul 20 08:41:52 2016 -0700 soc/intel/quark: Fix car_stage_entry routine name. Change routine name from car_state_entry to car_stage_entry. TEST=Build and run on Galileo Gen2 Change-Id: Ifd11db3fa711f2fe52ade1c6cde94f9be1f3a652 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/romstage.h | 2 +- src/soc/intel/quark/romstage/car_stage_entry.S | 2 +- src/soc/intel/quark/romstage/romstage.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 7d89c8b..7e761ab 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -25,7 +25,7 @@ #include <fsp/romstage.h> #include <soc/reg_access.h> -asmlinkage void *car_state_c_entry(void); +asmlinkage void *car_stage_c_entry(void); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); void pcie_init(void); diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index bf51061..d0a0db0 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -27,7 +27,7 @@ car_stage_entry: /* Enter the C code */ - call car_state_c_entry + call car_stage_c_entry #if !ENV_VERSTAGE #include "src/drivers/intel/fsp1_1/after_raminit.S" diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 457c922..4f9b698 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -66,7 +66,7 @@ static const struct reg_script hsuart_init[] = { REG_SCRIPT_END }; -asmlinkage void *car_state_c_entry(void) +asmlinkage void *car_stage_c_entry(void) { post_code(0x20); if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) {

1 0

Patch set updated for coreboot: soc/intel/quark: Remove use of EDK-II macros and data types
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15858 -gerrit commit 487cd1dd65a5f0871495cd0227867159359a1091 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 09:17:10 2016 -0700 soc/intel/quark: Remove use of EDK-II macros and data types Replace the use of ASSERT macro with if/die. Replace the use of UINT32 data type with uint32_t. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2 Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 15 +++++++----- src/soc/intel/quark/chip.h | 52 ++++++++++++++++++++-------------------- src/soc/intel/quark/i2c.c | 20 ++++++++++------ src/soc/intel/quark/memmap.c | 2 +- src/soc/intel/quark/reg_access.c | 12 ++++++---- 5 files changed, 57 insertions(+), 44 deletions(-) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 30ab48a..07eca13 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -101,19 +101,22 @@ static const struct reg_script thermal_init_script[] = { static void chip_init(void *chip_info) { /* Validate the temperature settings */ - ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); - ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS - > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); + if(PLATFORM_CATASTROPHIC_TRIP_CELSIUS > 255) + die("PLATFORM_CATASTROPHIC_TRIP_CELSIUS > 255\n"); + if(PLATFORM_CATASTROPHIC_TRIP_CELSIUS + <= PLATFORM_CATASTROPHIC_CLEAR_CELSIUS) + die("PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= PLATFORM_CATASTROPHIC_CLEAR_CELSIUS\n"); /* Set the temperature settings */ reg_script_run(thermal_init_script); /* Verify that the thermal configuration is locked */ - ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) + if((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) - == (TS_LOCK_THRM_CTRL_REGS_ENABLE - | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); + != (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) + die("(reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) != (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)\n"); /* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 66105ea..b239631 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -47,70 +47,70 @@ struct soc_intel_quark_config { * the FSP PCD field name. */ - UINT32 FspReservedMemoryLength; /* FSP reserved memory in bytes */ + uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */ - UINT32 Flags; /* Bitmap of MRC_FLAG_XXX defs above */ - UINT32 tRAS; /* ACT to PRE command period in picoseconds */ + uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */ + uint32_t tRAS; /* ACT to PRE command period in picoseconds */ /* Delay from start of internal write transaction to internal read * command in picoseconds */ - UINT32 tWTR; + uint32_t tWTR; /* ACT to ACT command period (JESD79 specific to page size 1K/2K) in * picoseconds */ - UINT32 tRRD; + uint32_t tRRD; /* Four activate window (JESD79 specific to page size 1K/2K) in * picoseconds */ - UINT32 tFAW; - UINT8 DramWidth; /* 0=x8, 1=x16, others=RESERVED */ + uint32_t tFAW; + uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */ /* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU * support 1066 memory */ - UINT8 DramSpeed; - UINT8 DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ + uint8_t DramSpeed; + uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ /* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */ - UINT8 RankMask; - UINT8 ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ - UINT8 ChanWidth; /* 1=x16, others=RESERVED */ + uint8_t RankMask; + uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ + uint8_t ChanWidth; /* 1=x16, others=RESERVED */ /* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */ - UINT8 AddrMode; + uint8_t AddrMode; /* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */ - UINT8 SrInt; - UINT8 SrTemp; /* 0=normal, 1=extended, others=RESERVED */ + uint8_t SrInt; + uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */ /* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver * impedance control. */ - UINT8 DramRonVal; - UINT8 DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ - UINT8 DramRttWrVal; /* 0=off others=RESERVED */ + uint8_t DramRonVal; + uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ + uint8_t DramRttWrVal; /* 0=off others=RESERVED */ /* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ - UINT8 SocRdOdtVal; - UINT8 SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ - UINT8 SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ + uint8_t SocRdOdtVal; + uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ + uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ /* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */ - UINT8 DramDensity; - UINT8 tCL; /* DRAM CAS Latency in clocks */ + uint8_t DramDensity; + uint8_t tCL; /* DRAM CAS Latency in clocks */ /* ECC scrub interval in miliseconds 1..255 (0 works as feature * disable) */ - UINT8 EccScrubInterval; + uint8_t EccScrubInterval; /* Number of 32B blocks read for ECC scrub 2..16 */ - UINT8 EccScrubBlkSize; + uint8_t EccScrubBlkSize; - UINT8 SmmTsegSize; /* SMM size in MiB */ + uint8_t SmmTsegSize; /* SMM size in MiB */ }; extern struct chip_operations soc_ops; diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 118cbea..9e02915 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -63,9 +63,12 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) i2c_disable(regs); /* Set the slave address */ - ASSERT (count > 0); - ASSERT (segments != NULL); - ASSERT (segments->read == 0); + if (count == 0) + die("ERROR - count == 0\n"); + if (segments == NULL) + die("ERROR - segments == NULL\n"); + if (segments->read != 0) + die("ERROR - segments->read != \n"); /* Clear the start and stop detection */ status = regs->ic_clr_start_det; @@ -98,9 +101,12 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) while (count-- > 0) { buffer = segments->buf; length = segments->len; - ASSERT (buffer != NULL); - ASSERT (length >= 1); - ASSERT (segments->chip = chip); + if (buffer == NULL) + die("ERROR - buffer == NULL\n"); + if (length < 1) + die("ERROR - length < 1\n"); + if (segments->chip != chip) + die("ERROR - segments->chip != chip\n"); if (segments->read) { /* Place read commands into the FIFO */ @@ -166,7 +172,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) /* Finish reading the data bytes */ while (read_length > 0) { status = regs->ic_status; - *buffer++ = (UINT8)regs->ic_data_cmd; + *buffer++ = (uint8_t)regs->ic_data_cmd; read_length--; bytes_transferred++; status = regs->ic_status; diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 351fab7..f880443 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -26,7 +26,7 @@ size_t mmap_region_granularity(void) void *cbmem_top(void) { - UINT32 top_of_memory; + uint32_t top_of_memory; /* Determine the TSEG base */ top_of_memory = reg_host_bridge_unit_read(QNC_MSG_FSBIC_REG_HSMMC); diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 4f14173..7383ddd 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -26,7 +26,8 @@ static uint16_t get_gpe0_address(uint32_t reg_address) /* Get the GPE0 base address */ gpe0_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GPE0BLK); - ASSERT (gpe0_base_address >= 0x80000000); + if (gpe0_base_address < 0x80000000) + die("ERROR - gpe0_base_address < 0x80000000\n"); gpe0_base_address &= B_QNC_LPC_GPE0BLK_MASK; /* Return the GPE0 register address */ @@ -40,7 +41,8 @@ static uint32_t *get_gpio_address(uint32_t reg_address) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1); gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ASSERT (gpio_base_address != 0x00000000); + if (gpio_base_address == 0) + die("ERROR - gpio_base_address == 0\n"); /* Return the GPIO register address */ return (uint32_t *)(gpio_base_address + reg_address); @@ -53,7 +55,8 @@ void *get_i2c_address(void) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_0); gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ASSERT (gpio_base_address != 0x00000000); + if (gpio_base_address == 0) + die("ERROR - gpio_base_address == 0\n"); /* Return the GPIO register address */ return (void *)gpio_base_address; @@ -65,7 +68,8 @@ static uint16_t get_legacy_gpio_address(uint32_t reg_address) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE); - ASSERT (gpio_base_address >= 0x80000000); + if (gpio_base_address < 0x80000000) + die("ERROR - gpio_base_address < 0x80000000\n"); gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK; /* Return the GPIO register address */

1 0

Patch set updated for coreboot: mainboard/intel/galileo: Remove use of EDK-II macros & data types
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15859 -gerrit commit a0336c633948f791adedde54a7f67f9ffbed1fff Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 09:28:56 2016 -0700 mainboard/intel/galileo: Remove use of EDK-II macros & data types Replace the use of ASSERT macro with if/die. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2. Change-Id: I0756b0f30b3488647530e2dd1a4ab62813815f3e Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/reg_access.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index 36345ff..8934e8a 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -45,8 +45,9 @@ static uint64_t reg_read(struct reg_script_context *ctx) case GEN2_I2C_LED_PWM: if (ctx->display_features) printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id); - ret_code = i2c_readb(0, step->id, (UINT8)step->reg, &value); - ASSERT(ret_code == 2); + ret_code = i2c_readb(0, step->id, (uint8_t)step->reg, &value); + if (ret_code != 2) + die("ERROR - ret_code != 2\n"); break; } return value; @@ -76,9 +77,10 @@ static void reg_write(struct reg_script_context *ctx) case RMU_TEMP_REGS: if (ctx->display_features) printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id); - value = (UINT8)step->value; - ret_code = i2c_writeb(0, step->id, (UINT8)step->reg, value); - ASSERT(ret_code == 2); + value = (uint8_t)step->value; + ret_code = i2c_writeb(0, step->id, (uint8_t)step->reg, value); + if (ret_code != 2) + die("ERROR - ret_code != 2\n"); break; } }

1 0

Patch set updated for coreboot: soc/intel/quark: Initialize MTRRs in bootblock
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15861 -gerrit commit 38de68812fc841bdb51df361260d5db5dc49a1b9 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:11:05 2016 -0700 soc/intel/quark: Initialize MTRRs in bootblock Initialize the MTRRs for use by bootblock and romstage. Display the MTRRs. TEST=Build and run on Galileo Gen2. Change-Id: Ib1d422c738820163f54771c65034ae77301237ec Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/bootblock/bootblock.c | 25 +++++++++++++++++++++++++ src/soc/intel/quark/include/soc/reg_access.h | 1 + src/soc/intel/quark/reg_access.c | 1 - 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 4aa774b..e8fecc2 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include <device/pci_def.h> #include <program_loading.h> #include <soc/iomap.h> +#include <soc/intel/common/util.h> #include <soc/pci_devs.h> #include <soc/reg_access.h> @@ -47,8 +48,26 @@ static const struct reg_script hsuart_init[] = { REG_SCRIPT_END }; +static const struct reg_script mtrr_init[] = { + /* Cache the SPI flash */ + REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE) + | MTRR_TYPE_WRBACK)), + REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE) + | MTRR_PHYS_MASK_VALID)), + + /* Cache ESRAM */ + REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000 + | MTRR_TYPE_WRBACK)), + REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff) + | MTRR_PHYS_MASK_VALID)), + REG_SCRIPT_END +}; + void bootblock_soc_early_init(void) { + /* Initialize the MTRRs */ + reg_script_run(mtrr_init); + /* Initialize the controllers */ reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); @@ -60,6 +79,12 @@ void bootblock_soc_early_init(void) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } +void bootblock_soc_init(void) +{ + /* Display the MTRRs */ + soc_display_mtrrs(); +} + void platform_prog_run(struct prog *prog) { /* Display the program entry point */ diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index a07bd22..0e64917 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -20,6 +20,7 @@ #include <arch/io.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <delay.h> #include <fsp/util.h> #include <reg_script.h> diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 7383ddd..621ef74 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -15,7 +15,6 @@ #define __SIMPLE_DEVICE__ -#include <cpu/x86/mtrr.h> #include <console/console.h> #include <soc/pci_devs.h> #include <soc/ramstage.h>

1 0

Patch set updated for coreboot: soc/intel/quark: Prepare for FSP2.0 support
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15862 -gerrit commit 88b0a856dcf5a32cf7c6adf8bcbd7c9185a0a882 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jul 20 08:58:58 2016 -0700 soc/intel/quark: Prepare for FSP2.0 support Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 1 + src/soc/intel/quark/chip.c | 14 +- src/soc/intel/quark/fsp1_1.c | 35 +++++ src/soc/intel/quark/include/soc/pm.h | 1 + src/soc/intel/quark/include/soc/ramstage.h | 1 + src/soc/intel/quark/include/soc/romstage.h | 2 + src/soc/intel/quark/romstage/Makefile.inc | 2 + src/soc/intel/quark/romstage/car.c | 67 +++++++++ src/soc/intel/quark/romstage/fsp1_1.c | 204 ++++++++++++++++++++++++++ src/soc/intel/quark/romstage/mtrr.c | 2 +- src/soc/intel/quark/romstage/romstage.c | 227 +---------------------------- 11 files changed, 323 insertions(+), 233 deletions(-) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index f5b9746..4740ec7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 07eca13..c8c6b39 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -119,10 +119,7 @@ static void chip_init(void *chip_info) die("(reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) != (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)\n"); /* Perform silicon specific init. */ - if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) - intel_silicon_init(); - else - fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); + fsp_silicon_init(); } static void pci_domain_set_resources(device_t dev) @@ -152,12 +149,3 @@ struct chip_operations soc_intel_quark_ops = { .init = &chip_init, .enable_dev = chip_enable_dev, }; - -void soc_silicon_init_params(SILICON_INIT_UPD *upd) -{ -} - -void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, - SILICON_INIT_UPD *new) -{ -} diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c new file mode 100644 index 0000000..ee10e38 --- /dev/null +++ b/src/soc/intel/quark/fsp1_1.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <fsp/util.h> +#include <soc/ramstage.h> + +void fsp_silicon_init(void) +{ + if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) + intel_silicon_init(); + else + fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); +} + +void soc_silicon_init_params(SILICON_INIT_UPD *upd) +{ +} + +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, + SILICON_INIT_UPD *new) +{ +} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 30d8841..7547a53 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -24,6 +24,7 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __attribute__ ((packed)); +struct chipset_power_state *get_power_state(void); struct chipset_power_state *fill_power_state(void); #endif diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 80e2f00..9f201a0 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -23,5 +23,6 @@ #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(device_t dev); +void fsp_silicon_init(void); #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 7e761ab..fcac3e2 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -26,6 +26,8 @@ #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); +void clear_smi_and_wake_events(void); +void disable_rom_shadow(void); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); void pcie_init(void); diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 16fc5ac..635da83 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -13,7 +13,9 @@ # GNU General Public License for more details. # +romstage-y += car.c romstage-y += car_stage_entry.S +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/car.c b/src/soc/intel/quark/romstage/car.c new file mode 100644 index 0000000..781349c --- /dev/null +++ b/src/soc/intel/quark/romstage/car.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <soc/reg_access.h> + +static const struct reg_script legacy_gpio_init[] = { + /* Temporarily enable the legacy GPIO controller */ + REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID + | LEGACY_GPIO_BASE_ADDRESS), + /* Temporarily enable the GPE controller */ + REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID + | GPE0_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), + REG_SCRIPT_END +}; + +static const struct reg_script i2c_gpio_controller_init[] = { + /* Temporarily enable the GPIO controller */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +static const struct reg_script hsuart_init[] = { + /* Enable the HSUART */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +void car_soc_pre_console_init(void) +{ + /* Initialize the controllers */ + reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); + reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); + + /* Enable the HSUART */ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + reg_script_run_on_dev(HSUART0_BDF, hsuart_init); + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + reg_script_run_on_dev(HSUART1_BDF, hsuart_init); +} + +void car_soc_post_console_init(void) +{ + report_platform_info(); +}; diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c new file mode 100644 index 0000000..a0fb009 --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <cbfs.h> +#include "../chip.h" +#include <fsp/util.h> +#include <lib.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +asmlinkage void *car_stage_c_entry(void) +{ + FSP_INFO_HEADER *fih; + struct cache_as_ram_params car_params = {0}; + void *top_of_stack; + + post_code(0x20); + + /* Copy the FSP binary into ESRAM */ + memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, + 0x00040000); + + /* Locate the FSP header in ESRAM */ + fih = find_fsp(CONFIG_FSP_ESRAM_LOC); + + /* Start the early verstage/romstage code */ + post_code(0x2A); + car_params.fih = fih; + top_of_stack = cache_as_ram_main(&car_params); + + /* Initialize MTRRs and switch stacks after RAM initialized */ + return top_of_stack; +} + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *get_power_state(void) +{ + return (struct chipset_power_state *)car_get_var_ptr(&power_state); +} + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = get_power_state(); + + ps->prev_sleep_state = 0; + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +} + +/* Initialize the UPD parameters for MemoryInit */ +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) +{ + const struct device *dev; + const struct soc_intel_quark_config *config; + char *rmu_file; + size_t rmu_file_len; + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + printk(BIOS_ERR, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return; + } + config = dev->chip_info; + + /* Display the ROM shadow data */ + hexdump((void *)0x000ffff0, 0x10); + + /* Clear SMI and wake events */ + clear_smi_and_wake_events(); + + /* Locate the RMU data file in flash */ + rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, + &rmu_file_len); + if (!rmu_file) + die("Microcode file (rmu.bin) not found."); + + /* Update the UPD data for MemoryInit */ + printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd); + upd->AddrMode = config->AddrMode; + upd->ChanMask = config->ChanMask; + upd->ChanWidth = config->ChanWidth; + upd->DramDensity = config->DramDensity; + upd->DramRonVal = config->DramRonVal; + upd->DramRttNomVal = config->DramRttNomVal; + upd->DramRttWrVal = config->DramRttWrVal; + upd->DramSpeed = config->DramSpeed; + upd->DramType = config->DramType; + upd->DramWidth = config->DramWidth; + upd->EccScrubBlkSize = config->EccScrubBlkSize; + upd->EccScrubInterval = config->EccScrubInterval; + upd->Flags = config->Flags; + upd->FspReservedMemoryLength = config->FspReservedMemoryLength; + upd->RankMask = config->RankMask; + upd->RmuBaseAddress = (uintptr_t)rmu_file; + upd->RmuLength = rmu_file_len; + upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->SmmTsegSize : 0; + upd->SocRdOdtVal = config->SocRdOdtVal; + upd->SocWrRonVal = config->SocWrRonVal; + upd->SocWrSlewRate = config->SocWrSlewRate; + upd->SrInt = config->SrInt; + upd->SrTemp = config->SrTemp; + upd->tCL = config->tCL; + upd->tFAW = config->tFAW; + upd->tRAS = config->tRAS; + upd->tRRD = config->tRRD; + upd->tWTR = config->tWTR; +} + +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) +{ + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), + old->AddrMode, new->AddrMode); + fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), + old->ChanMask, new->ChanMask); + fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), + old->ChanWidth, new->ChanWidth); + fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), + old->DramDensity, new->DramDensity); + fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), + old->DramRonVal, new->DramRonVal); + fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), + old->DramRttNomVal, new->DramRttNomVal); + fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), + old->DramRttWrVal, new->DramRttWrVal); + fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), + old->DramSpeed, new->DramSpeed); + fsp_display_upd_value("DramType", sizeof(old->DramType), + old->DramType, new->DramType); + fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), + old->DramWidth, new->DramWidth); + fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), + old->EccScrubBlkSize, new->EccScrubBlkSize); + fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), + old->EccScrubInterval, new->EccScrubInterval); + fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, + new->Flags); + fsp_display_upd_value("FspReservedMemoryLength", + sizeof(old->FspReservedMemoryLength), + old->FspReservedMemoryLength, new->FspReservedMemoryLength); + fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, + new->RankMask); + fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), + old->RmuBaseAddress, new->RmuBaseAddress); + fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), + old->RmuLength, new->RmuLength); + fsp_display_upd_value("SerialPortBaseAddress", + sizeof(old->SerialPortBaseAddress), + old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), + old->SmmTsegSize, new->SmmTsegSize); + fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), + old->SocRdOdtVal, new->SocRdOdtVal); + fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), + old->SocWrRonVal, new->SocWrRonVal); + fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), + old->SocWrSlewRate, new->SocWrSlewRate); + fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, + new->SrInt); + fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, + new->SrTemp); + fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); + fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); + fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); + fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); + fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); +} + +void soc_after_ram_init(struct romstage_params *params) +{ + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + disable_rom_shadow(); + + /* Initialize the PCIe bridges */ + pcie_init(); +} diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index ce5bd4a..e6bb51f 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -19,7 +19,7 @@ #include <cpu/x86/mtrr.h> #include <soc/intel/common/util.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> +#include <soc/reg_access.h> asmlinkage void *soc_set_mtrrs(void *top_of_stack) { diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4f9b698..9ee4135 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -17,21 +17,14 @@ #include <arch/early_variables.h> #include <console/console.h> -#include <cbfs.h> -#include "../chip.h" -#include <device/pci_def.h> -#include <fsp/car.h> #include <fsp/util.h> #include <lib.h> -#include <soc/intel/common/util.h> -#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <soc/reg_access.h> -#include <string.h> -static const struct reg_script clear_smi_and_wake_events[] = { +static const struct reg_script clear_smi_and_wake_events_script[] = { /* Clear any SMI or wake events */ REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), @@ -40,221 +33,20 @@ static const struct reg_script clear_smi_and_wake_events[] = { REG_SCRIPT_END }; -static const struct reg_script legacy_gpio_init[] = { - /* Temporarily enable the legacy GPIO controller */ - REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID - | LEGACY_GPIO_BASE_ADDRESS), - /* Temporarily enable the GPE controller */ - REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID - | GPE0_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), - REG_SCRIPT_END -}; - -static const struct reg_script i2c_gpio_controller_init[] = { - /* Temporarily enable the GPIO controller */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), - REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), - REG_SCRIPT_END -}; - -static const struct reg_script hsuart_init[] = { - /* Enable the HSUART */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), - REG_SCRIPT_END -}; - -asmlinkage void *car_stage_c_entry(void) -{ - post_code(0x20); - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - FSP_INFO_HEADER *fih; - struct cache_as_ram_params car_params = {0}; - void *top_of_stack; - - /* Copy the FSP binary into ESRAM */ - memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, - 0x00040000); - - /* Locate the FSP header in ESRAM */ - fih = find_fsp(CONFIG_FSP_ESRAM_LOC); - - /* Start the early verstage/romstage code */ - post_code(0x2A); - car_params.fih = fih; - top_of_stack = cache_as_ram_main(&car_params); - - /* Initialize MTRRs and switch stacks after RAM initialized */ - return top_of_stack; - } - - return NULL; -} - -void car_soc_pre_console_init(void) -{ - /* Initialize the controllers */ - reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); - reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); - - /* Enable the HSUART */ - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) - reg_script_run_on_dev(HSUART0_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) - reg_script_run_on_dev(HSUART1_BDF, hsuart_init); -} - -void car_soc_post_console_init(void) -{ - report_platform_info(); -}; - -static struct chipset_power_state power_state CAR_GLOBAL; - -struct chipset_power_state *fill_power_state(void) -{ - struct chipset_power_state *ps = car_get_var_ptr(&power_state); - - ps->prev_sleep_state = ACPI_S0; - printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps; -} - -/* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) +void clear_smi_and_wake_events(void) { - const struct device *dev; - const struct soc_intel_quark_config *config; - struct chipset_power_state *ps = car_get_var_ptr(&power_state); - char *rmu_file; - size_t rmu_file_len; - - /* Locate the configuration data from devicetree.cb */ - dev = dev_find_slot(0, LPC_DEV_FUNC); - if (!dev) { - printk(BIOS_ERR, - "Error! Device (PCI:0:%02x.%01x) not found, " - "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - return; - } - config = dev->chip_info; - - /* Display the ROM shadow data */ - hexdump((void *)0x000ffff0, 0x10); + struct chipset_power_state *ps; /* Clear SMI and wake events */ - if (ps->prev_sleep_state != ACPI_S3) { + ps = get_power_state(); + if (ps->prev_sleep_state != 3) { printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n"); - reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events); + reg_script_run_on_dev(LPC_BDF, + clear_smi_and_wake_events_script); } - - /* Locate the RMU data file in flash */ - rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, - &rmu_file_len); - if (!rmu_file) - die("Microcode file (rmu.bin) not found."); - - /* Update the UPD data for MemoryInit */ - printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd); - upd->AddrMode = config->AddrMode; - upd->ChanMask = config->ChanMask; - upd->ChanWidth = config->ChanWidth; - upd->DramDensity = config->DramDensity; - upd->DramRonVal = config->DramRonVal; - upd->DramRttNomVal = config->DramRttNomVal; - upd->DramRttWrVal = config->DramRttWrVal; - upd->DramSpeed = config->DramSpeed; - upd->DramType = config->DramType; - upd->DramWidth = config->DramWidth; - upd->EccScrubBlkSize = config->EccScrubBlkSize; - upd->EccScrubInterval = config->EccScrubInterval; - upd->Flags = config->Flags; - upd->FspReservedMemoryLength = config->FspReservedMemoryLength; - upd->RankMask = config->RankMask; - upd->RmuBaseAddress = (uintptr_t)rmu_file; - upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; - upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? - config->SmmTsegSize : 0; - upd->SocRdOdtVal = config->SocRdOdtVal; - upd->SocWrRonVal = config->SocWrRonVal; - upd->SocWrSlewRate = config->SocWrSlewRate; - upd->SrInt = config->SrInt; - upd->SrTemp = config->SrTemp; - upd->tCL = config->tCL; - upd->tFAW = config->tFAW; - upd->tRAS = config->tRAS; - upd->tRRD = config->tRRD; - upd->tWTR = config->tWTR; } -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) -{ - /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); - fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), - old->AddrMode, new->AddrMode); - fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), - old->ChanMask, new->ChanMask); - fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), - old->ChanWidth, new->ChanWidth); - fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), - old->DramDensity, new->DramDensity); - fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), - old->DramRonVal, new->DramRonVal); - fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), - old->DramRttNomVal, new->DramRttNomVal); - fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), - old->DramRttWrVal, new->DramRttWrVal); - fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), - old->DramSpeed, new->DramSpeed); - fsp_display_upd_value("DramType", sizeof(old->DramType), - old->DramType, new->DramType); - fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), - old->DramWidth, new->DramWidth); - fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), - old->EccScrubBlkSize, new->EccScrubBlkSize); - fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), - old->EccScrubInterval, new->EccScrubInterval); - fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, - new->Flags); - fsp_display_upd_value("FspReservedMemoryLength", - sizeof(old->FspReservedMemoryLength), - old->FspReservedMemoryLength, new->FspReservedMemoryLength); - fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, - new->RankMask); - fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), - old->RmuBaseAddress, new->RmuBaseAddress); - fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), - old->RmuLength, new->RmuLength); - fsp_display_upd_value("SerialPortBaseAddress", - sizeof(old->SerialPortBaseAddress), - old->SerialPortBaseAddress, new->SerialPortBaseAddress); - fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), - old->SmmTsegSize, new->SmmTsegSize); - fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), - old->SocRdOdtVal, new->SocRdOdtVal); - fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), - old->SocWrRonVal, new->SocWrRonVal); - fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), - old->SocWrSlewRate, new->SocWrSlewRate); - fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, - new->SrInt); - fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, - new->SrTemp); - fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); - fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); - fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); - fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); - fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); -} - -void soc_after_ram_init(struct romstage_params *params) +void disable_rom_shadow(void) { uint32_t data; @@ -273,7 +65,4 @@ void soc_after_ram_init(struct romstage_params *params) /* Display the DRAM data */ hexdump((void *)0x000ffff0, 0x10); - - /* Initialize the PCIe bridges */ - pcie_init(); }

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Patch set updated for coreboot: soc/intel/quark: Add header files for FSP 2.0
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15863 -gerrit commit 091f57c6d39c55df401f16b039c3d657e2eb8621 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:00:50 2016 -0700 soc/intel/quark: Add header files for FSP 2.0 Add the FSP 2.0 header files for Quark. These files were run through the drivers/intel/fsp2_0/header_util to convert the data types so that they are compatible with the coreboot build system. TEST=Build and run on Galileo Gen2. Change-Id: I15548888215cc811fa753d30b65e3a19e3f8ff8d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/fsp/FspEas.h | 42 +++++ src/soc/intel/quark/include/soc/fsp/FspUpd.h | 44 +++++ src/soc/intel/quark/include/soc/fsp/FspmUpd.h | 223 ++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/fsp/FspsUpd.h | 52 ++++++ src/soc/intel/quark/include/soc/fsp/FsptUpd.h | 89 ++++++++++ 5 files changed, 450 insertions(+) diff --git a/src/soc/intel/quark/include/soc/fsp/FspEas.h b/src/soc/intel/quark/include/soc/fsp/FspEas.h new file mode 100644 index 0000000..48d956e --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspEas.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPEAS_H__ +#define __FSPEAS_H__ + +#include <fsp/upd.h> +#include <soc/fsp/FspmUpd.h> +#include <soc/fsp/FspsUpd.h> +#include <soc/fsp/FsptUpd.h> +#include <fsp/api.h> + +#endif /* _FSPEAS_H_ */ diff --git a/src/soc/intel/quark/include/soc/fsp/FspUpd.h b/src/soc/intel/quark/include/soc/fsp/FspUpd.h new file mode 100644 index 0000000..d3277d9 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspUpd.h @@ -0,0 +1,44 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ + +#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h new file mode 100644 index 0000000..bb0fc51 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h @@ -0,0 +1,223 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + + +/** Fsp M Configuration +**/ +struct FSP_M_CONFIG { + +/** Offset 0x0040 - RmuBaseAddress + RMU microcode binary base address in SPI flash' +**/ + uint32_t RmuBaseAddress; + +/** Offset 0x0044 - RmuLength + RMU microcode binary length in bytes +**/ + uint32_t RmuLength; + +/** Offset 0x0048 - SerialPortBaseAddress + Debug serial port base address set by BIOS. Zero disables debug serial output. +**/ + uint32_t SerialPortBaseAddress; + +/** Offset 0x004C - tRAS + ACT to PRE command period in picoseconds. +**/ + uint32_t tRAS; + +/** Offset 0x0050 - tWTR + Delay from start of internal write transaction to internal read command in picoseconds. +**/ + uint32_t tWTR; + +/** Offset 0x0054 - tRRD + ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + uint32_t tRRD; + +/** Offset 0x0058 - tFAW + Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + uint32_t tFAW; + +/** Offset 0x005C - Flags + Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN + BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" + topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices + on writes. +**/ + uint32_t Flags; + +/** Offset 0x0060 - DramWidth + 0=x8, 1=x16, others=RESERVED. +**/ + uint8_t DramWidth; + +/** Offset 0x0061 - DramSpeed + 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. +**/ + uint8_t DramSpeed; + +/** Offset 0x0062 - DramType + 0=DDR3, 1=DDR3L, others=RESERVED. +**/ + uint8_t DramType; + +/** Offset 0x0063 - RankMask + bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. +**/ + uint8_t RankMask; + +/** Offset 0x0064 - ChanMask + bit[0] CHAN0_EN, others=RESERVED. +**/ + uint8_t ChanMask; + +/** Offset 0x0065 - ChanWidth + 1=x16, others=RESERVED. +**/ + uint8_t ChanWidth; + +/** Offset 0x0066 - AddrMode + 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. +**/ + uint8_t AddrMode; + +/** Offset 0x0067 - SrInt + 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. +**/ + uint8_t SrInt; + +/** Offset 0x0068 - SrTemp + 0=normal, 1=extended, others=RESERVED. +**/ + uint8_t SrTemp; + +/** Offset 0x0069 - DramRonVal + 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. +**/ + uint8_t DramRonVal; + +/** Offset 0x006A - DramRttNomVal + 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. +**/ + uint8_t DramRttNomVal; + +/** Offset 0x006B - DramRttWrVal + 0=off others=RESERVED. +**/ + uint8_t DramRttWrVal; + +/** Offset 0x006C - SocRdOdtVal + 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. +**/ + uint8_t SocRdOdtVal; + +/** Offset 0x006D - SocWrRonVal + 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. +**/ + uint8_t SocWrRonVal; + +/** Offset 0x006E - SocWrSlewRate + 0=2.5V/ns, 1=4V/ns, others=RESERVED. +**/ + uint8_t SocWrSlewRate; + +/** Offset 0x006F - DramDensity + 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. +**/ + uint8_t DramDensity; + +/** Offset 0x0070 - tCL + DRAM CAS Latency in clocks +**/ + uint8_t tCL; + +/** Offset 0x0071 - EccScrubInterval + ECC scrub interval in miliseconds 1..255 (0 works as feature disable +**/ + uint8_t EccScrubInterval; + +/** Offset 0x0072 - EccScrubBlkSize + Number of 32B blocks read for ECC scrub 2..16 +**/ + uint8_t EccScrubBlkSize; + +/** Offset 0x0073 - SmmTsegSize + Size of the SMM region in 1 MiB chunks +**/ + uint8_t SmmTsegSize; + +/** Offset 0x0074 - FspReservedMemoryLength + FSP reserved memory length in bytes +**/ + uint32_t FspReservedMemoryLength; + +/** Offset 0x0078 - MrcDataPtr + Pointer to saved MRC data +**/ + uint32_t MrcDataPtr; + +/** Offset 0x007C - MrcDataLength + Length of saved MRC data +**/ + uint32_t MrcDataLength; + +/** Offset 0x0080 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +/** Fsp M UPD Configuration +**/ +struct FSPM_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + struct FSP_M_CONFIG FspmConfig; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspsUpd.h b/src/soc/intel/quark/include/soc/fsp/FspsUpd.h new file mode 100644 index 0000000..6b054e8 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspsUpd.h @@ -0,0 +1,52 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + + +/** Fsp S UPD Configuration +**/ +struct FSPS_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FsptUpd.h b/src/soc/intel/quark/include/soc/fsp/FsptUpd.h new file mode 100644 index 0000000..8b1ded7 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FsptUpd.h @@ -0,0 +1,89 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + + +/** Fsp T Common UPD +**/ +struct FSPT_COMMON_UPD { + +/** Offset 0x0020 +**/ + uint8_t Revision; + +/** Offset 0x0021 +**/ + uint8_t Reserved[3]; + +/** Offset 0x0024 +**/ + uint32_t MicrocodeRegionBase; + +/** Offset 0x0028 +**/ + uint32_t MicrocodeRegionLength; + +/** Offset 0x002C +**/ + uint32_t CodeRegionBase; + +/** Offset 0x0030 +**/ + uint32_t CodeRegionLength; + +/** Offset 0x0034 +**/ + uint8_t Reserved1[12]; +} __attribute__((packed)); + +/** Fsp T UPD Configuration +**/ +struct FSPT_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSPT_COMMON_UPD FsptCommonUpd; + +/** Offset 0x0040 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif

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coreboot-gerrit July 2016