coreboot-gerrit July 2016

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Patch set updated for coreboot: drivers/intel/fsp2_0: Monitor FSP setting of MTRRs
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15849 -gerrit commit 85feccb333302a5107d9b31e360f1598ee0faa9e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 08:26:06 2016 -0700 drivers/intel/fsp2_0: Monitor FSP setting of MTRRs Display the MTRR values in the following locations: * Before the call to FspMemoryInit to document coreboot settings * After the call to FspMemoryInit * After the call to FspSiliconInit * After the call to FspNotify TEST=Build and run on Galileo Gen2 Change-Id: I8942ef4ca4677501a5c38abaff1c3489eebea53c Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/debug.h | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 3fbc609..976e0fe 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -17,13 +17,34 @@ #include <fsp/api.h> #include <fsp/util.h> #include <memrange.h> +#include <soc/intel/common/util.h> +/*----------- + * HOBs + *----------- + */ struct hob_header { uint16_t type; uint16_t length; } __attribute__((packed)); /*----------- + * MTRRs + *----------- + */ +#if IS_ENABLED(CONFIG_DISPLAY_MTRRS) +static inline __attribute__((always_inline)) void fsp_display_mtrrs(void) +{ + /* Display the MTRRs */ + soc_display_mtrrs(); +} +#else /* CONFIG_DISPLAY_MTRRS */ +static inline __attribute__((always_inline)) void fsp_display_mtrrs(void) +{ +} +#endif /* CONFIG_DISPLAY_MTRRS */ + +/*----------- * MemoryInit *----------- */ @@ -36,6 +57,9 @@ static inline __attribute__((always_inline)) void fsp_debug_before_memory_init( const struct FSPM_UPD *fspm_new_upd, void **hob_list_ptr) { + /* Display the MTRRs */ + fsp_display_mtrrs(); + /* Display the call entry point and paramters */ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", @@ -50,6 +74,9 @@ static inline __attribute__((always_inline)) void fsp_debug_memory_init( { if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + + /* Display the MTRRs */ + fsp_display_mtrrs(); } /*----------- @@ -75,6 +102,9 @@ static inline __attribute__((always_inline)) void fsp_debug_silicon_init( { if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); + + /* Display the MTRRs */ + fsp_display_mtrrs(); } /*----------- @@ -105,6 +135,9 @@ static inline __attribute__((always_inline)) void fsp_debug_notify( { if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status); + + /* Display the MTRRs */ + fsp_display_mtrrs(); } #endif /* _FSP2_0_DEBUG_H_ */

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add display HOB support
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15851 -gerrit commit 68971e08a410c2a0289317b3ae106ad339089330 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jul 27 07:40:25 2016 -0700 drivers/intel/fsp2_0: Add display HOB support Add support to display the HOBs returned by FSP: * Add Kconfig value to enable HOB display * Move hob_header, hob_resource and uuid_name structures into debug.h * Move hob_type enum into debug.h * Remove static from the debug utility functions * Add fsp_ prefix to the debug utility functions * Declare the debug utility functions in debug.h * Add HOB type name table * Add more GUID values * Add new GUID name table for additional GUIDs * Add routine to convert EDK-II GUID into a name * Add SOC specific routine to handle unknown GUID types * Add routine to convert HOB type into a name * Add SOC specific routine to handle unknown HOB types * Add routine to display the hobs TEST=Build and run on Galileo Gen2 Change-Id: I10606d752859fff0f4f08a5ac03ab129b2c96d1f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 6 + src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/hand_off_block.c | 68 ++++-------- src/drivers/intel/fsp2_0/hob_display.c | 157 +++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 69 ++++++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 7 +- 6 files changed, 262 insertions(+), 47 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 32dbb59..06f1a7c 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,12 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP. +config DISPLAY_HOBS + bool "Display the hand-off-blocks" + default n + help + Display the FSP HOBs which are provided for coreboot. + config DISPLAY_UPD_DATA bool "Display UPD data" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 91e86b5..5b8c663 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -16,12 +16,14 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-y += util.c romstage-y += memory_init.c ramstage-y += graphics.c ramstage-y += hand_off_block.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index ce06a82..d3392cd 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -21,14 +21,6 @@ #define HOB_HEADER_LEN 8 -struct hob_resource { - uint8_t owner_guid[16]; - uint32_t type; - uint32_t attribute_type; - uint64_t addr; - uint64_t length; -} __attribute__((packed)); - enum resource_type { EFI_RESOURCE_SYSTEM_MEMORY = 0, EFI_RESOURCE_MEMORY_MAPPED_IO = 1, @@ -50,21 +42,6 @@ static const char *resource_names[] = { [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED", }; -enum hob_type { - HOB_TYPE_HANDOFF = 0x0001, - HOB_TYPE_MEMORY_ALLOCATION = 0x0002, - HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, - HOB_TYPE_GUID_EXTENSION = 0x0004, - HOB_TYPE_FV = 0x0005, - HOB_TYPE_CPU = 0x0006, - HOB_TYPE_MEMORY_POOL = 0x0007, - HOB_TYPE_FV2 = 0x0009, - HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, - HOB_TYPE_UCAPSULE = 0x000B, - HOB_TYPE_UNUSED = 0xFFFE, - HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, -}; - /* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ static const uint8_t uuid_owner_bootloader_tolum[16] = { 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, @@ -90,15 +67,13 @@ static const uint8_t empty_uuid[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -static const struct uuid_name_map { - const void *uuid; - const char *name; -} uuid_names[] = { +const struct uuid_name_map uuid_names[] = { { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, { uuid_owner_tseg, "TSEG" }, { uuid_fsp_nv_storage, "FSP_NV_STORAGE" }, }; +const size_t uuid_names_entries = ARRAY_SIZE(uuid_names); static const char *resource_name(enum resource_type type) { @@ -111,7 +86,7 @@ static const char *resource_name(enum resource_type type) * Utilities for walking HOBs */ -static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) +bool fsp_uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) { return !memcmp(uuid1, uuid2, 16); } @@ -123,13 +98,13 @@ static const char *uuid_name(const uint8_t uuid[16]) for (i = 0; i < ARRAY_SIZE(uuid_names); i++) { owner_entry = uuid_names + i; - if (uuid_compare(uuid, owner_entry->uuid)) + if (fsp_uuid_compare(uuid, owner_entry->uuid)) return owner_entry->name; } return "UNKNOWN"; } -static const struct hob_header *next_hob(const struct hob_header *parent) +const struct hob_header *fsp_next_hob(const struct hob_header *parent) { union { const struct hob_header *hob; @@ -167,8 +142,8 @@ static const void *hob_header_to_extension_hob(const struct hob_header *hob) return hob_walker.hob_descr; } -static const -struct hob_resource *hob_header_to_resource(const struct hob_header *hob) +const +struct hob_resource *fsp_hob_header_to_resource(const struct hob_header *hob) { return hob_header_to_struct(hob); } @@ -197,13 +172,14 @@ struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, { const struct hob_resource *res; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) continue; - res = hob_header_to_resource(hob); - if (uuid_compare(res->owner_guid, uuid)) + res = fsp_hob_header_to_resource(hob); + if (fsp_uuid_compare(res->owner_guid, uuid)) return res; } return NULL; @@ -228,7 +204,7 @@ void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list) * Utilities for printing HOB information */ -static void print_guid(const void *base) +void fsp_print_guid(const void *base) { uint32_t big; uint16_t mid[2]; @@ -243,30 +219,30 @@ static void print_guid(const void *base) id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); } -static void print_resource_descriptor(const void *base) +void fsp_print_resource_descriptor(const void *base) { const struct hob_resource *res; - res = hob_header_to_resource(base); + res = fsp_hob_header_to_resource(base); printk(BIOS_DEBUG, "Resource %s, attribute %x\n", resource_name(res->type), res->attribute_type); printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); - if (!uuid_compare(res->owner_guid, empty_uuid)) { + if (!fsp_uuid_compare(res->owner_guid, empty_uuid)) { printk(BIOS_DEBUG, "\tOwner GUID: "); - print_guid(res->owner_guid); + fsp_print_guid(res->owner_guid); printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); } } - void fsp_print_memory_resource_hobs(const void *hob_list) { const struct hob_header *hob = hob_list; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + hob = fsp_next_hob(hob)) { if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR) - print_resource_descriptor(hob); + fsp_print_resource_descriptor(hob); } } @@ -278,13 +254,14 @@ const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) if (!hob) return NULL; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_GUID_EXTENSION) continue; hob_uuid = hob_header_to_struct(hob); - if (uuid_compare(hob_uuid, uuid)) { + if (fsp_uuid_compare(hob_uuid, uuid)) { *size = hob->length - (HOB_HEADER_LEN + 16); return hob_header_to_extension_hob(hob); } @@ -293,7 +270,6 @@ const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) return NULL; } - const void *fsp_find_nv_storage_data(size_t *size) { return fsp_find_extension_hob_by_uuid(uuid_fsp_nv_storage, size); diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c new file mode 100644 index 0000000..1b10ed4 --- /dev/null +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <fsp/util.h> + +struct hob_type_name { + uint16_t type; + const char *name; +} __attribute__((packed)); + +static const struct hob_type_name hob_type_names [] = { + { HOB_TYPE_HANDOFF, "HOB_TYPE_HANDOFF" }, + { HOB_TYPE_MEMORY_ALLOCATION, "HOB_TYPE_MEMORY_ALLOCATION" }, + { HOB_TYPE_RESOURCE_DESCRIPTOR, "HOB_TYPE_RESOURCE_DESCRIPTOR" }, + { HOB_TYPE_GUID_EXTENSION, "HOB_TYPE_GUID_EXTENSION" }, + { HOB_TYPE_FV, "HOB_TYPE_FV" }, + { HOB_TYPE_CPU, "HOB_TYPE_CPU" }, + { HOB_TYPE_MEMORY_POOL, "HOB_TYPE_MEMORY_POOL" }, + { HOB_TYPE_FV2, "HOB_TYPE_FV2" }, + { HOB_TYPE_LOAD_PEIM_UNUSED, "HOB_TYPE_LOAD_PEIM_UNUSED" }, + { HOB_TYPE_UCAPSULE, "HOB_TYPE_UCAPSULE" }, + { HOB_TYPE_UNUSED, "HOB_TYPE_UNUSED" }, + { HOB_TYPE_END_OF_HOB_LIST, "HOB_TYPE_END_OF_HOB_LIST" } +}; + +static const uint8_t uuid_graphics_info[16] = { + 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 +}; + +static const uint8_t uuid_smbios_memory_info[16] = { + 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 +}; + +static const uint8_t uuid_bootloader_temp_memory[16] = { + 0x6c, 0xf4, 0xcf, 0xbb, 0xd3, 0xc8, 0x13, 0x41, + 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e +}; + +static const uint8_t uuid_fsp_info_header[16] = { + 0xbe, 0x40, 0x27, 0x91, 0x84, 0x22, 0x34, 0x47, + 0xb9, 0x71, 0x84, 0xb0, 0x27, 0x35, 0x3f, 0x0c +}; + +static const struct uuid_name_map guid_names[] = { + { uuid_graphics_info, "GRAPHICS INFO" }, + { uuid_smbios_memory_info, "FSP_SMBIOS_MEMORY_INFO_GUID" }, + { uuid_bootloader_temp_memory, "FSP_BOOTLOADER_TEMP_MEMORY_HOB_GUID" }, + { uuid_fsp_info_header, "FSP_INFO_HEADER_GUID" }, +}; + +const char *fsp_get_hob_type_name(const struct hob_header *hob) +{ + size_t index; + const char *name; + + for (index = 0; index < ARRAY_SIZE(hob_type_names); index++) + if (hob->type == hob_type_names[index].type) + return hob_type_names[index].name; + + /* Get name for SOC specific hob */ + name = soc_get_hob_type_name(hob); + if (name != NULL) + return name; + return "Unknown HOB type"; +} + +const char *fsp_get_guid_name(const uint8_t *guid) +{ + size_t index; + const char *name; + + /* Compare the GUID values in hand_off_block.c */ + for (index = 0; index < uuid_names_entries; index++) + if (fsp_uuid_compare(guid, uuid_names[index].uuid)) + return uuid_names[index].name; + + /* Compare the GUID values in this module */ + for (index = 0; index < ARRAY_SIZE(guid_names); index++) + if (fsp_uuid_compare(guid, guid_names[index].uuid)) + return guid_names[index].name; + + /* Get GUID name from SOC */ + name = soc_get_guid_name(guid); + if (name != NULL) + return name; + return "Unknown GUID"; +} + +__attribute__((weak)) const char *soc_get_hob_type_name( + const struct hob_header *hob) +{ + return NULL; +} + +void fsp_print_guid_extension_hob(const struct hob_header *hob) +{ + const struct hob_resource *res; + + res = fsp_hob_header_to_resource(hob); + printk(BIOS_DEBUG, "\t"); + fsp_print_guid(res->owner_guid); + printk(BIOS_DEBUG, ": %s\n", fsp_get_guid_name(res->owner_guid)); +} + +__attribute__((weak)) const char *soc_get_guid_name(const uint8_t *guid) +{ + return NULL; +} + +void fsp_display_hobs(const struct hob_header *hob_list_ptr) +{ + const struct hob_header *hob = hob_list_ptr; + + /* Display the HOB list pointer */ + printk(BIOS_DEBUG, "\n=== FSP HOBs ===\n"); + printk(BIOS_DEBUG, "0x%p: hob_list_ptr\n", hob); + + /* Walk the list of HOBs */ + while (1) { + /* Display the HOB header */ + printk(BIOS_DEBUG, "0x%p, 0x%08x bytes: %s\n", hob, hob->length, + fsp_get_hob_type_name(hob)); + switch(hob->type) { + default: + soc_display_hob(hob); + break; + + case HOB_TYPE_END_OF_HOB_LIST: + printk(BIOS_DEBUG, "=== End of FSP HOBs ===\n\n"); + return; + + case HOB_TYPE_RESOURCE_DESCRIPTOR: + fsp_print_resource_descriptor(hob); + break; + + case HOB_TYPE_GUID_EXTENSION: + fsp_print_guid_extension_hob(hob); + break; + } + hob = fsp_next_hob(hob); + } +} + +__attribute__((weak)) void soc_display_hob(const struct hob_header *hob) +{ +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 7c48886..8935ce1 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -28,6 +28,66 @@ struct hob_header { uint16_t length; } __attribute__((packed)); +struct hob_resource { + uint8_t owner_guid[16]; + uint32_t type; + uint32_t attribute_type; + uint64_t addr; + uint64_t length; +} __attribute__((packed)); + +struct uuid_name_map { + const void *uuid; + const char *name; +}; + +enum hob_type { + HOB_TYPE_HANDOFF = 0x0001, + HOB_TYPE_MEMORY_ALLOCATION = 0x0002, + HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, + HOB_TYPE_GUID_EXTENSION = 0x0004, + HOB_TYPE_FV = 0x0005, + HOB_TYPE_CPU = 0x0006, + HOB_TYPE_MEMORY_POOL = 0x0007, + HOB_TYPE_FV2 = 0x0009, + HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, + HOB_TYPE_UCAPSULE = 0x000B, + HOB_TYPE_UNUSED = 0xFFFE, + HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, +}; + +extern const struct uuid_name_map uuid_names[]; +extern const size_t uuid_names_entries; + +/* + * Hand-off-block handling functions that depend on CBMEM, and thus can only + * be used after cbmem_initialize(). + */ +const void *fsp_get_hob_list(void); + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +/* Display HOBs API */ +void fsp_display_hobs(const struct hob_header *hob_list_ptr); + +/* Callbacks for displaying HOBs - place in a separate file that is + * conditionally build with CONFIG_DISPLAY_HOBS. + */ +const char *soc_get_hob_type_name(const struct hob_header *hob); +const char *soc_get_guid_name(const uint8_t *guid); +void soc_display_hob(const struct hob_header *hob); + +/* Display HOBs utility functions */ +const char *fsp_get_hob_type_name(const struct hob_header *hob); +const char *fsp_get_guid_name(const uint8_t *guid); +void fsp_print_guid_extension_hob(const struct hob_header *hob); +#else /* CONFIG_DISPLAY_HOBS */ +/* Remove HOB display code from the image */ +static inline __attribute__((always_inline)) void fsp_display_hobs( + const struct hob_header *hob_list_ptr) +{ +} +#endif /* CONFIG_DISPLAY_HOBS */ + /*----------- * MTRRs *----------- @@ -113,6 +173,9 @@ static inline __attribute__((always_inline)) void fsp_debug_memory_init( if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + /* Display the HOBs */ + fsp_display_hobs(hob_list_ptr); + /* Display the MTRRs */ fsp_display_mtrrs(); } @@ -144,6 +207,9 @@ static inline __attribute__((always_inline)) void fsp_debug_silicon_init( if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); + /* Display the HOBs */ + fsp_display_hobs((const struct hob_header *)fsp_get_hob_list()); + /* Display the MTRRs */ fsp_display_mtrrs(); } @@ -177,6 +243,9 @@ static inline __attribute__((always_inline)) void fsp_debug_notify( if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status); + /* Display the HOBs */ + fsp_display_hobs((const struct hob_header *)fsp_get_hob_list()); + /* Display the MTRRs */ fsp_display_mtrrs(); } diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index cc70cc1..c84a017 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -25,7 +25,6 @@ * be used after cbmem_initialize(). */ void fsp_save_hob_list(void *hob_list_ptr); -const void *fsp_get_hob_list(void); const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size); const void *fsp_find_nv_storage_data(size_t *size); enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); @@ -34,7 +33,13 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); * the HOB list explicitly. */ void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list); +const struct hob_resource *fsp_hob_header_to_resource( + const struct hob_header *hob); +const struct hob_header *fsp_next_hob(const struct hob_header *parent); +void fsp_print_guid(const void *guid); void fsp_print_memory_resource_hobs(const void *hob_list); +void fsp_print_resource_descriptor(const void *base); +bool fsp_uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]); /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr,

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInit
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15850 -gerrit commit 04318f63739e6d1b3ba0d670067d6c299305b3c5 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 09:52:38 2016 -0700 drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInit Verify that FSP is properly returning: * HOB list pointer * FSP_BOOTLOADER_TOLUM_HOB * FSP_RESERVED_MEMORY_RESOURCE_HOB TEST=Build and run on Galileo Gen2 Change-Id: I23005d10f7f3ccf06a2e29dab5fa11c7ed79f187 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 ++++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/hand_off_block.c | 15 +++++-- src/drivers/intel/fsp2_0/hob_verify.c | 63 ++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 30 ++++++++++++- src/drivers/intel/fsp2_0/include/fsp/util.h | 3 +- src/drivers/intel/fsp2_0/memory_init.c | 4 +- 7 files changed, 116 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 06f1a7c..4ff6116 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -73,4 +73,11 @@ config FSP_M_XIP help Select this value when FSP-M is execute-in-place. +config VERIFY_HOBS + bool "Verify the FSP hand-off-blocks" + default n + help + Verify that the HOBs required by coreboot are returned by FSP and + that the resource HOBs are in the correct order and position. + endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 5b8c663..9982dcb 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -18,12 +18,14 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += hand_off_block.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c ramstage-y += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c +ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index d3392cd..9693cd2 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -43,7 +43,7 @@ static const char *resource_names[] = { }; /* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ -static const uint8_t uuid_owner_bootloader_tolum[16] = { +const uint8_t uuid_owner_bootloader_tolum[16] = { 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44, }; @@ -185,13 +185,14 @@ struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, return NULL; } -void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list) +void fsp_find_range_hob(struct range_entry *re, const void *hob_list, + const uint8_t uuid[16]) { const struct hob_resource *fsp_mem; range_entry_init(re, 0, 0, 0); - fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp); + fsp_mem = find_resource_hob_by_uuid(hob_list, uuid); if (!fsp_mem) { return; @@ -200,6 +201,14 @@ void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list) range_entry_init(re, fsp_mem->addr, fsp_mem->addr + fsp_mem->length, 0); } +struct range_entry fsp_find_reserved_memory(const void *hob_list) +{ + struct range_entry re; + + fsp_find_range_hob(&re, hob_list, uuid_owner_fsp); + return re; +} + /* * Utilities for printing HOB information */ diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c new file mode 100644 index 0000000..b73f7cc --- /dev/null +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> + +struct range_entry fsp_find_bootloader_tolum(const void *hob_list) +{ + struct range_entry re; + + fsp_find_range_hob(&re, hob_list, uuid_owner_bootloader_tolum); + return re; +} + +void fsp_verify_hobs(const struct hob_header *hob_list_ptr) +{ + struct range_entry fsp_mem; + struct range_entry tolum; + + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + tolum = fsp_find_bootloader_tolum(hob_list_ptr); + if ((range_entry_base(&tolum) == 0) + && (range_entry_base(&tolum) == range_entry_end(&tolum))) + die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + if (range_entry_size(&tolum) < cbmem_overhead_size()) { + printk(BIOS_ERR, + "FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08lx\n", + range_entry_size(&tolum), cbmem_overhead_size()); + die("ERROR: FSP_BOOTLOADER_TOLUM_HOB too small!\n"); + } + + /* Locate the FSP reserved memory area */ + fsp_mem = fsp_find_reserved_memory(hob_list_ptr); + if ((range_entry_base(&fsp_mem) == 0) + && (range_entry_base(&fsp_mem) == range_entry_end(&fsp_mem))) + die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + + /* Verify the the bootloader tolum is above the FSP reserved area */ + if (range_entry_end(&tolum) <= range_entry_base(&fsp_mem)) + die("ERROR - FSP reserved region after BIOS TOLUM!\n"); + if (range_entry_base(&tolum) < range_entry_end(&fsp_mem)) + die("ERROR - FSP reserved region overlaps BIOS TOLUM!\n"); + + /* Verify that the FSP reserved area immediately follows the BIOS + * reserved area + */ + if (range_entry_base(&tolum) != range_entry_end(&fsp_mem)) + die("ERROR - Space between FSP reserved region and BIOS TOLUM!\n"); + + if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + printk(BIOS_CRIT, "0x%p: cbmem_top\n", cbmem_top()); + die("ERROR - Space between cbmem_top and BIOS TOLUM!\n"); + } +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 8935ce1..26d13ae 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -56,6 +56,7 @@ enum hob_type { HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, }; +extern const uint8_t uuid_owner_bootloader_tolum[16]; extern const struct uuid_name_map uuid_names[]; extern const size_t uuid_names_entries; @@ -65,6 +66,13 @@ extern const size_t uuid_names_entries; */ const void *fsp_get_hob_list(void); +/* + * Hand-off-block utilities which do not depend on CBMEM, but need to be passed + * the HOB list explicitly. + */ +void fsp_find_range_hob(struct range_entry *re, const void *hob_list, + const uint8_t uuid[16]); + #if IS_ENABLED(CONFIG_DISPLAY_HOBS) /* Display HOBs API */ void fsp_display_hobs(const struct hob_header *hob_list_ptr); @@ -104,6 +112,21 @@ static inline __attribute__((always_inline)) void fsp_display_mtrrs(void) } #endif /* CONFIG_DISPLAY_MTRRS */ +#if IS_ENABLED(CONFIG_VERIFY_HOBS) +/* Verify HOBs API */ +void fsp_verify_hobs(const struct hob_header *hob_list_ptr); + +/* Verify HOBs utility functions */ +struct range_entry fsp_find_bootloader_tolum(const void *hob_list); + +#else /* CONFIG_VERIFY_HOBS */ +/* Remove HOB display code from the image */ +static inline __attribute__((always_inline)) void fsp_verify_hobs( + const struct hob_header *hob_list_ptr) +{ +} +#endif /* CONFIG_VERIFY_HOBS */ + /*----------- * UPD *----------- @@ -173,8 +196,13 @@ static inline __attribute__((always_inline)) void fsp_debug_memory_init( if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); - /* Display the HOBs */ + /* Verify that the HOB list pointer was set */ + if (hob_list_ptr == NULL) + die("ERROR - HOB list pointer was not returned!\n"); + + /* Display and verify the HOBs */ fsp_display_hobs(hob_list_ptr); + fsp_verify_hobs(hob_list_ptr); /* Display the MTRRs */ fsp_display_mtrrs(); diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index c84a017..0877387 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -18,7 +18,6 @@ #include <fsp/api.h> #include <fsp/debug.h> #include <fsp/info_header.h> -#include <memrange.h> /* * Hand-off-block handling functions that depend on CBMEM, and thus can only @@ -32,7 +31,7 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); * Hand-off-block utilities which do not depend on CBMEM, but need to be passed * the HOB list explicitly. */ -void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list); +struct range_entry fsp_find_reserved_memory(const void *hob_list); const struct hob_resource *fsp_hob_header_to_resource( const struct hob_header *hob); const struct hob_header *fsp_next_hob(const struct hob_header *parent); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 4921e88..78e3d81 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -67,7 +67,7 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, struct range_entry fsp_mem; struct romstage_handoff *handoff; - fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); + fsp_mem = fsp_find_reserved_memory(hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */ if (!s3wake) { @@ -188,7 +188,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, enum fsp_status status; fsp_memory_init_fn fsp_raminit; struct FSPM_UPD fspm_upd, *upd; - void *hob_list_ptr; + void *hob_list_ptr = NULL; struct FSPM_ARCH_UPD *arch_upd; post_code(0x34);

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: FSP driver handles all FSP errors
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15853 -gerrit commit 99de3054cbf3b2d941dd2d63fad623fbac2e91b3 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:18:52 2016 -0700 drivers/intel/fsp2_0: FSP driver handles all FSP errors Move all FSP error handling into the FSP 2.0 driver. This removes the need to implement error handling within the SOC code. TEST=Build and run on Galileo Gen2 Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 6 +++--- src/drivers/intel/fsp2_0/memory_init.c | 29 ++++++++++++----------------- src/drivers/intel/fsp2_0/notify.c | 11 +++++++---- src/drivers/intel/fsp2_0/silicon_init.c | 27 ++++++++++++--------------- src/soc/intel/apollolake/chip.c | 10 +++------- src/soc/intel/apollolake/romstage.c | 6 +----- 6 files changed, 38 insertions(+), 51 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index bc55c50..1348ead 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -60,9 +60,9 @@ enum fsp_notify_phase { /* Main FSP stages */ -enum fsp_status fsp_memory_init(bool s3wake); -enum fsp_status fsp_silicon_init(void); -enum fsp_status fsp_notify(enum fsp_notify_phase phase); +void fsp_memory_init(bool s3wake); +void fsp_silicon_init(void); +void fsp_notify(enum fsp_notify_phase phase); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 78e3d81..0677e74 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -61,7 +61,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) */ #define MRC_DEAD_VERSION (0xdeaddead) -static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, +static void do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; @@ -85,7 +85,7 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) - die("Failed to accommodate FSP reserved memory request"); + die("Failed to accommodate FSP reserved memory request!\n"); /* Now that CBMEM is up, save the list so ramstage can use it */ fsp_save_hob_list(hob_list_ptr); @@ -101,8 +101,6 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, handoff->s3_resume = s3wake; else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - - return FSP_SUCCESS; } static void fsp_fill_mrc_cache(struct FSPM_ARCH_UPD *arch_upd, bool s3wake, @@ -182,7 +180,7 @@ static enum cb_err fsp_fill_common_arch_params(struct FSPM_ARCH_UPD *arch_upd, return CB_SUCCESS; } -static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, +static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, const struct memranges *memmap) { enum fsp_status status; @@ -196,8 +194,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) { - printk(BIOS_ERR, "Invalid FSPM signature\n"); - return FSP_INCOMPATIBLE_VERSION; + die("Invalid FSPM signature!\n"); } /* Copy the default values from the UPD area */ @@ -211,7 +208,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, hdr->fsp_revision, memmap) != CB_SUCCESS) - return FSP_NOT_FOUND; + die("FSPM_ARCH_UPD not found!\n"); /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd); @@ -229,13 +226,12 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, fsp_debug_memory_init(status, hob_list_ptr); - /* Handle any resets requested by FSPM. */ + /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); - if (status != FSP_SUCCESS) - return status; + die("FspMemoryInit returned an error!\n"); - return do_fsp_post_memory_init(hob_list_ptr, s3wake, hdr->fsp_revision); + do_fsp_post_memory_init(hob_list_ptr, s3wake, hdr->fsp_revision); } /* Load the binary into the memory specified by the info header. */ @@ -286,7 +282,7 @@ static enum cb_err load_fspm_xip(struct fsp_header *hdr, return CB_SUCCESS; } -enum fsp_status fsp_memory_init(bool s3wake) +void fsp_memory_init(bool s3wake) { struct fsp_header hdr; enum cb_err status; @@ -298,7 +294,7 @@ enum fsp_status fsp_memory_init(bool s3wake) if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); - return FSP_NOT_FOUND; + die("FSPM not available!\n"); } cbfs_file_data(&file_data, &file_desc); @@ -315,12 +311,11 @@ enum fsp_status fsp_memory_init(bool s3wake) status = load_fspm_xip(&hdr, &file_data); if (status != CB_SUCCESS) { - printk(BIOS_ERR, "Loading FSPM failed.\n"); - return FSP_NOT_FOUND; + die("Loading FSPM failed!\n"); } /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); - return do_fsp_memory_init(&hdr, s3wake, &memmap); + do_fsp_memory_init(&hdr, s3wake, &memmap); } diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 139e172..b002cf8 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -17,14 +17,14 @@ #include <string.h> #include <timestamp.h> -enum fsp_status fsp_notify(enum fsp_notify_phase phase) +void fsp_notify(enum fsp_notify_phase phase) { enum fsp_status ret; fsp_notify_fn fspnotify; struct fsp_notify_params notify_params = { .phase = phase }; - if (!fsps_hdr.silicon_init_entry_offset) - return FSP_NOT_FOUND; + if (!fsps_hdr.notify_phase_entry_offset) + die("Notify_phase_entry_offset is zero!\n"); fspnotify = (void*) (fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); @@ -49,5 +49,8 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase) } fsp_debug_notify(ret); - return ret; + /* Handle any errors returned by FspNotify */ + fsp_handle_reset(ret); + if (ret != FSP_SUCCESS) + die("FspNotify returned an error!\n"); } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index b9fea66..c539db6 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -23,7 +23,7 @@ struct fsp_header fsps_hdr; -static enum fsp_status do_silicon_init(struct fsp_header *hdr) +static void do_silicon_init(struct fsp_header *hdr) { struct FSPS_UPD upd, *supd; fsp_silicon_init_fn silicon_init; @@ -32,8 +32,7 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) { - printk(BIOS_ERR, "Invalid FSPS signature\n"); - return FSP_INCOMPATIBLE_VERSION; + die("Invalid FSPS signature\n"); } memcpy(&upd, supd, sizeof(upd)); @@ -54,13 +53,13 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) fsp_debug_silicon_init(status); - /* Handle any resets requested by FSPS. */ + /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); - - return status; + if (status != FSP_SUCCESS) + die("FspSiliconINit returned an error!\n"); } -enum fsp_status fsp_silicon_init(void) +void fsp_silicon_init(void) { struct fsp_header *hdr = &fsps_hdr; struct cbfsf file_desc; @@ -71,7 +70,7 @@ enum fsp_status fsp_silicon_init(void) if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); - return FSP_NOT_FOUND; + die("FSPS not available!\n"); } cbfs_file_data(&rdev, &file_desc); @@ -81,26 +80,24 @@ enum fsp_status fsp_silicon_init(void) dest = cbmem_add(CBMEM_ID_REFCODE, size); if (dest == NULL) { - printk(BIOS_ERR, "Could not add FSPS to CBMEM.\n"); - return FSP_NOT_FOUND; + die("Could not add FSPS to CBMEM!\n"); } if (rdev_readat(&rdev, dest, 0, size) < 0) - return FSP_NOT_FOUND; + die("Failed to read FSPS!\n"); if (fsp_component_relocate((uintptr_t)dest, dest, size) < 0) { - printk(BIOS_ERR, "Unable to relocate FSPS.\n"); - return FSP_NOT_FOUND; + die("Unable to relocate FSPS!\n"); } /* Create new region device in memory after relocation. */ rdev_chain(&rdev, &addrspace_32bit.rdev, (uintptr_t)dest, size); if (fsp_validate_component(hdr, &rdev) != CB_SUCCESS) - return FSP_NOT_FOUND; + die("Invalid FSPS header!\n"); /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); - return do_silicon_init(hdr); + do_silicon_init(hdr); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 10b71fb..812f663 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -200,8 +200,7 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - if (fsp_silicon_init() != FSP_SUCCESS) - die("FSP silicon init failed. Giving up."); + fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); @@ -411,12 +410,9 @@ static void fsp_notify_dummy(void *arg) { enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; - enum fsp_status ret; - if ((ret = fsp_notify(ph)) != FSP_SUCCESS) { - printk(BIOS_CRIT, "FspNotify failed, ret = %x!\n", ret); - fsp_handle_reset(ret); - } + fsp_notify(ph); + /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ if (ph == READY_TO_BOOT) { fsp_notify_dummy((void *)END_OF_FIRMWARE); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index da7fcf1..8f17fdd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -114,11 +114,7 @@ asmlinkage void car_stage_entry(void) console_init(); s3wake = fill_power_state(ps) == ACPI_S3; - - if (fsp_memory_init(s3wake) != FSP_SUCCESS) { - die("FSP memory init failed. Giving up."); - } - + fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n");

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Handle FspNotify calls
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15855 -gerrit commit 833e210ea76023fef2d777f79b8bb99cbd7c3670 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:59:06 2016 -0700 drivers/intel/fsp2_0: Handle FspNotify calls Other SOC platforms need to handle the FspNotify calls in the same way as Apollo Lake. Migrate the FspNotify calls into the FSP 2.0 driver. Provide a platform callback to handle anything else that needs to be done after the FspNotify call. TEST=Build and run on Galileo Gen2 Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 3 +++ src/drivers/intel/fsp2_0/notify.c | 25 +++++++++++++++++++++++++ src/soc/intel/apollolake/chip.c | 21 +++------------------ 3 files changed, 31 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 1348ead..5a647a2 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -68,6 +68,9 @@ void fsp_notify(enum fsp_notify_phase phase); void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd); +/* Callback after processing FSP notify */ +void platform_fsp_notify_status(enum fsp_notify_phase phase); + /* * # DOCUMENTATION: * diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index b002cf8..330c666 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -11,6 +11,7 @@ */ #include <arch/cpu.h> +#include <bootstate.h> #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> @@ -53,4 +54,28 @@ void fsp_notify(enum fsp_notify_phase phase) fsp_handle_reset(ret); if (ret != FSP_SUCCESS) die("FspNotify returned an error!\n"); + + /* Allow the platform to run something after FspNotify */ + platform_fsp_notify_status(phase); +} + +static void fsp_notify_dummy(void *arg) +{ + enum fsp_notify_phase phase = (uint32_t)arg; + + fsp_notify(phase); + if (phase == READY_TO_BOOT) + fsp_notify(END_OF_FIRMWARE); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, + (void *) AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, + (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, + (void *) READY_TO_BOOT); + +__attribute__((weak)) void platform_fsp_notify_status( + enum fsp_notify_phase phase) +{ } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 812f663..345d7c4 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -406,28 +406,13 @@ struct chip_operations soc_intel_apollolake_ops = { .final = &soc_final }; -static void fsp_notify_dummy(void *arg) +void platform_fsp_notify_status(enum fsp_notify_phase phase) { - - enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; - - fsp_notify(ph); - - /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ - if (ph == READY_TO_BOOT) { - fsp_notify_dummy((void *)END_OF_FIRMWARE); - /* Hide the P2SB device to align with previous behavior. */ + /* Hide the P2SB device to align with previous behavior. */ + if (phase == END_OF_FIRMWARE) p2sb_hide(); - } } -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, - (void *) AFTER_PCI_ENUM); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, - (void *) READY_TO_BOOT); -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, - (void *) READY_TO_BOOT); - /* * spi_init() needs to run unconditionally on every boot (including resume) to * allow write protect to be disabled for eventlog and nvram updates. This needs

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add UPD display support
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15847 -gerrit commit 10a59c10215eb0c1bafda56678d69e1c38dbfc37 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 09:48:49 2016 -0700 drivers/intel/fsp2_0: Add UPD display support Add UPD display support: * Add a Kconfig value to enable UPD value display * Add a routine to display a UPD value * Add a call before MemoryInit to display the UPD parameters * Add a routine to display the architectural parameters for MemoryInit * Add a weak routine to display the other UPD parameters for MemoryInit * Add a call before SiliconInit to display the UPD parameters * Add a weak routine to display the UPD parameters for SiliconInit TEST=Build and run on Galileo Gen2. Change-Id: I35fb8410c0bccf217b32af4b8bbe5ad6671f81f6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 +++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/include/fsp/debug.h | 41 +++++++++++++++ src/drivers/intel/fsp2_0/upd_display.c | 76 ++++++++++++++++++++++++++++ 4 files changed, 126 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 7f4bbee..32dbb59 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,13 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP. +config DISPLAY_UPD_DATA + bool "Display UPD data" + default n + help + Display the user specified product data prior to memory + initialization. + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 4f36664..91e86b5 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-y += util.c romstage-y += memory_init.c @@ -23,6 +24,7 @@ ramstage-y += graphics.c ramstage-y += hand_off_block.c ramstage-y += notify.c ramstage-y += silicon_init.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 976e0fe..7c48886 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -45,6 +45,41 @@ static inline __attribute__((always_inline)) void fsp_display_mtrrs(void) #endif /* CONFIG_DISPLAY_MTRRS */ /*----------- + * UPD + *----------- + */ +#if IS_ENABLED(CONFIG_DISPLAY_UPD_DATA) + +/* Display UPD API */ +void fspm_display_upd_values(const struct FSPM_UPD *old, const struct FSPM_UPD *new); + +/* Callbacks for displaying UPD parameters - place in a separate file + * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. + */ +void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd); +void soc_display_fsps_upd_params(const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd); + +/* Display UPD utility functions */ +void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new); + +#else /* CONFIG_DISPLAY_UPD_DATA */ +/* Remove UPD display code from the image */ +static inline __attribute__((always_inline)) void fspm_display_upd_values( + const struct FSPM_UPD *old, const struct FSPM_UPD *new) +{ +} + +static inline __attribute__((always_inline)) void soc_display_fsps_upd_params( + const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd) +{ +} +#endif /* CONFIG_DISPLAY_UPD_DATA */ + +/*----------- * MemoryInit *----------- */ @@ -60,6 +95,9 @@ static inline __attribute__((always_inline)) void fsp_debug_before_memory_init( /* Display the MTRRs */ fsp_display_mtrrs(); + /* Display the UPD values */ + fspm_display_upd_values(fspm_old_upd, fspm_new_upd); + /* Display the call entry point and paramters */ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", @@ -90,6 +128,9 @@ static inline __attribute__((always_inline)) void fsp_debug_before_silicon_init( fsp_silicon_init_fn silicon_init, const struct FSPS_UPD *fsps_old_upd, const struct FSPS_UPD *fsps_new_upd) { + /* Display the UPD values */ + soc_display_fsps_upd_params(fsps_old_upd, fsps_new_upd); + /* Display the call to FSP SiliconInit */ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init); diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c new file mode 100644 index 0000000..5db6268 --- /dev/null +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> + +void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new) +{ + size *= 2; + if (old == new) { + printk(BIOS_SPEW, " 0x%0*llx: %s\n", size, new, name); + } else { + printk(BIOS_SPEW, " 0x%0*llx --> 0x%0*llx: %s\n", size, old, + size, new, name); + } +} + +static void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old, + const struct FSPM_ARCH_UPD *new) +{ + /* Display the architectural parameters for MemoryInit */ + printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n", + new); + fsp_display_upd_value("Revision", sizeof(old->Revision), + old->Revision, new->Revision); + fsp_display_upd_value("NvsBufferPtr", sizeof(old->NvsBufferPtr), + (uint64_t)(uintptr_t)old->NvsBufferPtr, + (uint64_t)(uintptr_t)new->NvsBufferPtr); + fsp_display_upd_value("StackBase", sizeof(old->StackBase), + (uint64_t)(uintptr_t)old->StackBase, + (uint64_t)(uintptr_t)new->StackBase); + fsp_display_upd_value("StackSize", sizeof(old->StackSize), + old->StackSize, new->StackSize); + fsp_display_upd_value("BootLoaderTolumSize", + sizeof(old->BootLoaderTolumSize), + old->BootLoaderTolumSize, new->BootLoaderTolumSize); + fsp_display_upd_value("BootMode", sizeof(old->BootMode), + old->BootMode, new->BootMode); +} + +/* Display the UPD parameters for MemoryInit */ +__attribute__((weak)) void soc_display_fspm_upd_params( + const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd) +{ + printk(BIOS_DEBUG, "UPD values for MemoryInit:\n"); + hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); +} + +void fspm_display_upd_values(const struct FSPM_UPD *old, + const struct FSPM_UPD *new) +{ + /* Display the UPD data */ + fspm_display_arch_params(&old->FspmArchUpd, &new->FspmArchUpd); + soc_display_fspm_upd_params(old, new); +} + +/* Display the UPD parameters for SiliconInit */ +__attribute__((weak)) void soc_display_fsps_upd_params( + const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd) +{ + printk(BIOS_DEBUG, "UPD values for SiliconInit:\n"); + hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); +}

1 0

Patch set updated for coreboot: arch/riscv: Add include/arch/barrier.h
by Jonathan Neuschäfer 31 Jul '16

31 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15830 -gerrit commit e352411b7d3dc4861551671ae77218431f114e1e Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Tue Jul 26 01:54:34 2016 +0200 arch/riscv: Add include/arch/barrier.h mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/include/arch/barrier.h | 39 ++++++++++++++++++++++++ src/arch/riscv/include/atomic.h | 1 - src/arch/riscv/virtual_memory.c | 5 +-- src/mainboard/emulation/qemu-riscv/qemu_util.c | 5 +-- src/mainboard/emulation/spike-riscv/spike_util.c | 1 + 5 files changed, 46 insertions(+), 5 deletions(-) diff --git a/src/arch/riscv/include/arch/barrier.h b/src/arch/riscv/include/arch/barrier.h new file mode 100644 index 0000000..257e2a2 --- /dev/null +++ b/src/arch/riscv/include/arch/barrier.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef __ARCH_BARRIER_H_ +#define __ARCH_BARRIER_H__ + +static inline void mb(void) { asm volatile("fence"); } +static inline void rmb(void) { asm volatile("fence"); } +static inline void wmb(void) { asm volatile("fence"); } + +#endif /* __ARCH_BARRIER_H__ */ diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h index 7141d7b..333cc6e 100644 --- a/src/arch/riscv/include/atomic.h +++ b/src/arch/riscv/include/atomic.h @@ -36,7 +36,6 @@ typedef struct { int lock; } spinlock_t; #define SPINLOCK_INIT {0} -#define mb() __sync_synchronize() #define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val) #define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr)) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index a7a81fb..bfdd84d 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -14,11 +14,12 @@ * GNU General Public License for more details. */ -#include <vm.h> +#include <arch/barrier.h> #include <arch/encoding.h> #include <atomic.h> -#include <stdint.h> #include <console/console.h> +#include <stdint.h> +#include <vm.h> pte_t* root_page_table; diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c index fca7d56..3c2941c 100644 --- a/src/mainboard/emulation/qemu-riscv/qemu_util.c +++ b/src/mainboard/emulation/qemu-riscv/qemu_util.c @@ -25,11 +25,12 @@ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. */ -#include <spike_util.h> +#include <arch/barrier.h> #include <arch/errno.h> #include <atomic.h> -#include <string.h> #include <console/console.h> +#include <spike_util.h> +#include <string.h> uintptr_t translate_address(uintptr_t vAddr) { // TODO: implement the page table translation algorithm diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index 358cb44..f0f5301 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -26,6 +26,7 @@ */ #include <spike_util.h> +#include <arch/barrier.h> #include <arch/errno.h> #include <atomic.h> #include <string.h>

1 0

Patch merged into coreboot/master: intel/wifi: Include conditionally in the build
by gerrit＠coreboot.org 31 Jul '16

31 Jul '16

the following patch was just integrated into master: commit 828e73e0b69896c769e2b9baf6a22c22eafd3734 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 28 17:26:39 2016 +0300 intel/wifi: Include conditionally in the build Keep this enabled by default as most x86 platforms could have PCI-e slots equipped with one of these Intel WiFi adapters. The Kconfig entries under google boards had no function previously, the variable was never referenced. Change-Id: I728ce3fd83d51d4e5e32b848a2079c5fcee29349 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/15931 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15931 for details. -gerrit

1 0

Patch set updated for coreboot: src/include: Capitalize CPU, RAM and ROM
by HAOUAS Elyes 30 Jul '16

30 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15942 -gerrit commit 76d542221dbb2cb8f199f1b5b9520f91c896fda4 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 21:25:21 2016 +0200 src/include: Capitalize CPU, RAM and ROM Change-Id: Id40c1bf868820c77ea20146d19c6d552c2f970c4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/include/cbfs.h | 2 +- src/include/console/post_codes.h | 6 +++--- src/include/cpu/x86/cache.h | 2 +- src/include/cpu/x86/mp.h | 12 ++++++------ src/include/cpu/x86/msr.h | 2 +- src/include/cpu/x86/mtrr.h | 2 +- src/include/cpu/x86/smm.h | 8 ++++---- src/include/gic.h | 2 +- src/include/rmodule.h | 2 +- 9 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d19218..6d9dd42 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -23,7 +23,7 @@ * Perform CBFS operations on the boot device. * ***********************************************/ -/* Return mapping of option rom found in boot device. NULL on error. */ +/* Return mapping of option ROM found in boot device. NULL on error. */ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device); /* Load stage by name into memory. Returns entry address on success. NULL on * failure. */ diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 8e47905..c7722e5 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -82,14 +82,14 @@ #define POST_ENTRY_C_START 0x13 /** - * \brief Pre call to ram stage main() + * \brief Pre call to RAM stage main() * - * POSTed right before ram stage main() is called from c_start.S + * POSTed right before RAM stage main() is called from c_start.S */ #define POST_PRE_HARDWAREMAIN 0x79 /** - * \brief Entry into coreboot in ram stage main() + * \brief Entry into coreboot in RAM stage main() * * This is the first call in hardwaremain.c. If this code is POSTed, then * ramstage has successfully loaded and started executing. diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 9c1af29..2c8c44b 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -52,7 +52,7 @@ static inline void invd(void) /* The following functions require the always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as - * ram, the cache as ram stack can no longer be used. Called + * RAM, the cache as RAM stack can no longer be used. Called * functions must be inlined to avoid stack usage. Also, the * compiler must keep local variables register based and not * allocated them from the stack. With gcc 4.5.0, some functions diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 9742df0..cea3139 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -59,9 +59,9 @@ struct mp_ops { void (*get_microcode_info)(const void **microcode, int *parallel); /* * Optionally provide a function which adjusts the APIC id - * map to cpu number. By default the cpu number and APIC id - * are 1:1. To change the APIC id for a given cpu return the - * new APIC id. It's called for each cpu as indicated by + * map to CPU number. By default the CPU number and APIC id + * are 1:1. To change the APIC id for a given CPU return the + * new APIC id. It's called for each CPU as indicated by * get_cpu_count(). */ int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id); @@ -78,7 +78,7 @@ struct mp_ops { void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm); /* * Optionally provide a callback prior to the APs starting SMM - * relocation or cpu driver initialization. However, note that + * relocation or CPU driver initialization. However, note that * this callback is called after SMM handlers have been loaded. */ void (*pre_mp_smm_init)(void); @@ -88,11 +88,11 @@ struct mp_ops { */ void (*per_cpu_smm_trigger)(void); /* - * This function is called while each cpu is in the SMM relocation + * This function is called while each CPU is in the SMM relocation * handler. Its primary purpose is to adjust the SMBASE for the * permanent handler. The parameters passed are the current cpu * running the relocation handler, current SMBASE of relocation handler, - * and the pre-calculated staggered cpu SMBASE address of the permanent + * and the pre-calculated staggered CPU SMBASE address of the permanent * SMM handler. */ void (*relocation_handler)(int cpu, uintptr_t curr_smbase, diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index d644edd..db35ef1 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -48,7 +48,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, /* The following functions require the always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as - * ram, the cache as ram stack can no longer be used. Called + * RAM, the cache as RAM stack can no longer be used. Called * functions must be inlined to avoid stack usage. Also, the * compiler must keep local variables register based and not * allocated them from the stack. With gcc 4.5.0, some functions diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index d09c77e..f32bece 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -91,7 +91,7 @@ int get_free_var_mtrr(void); (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) -/* At the end of romstage, low ram 0..CACHE_TM_RAMTOP may be set +/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. * Note MTRR boundaries, must be power of two. */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 2b13f8c..c1051ad 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -491,8 +491,8 @@ u16 smm_get_pmbase(void); struct smm_runtime { u32 smbase; u32 save_state_size; - /* The apic_id_to_cpu provides a mapping from APIC id to cpu number. - * The cpu number is indicated by the index into the array by matching + /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. + * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader * initializes this array with a 1:1 mapping. If the APIC ids are not * contiguous like the 1:1 mapping it is up to the caller of the stub @@ -525,7 +525,7 @@ void *smm_get_save_state(int cpu); /* The smm_loader_params structure provides direction to the SMM loader: * - stack_top - optional external stack provided to loader. It must be at * least per_cpu_stack_size * num_concurrent_stacks in size. - * - per_cpu_stack_size - stack size per cpu for smm modules. + * - per_cpu_stack_size - stack size per CPU for smm modules. * - num_concurrent_stacks - number of concurrent cpus in handler needing stack * optional for setting up relocation handler. * - per_cpu_save_state_size - the smm save state size per cpu @@ -537,7 +537,7 @@ void *smm_get_save_state(int cpu); * the address of the module's parameters (if present). * - runtime - this field is a result only. The SMM runtime location is filled * into this field so the code doing the loading can manipulate the - * runtime's assumptions. e.g. updating the apic id to cpu map to + * runtime's assumptions. e.g. updating the apic id to CPU map to * handle sparse apic id space. */ struct smm_loader_params { diff --git a/src/include/gic.h b/src/include/gic.h index 1ac1eab..f7339a4 100644 --- a/src/include/gic.h +++ b/src/include/gic.h @@ -26,7 +26,7 @@ void gic_enable(void); /* Return a pointer to the base of the GIC distributor mmio region. */ void *gicd_base(void); -/* Return a pointer to the base of the GIC cpu mmio region. */ +/* Return a pointer to the base of the GIC CPU mmio region. */ void *gicc_base(void); #else /* CONFIG_GIC */ diff --git a/src/include/rmodule.h b/src/include/rmodule.h index c0c062c..c5de9c3 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -40,7 +40,7 @@ int rmodule_load_alignment(const struct rmodule *m); /* rmodule_calc_region() calculates the region size, offset to place an * rmodule in memory, and load address offset based off of a region allocator * with an alignment of region_alignment. This function helps place an rmodule - * in the same location in ram it will run from. The offset to place the + * in the same location in RAM it will run from. The offset to place the * rmodule into the region allocated of size region_size is returned. The * load_offset is the address to load and relocate the rmodule. * region_alignment must be a power of 2. */

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Patch merged into coreboot/master: bayou: delete pbuilder utility
by gerrit＠coreboot.org 30 Jul '16

30 Jul '16

the following patch was just integrated into master: commit 783d0c146f6a2c3710ce7cd9ebe2aabb5825d854 Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Jul 28 13:59:44 2016 +0200 bayou: delete pbuilder utility Delete pbuilder since it is not needed anymore. Change-Id: I685547e9692944b89521864fc3bee4e9a2f1139f Signed-off-by: Antonello Dettori <dev(a)dettori.io> Reviewed-on: https://review.coreboot.org/15955 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Omar Pakker Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/15955 for details. -gerrit

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coreboot-gerrit July 2016