coreboot-gerrit July 2016

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Patch set updated for coreboot: superio/nuvoton: Add Nuvoton NCT6791D
by Omar Pakker 30 Jul '16

30 Jul '16

Omar Pakker just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15967 -gerrit commit e2e2775c3c53312c8464945fb91cf23df8aad0b5 Author: Omar Pakker <omarpakker+coreboot(a)gmail.com> Date: Fri Jul 29 19:05:33 2016 +0200 superio/nuvoton: Add Nuvoton NCT6791D This adds support for Nuvoton NCT6791D Super I/O chips. Makes use of the common Nuvoton early_serial.c. Based on the Datasheet supplied by Nuvoton. Datasheet Version: January 8th, 2016 Revision 1.11 Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40 Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com> --- src/superio/nuvoton/Kconfig | 4 ++ src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct6791d/Makefile.inc | 16 +++++ src/superio/nuvoton/nct6791d/nct6791d.h | 58 ++++++++++++++++++ src/superio/nuvoton/nct6791d/superio.c | 99 +++++++++++++++++++++++++++++++ 5 files changed, 178 insertions(+) diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index ce7db26..4067a41 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -32,3 +32,7 @@ config SUPERIO_NUVOTON_NCT5572D config SUPERIO_NUVOTON_NCT6779D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + +config SUPERIO_NUVOTON_NCT6791D + bool + select SUPERIO_NUVOTON_COMMON_ROMSTAGE diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index eb3dd5d..94cc6b7 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -20,3 +20,4 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d diff --git a/src/superio/nuvoton/nct6791d/Makefile.inc b/src/superio/nuvoton/nct6791d/Makefile.inc new file mode 100644 index 0000000..db5c620 --- /dev/null +++ b/src/superio/nuvoton/nct6791d/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += superio.c diff --git a/src/superio/nuvoton/nct6791d/nct6791d.h b/src/superio/nuvoton/nct6791d/nct6791d.h new file mode 100644 index 0000000..69855ac --- /dev/null +++ b/src/superio/nuvoton/nct6791d/nct6791d.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NUVOTON_NCT6791D_H +#define SUPERIO_NUVOTON_NCT6791D_H + +/* Logical Device Numbers (LDN). */ +#define NCT6791D_PP 0x01 /* Parallel port */ +#define NCT6791D_SP1 0x02 /* UART A */ +#define NCT6791D_SP2 0x03 /* UART B, IR */ +#define NCT6791D_KBC 0x05 /* Keyboard Controller */ +#define NCT6791D_CIR 0x06 /* Consumer IR */ +#define NCT6791D_GPIO678 0x07 /* GPIO 6, 7 & 8 */ +#define NCT6791D_WDT1_WDTMEM_GPIO01 0x08 /* WDT1, WDT_MEM, GPIO 0 & 1 */ +#define NCT6791D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */ +#define NCT6791D_ACPI 0x0A /* ACPI */ +#define NCT6791D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */ +#define NCT6791D_BCLK_WDT2_WDTMEM 0x0D /* BCLK, WDT2, WDT_MEM */ +#define NCT6791D_CIRWUP 0x0E /* CIR Wake-Up */ +#define NCT6791D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */ +#define NCT6791D_PORT80 0x14 /* Port 80 UART */ +#define NCT6791D_DS 0x16 /* Deep Sleep */ + +/* Virtual LDNs */ +#define NCT6791D_WDT1 ((0 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_WDTMEM ((4 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_GPIOBASE ((3 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_GPIO0 ((1 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_GPIO1 ((7 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01) +#define NCT6791D_GPIO2 ((0 << 8) | NCT6791D_GPIO2345) +#define NCT6791D_GPIO3 ((1 << 8) | NCT6791D_GPIO2345) +#define NCT6791D_GPIO4 ((2 << 8) | NCT6791D_GPIO2345) +#define NCT6791D_GPIO5 ((3 << 8) | NCT6791D_GPIO2345) +#define NCT6791D_GPIO6 ((0 << 8) | NCT6791D_GPIO678) +#define NCT6791D_GPIO7 ((1 << 8) | NCT6791D_GPIO678) +#define NCT6791D_GPIO8 ((2 << 8) | NCT6791D_GPIO678) +#define NCT6791D_DS5 ((0 << 8) | NCT6791D_DS) +#define NCT6791D_DS3 ((1 << 8) | NCT6791D_DS) +#define NCT6791D_PCHDSW ((3 << 8) | NCT6791D_DS) +#define NCT6791D_DSWWOPT ((4 << 8) | NCT6791D_DS) +#define NCT6791D_DS3OPT ((5 << 8) | NCT6791D_DS) +#define NCT6791D_DSDSS ((6 << 8) | NCT6791D_DS) +#define NCT6791D_DSPU ((7 << 8) | NCT6791D_DS) + +#endif /* SUPERIO_NUVOTON_NCT6791D_H */ diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c new file mode 100644 index 0000000..4d6ed38 --- /dev/null +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com> + * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct6791d.h" + + +static void nct6791d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case NCT6791D_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6791d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, NCT6791D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_SP1, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_SP2, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, NCT6791D_CIR, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_GPIO678}, + { &ops, NCT6791D_WDT1_WDTMEM_GPIO01}, + { &ops, NCT6791D_GPIO2345}, + { &ops, NCT6791D_ACPI}, + { &ops, NCT6791D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + {0x0ffe, 0}, {0x0ffe, 4}, }, + { &ops, NCT6791D_BCLK_WDT2_WDTMEM}, + { &ops, NCT6791D_CIRWUP, PNP_IO0 | PNP_IRQ0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_GPIO_PP_OD}, + { &ops, NCT6791D_PORT80}, + { &ops, NCT6791D_DS}, + { &ops, NCT6791D_WDT1}, + { &ops, NCT6791D_WDTMEM}, + { &ops, NCT6791D_GPIOBASE, PNP_IO0, + {0x0ff8, 0}, }, + { &ops, NCT6791D_GPIO0}, + { &ops, NCT6791D_GPIO1}, + { &ops, NCT6791D_GPIO2}, + { &ops, NCT6791D_GPIO3}, + { &ops, NCT6791D_GPIO4}, + { &ops, NCT6791D_GPIO5}, + { &ops, NCT6791D_GPIO6}, + { &ops, NCT6791D_GPIO7}, + { &ops, NCT6791D_GPIO8}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6791d_ops = { + CHIP_NAME("NUVOTON NCT6791D Super I/O") + .enable_dev = enable_dev, +}; +

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New patch to review for coreboot: sunw/ultra40m2: Fix handling non-existence of a device
by Patrick Georgi 30 Jul '16

30 Jul '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15982 -gerrit commit 862303606dd9aa751eeb177b8422fc0a603c2284 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jul 30 13:10:44 2016 +0200 sunw/ultra40m2: Fix handling non-existence of a device This probably never happens, but since we already test for the presence of the device, it makes no sense to try to configure it after its absense was determined. Change-Id: I9877dcd15819fb7949fa08a0954b05780df66316 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1347362 --- src/mainboard/sunw/ultra40m2/mainboard.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/sunw/ultra40m2/mainboard.c b/src/mainboard/sunw/ultra40m2/mainboard.c index 3e2bbf0..072e8a1 100644 --- a/src/mainboard/sunw/ultra40m2/mainboard.c +++ b/src/mainboard/sunw/ultra40m2/mainboard.c @@ -52,8 +52,10 @@ static void emc6d103_init(void) }; struct device * const dev = dev_find_slot_on_smbus(2, 0x2d); - if (dev == NULL) + if (dev == NULL) { printk(BIOS_WARNING, "EMC6D103 not found\n"); + return; + } printk(BIOS_SPEW, "%s EMC6D103 id: %x %x\n", __func__, smbus_read_byte(dev, 0x3e), smbus_read_byte(dev, 0x3f));

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New patch to review for coreboot: siemens/sitemp_g1p1: Fix typo
by Patrick Georgi 30 Jul '16

30 Jul '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15981 -gerrit commit 78b9e7c28ddc9b40053d13ef5856f3e749fcd885 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jul 30 13:08:32 2016 +0200 siemens/sitemp_g1p1: Fix typo Change-Id: I1c9af223d3598c4822905acce0cf9b1dca6ad1b6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1287066 --- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 606e68c..9570cd0 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -740,7 +740,7 @@ static void detect_hw_variant( device_t dev ) } // restore changes made for device 2 dev2->bus->secondary = secondary; - dev2->bus->secondary = subordinate; + dev2->bus->subordinate = subordinate; pci_write_config32(dev2, PCI_PRIMARY_BUS, pci_primary_bus); } break;

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Patch set updated for coreboot: bayou: Adapt to the coreboot-v4 era
by Antonello Dettori 30 Jul '16

30 Jul '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15956 -gerrit commit 23f54d06933c4e4cb09e463d1a17818a27f268c9 Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Jul 29 12:03:43 2016 +0200 bayou: Adapt to the coreboot-v4 era Adapt bayou to work in a coreboot-v4 environment: - Move from the original model (bundling every payload needed in a single file and linking it to bayou itself) to leaving the handling of the secondary payloads to the coreboot build system. - Use the newly introduced region_device api in libpayload. - Use the functions provided by modern libpayload instead of relying on local ones. - Update the SELF code to use struct cbfs_payload_segment. - Introduce bptbuilder, new tool to build a simple binary configuration from the xml configuration file given. The port is complete: it can detect and boot compatible payloads, it can handle chains and other configurations. Change-Id: I034c92f52995ff6c69121d482d04dc8ab596b82c Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/Makefile.inc | 17 +- payloads/bayou/Kconfig | 6 + payloads/bayou/Makefile | 97 +++++--- payloads/bayou/bayou.h | 11 +- payloads/bayou/bayou.ldscript | 87 ------- payloads/bayou/bayou.xml.example | 8 +- payloads/bayou/bptbuilder/Makefile | 32 +++ payloads/bayou/bptbuilder/bptbuilder.h | 70 ++++++ payloads/bayou/bptbuilder/config.c | 252 +++++++++++++++++++ payloads/bayou/bptbuilder/create.c | 117 +++++++++ payloads/bayou/bptbuilder/main.c | 79 ++++++ payloads/bayou/bptbuilder/show.c | 134 +++++++++++ payloads/bayou/cbfs_walker.c | 90 +++++++ payloads/bayou/config.c | 105 ++++---- payloads/bayou/lzma.c | 43 ---- payloads/bayou/lzmadecode.c | 398 ------------------------------- payloads/bayou/lzmadecode.h | 67 ------ payloads/bayou/main.c | 33 ++- payloads/bayou/menu.c | 3 +- payloads/bayou/nrv2b.c | 86 ------- payloads/bayou/payload.c | 6 +- payloads/bayou/self.c | 121 ++++------ payloads/bayou/self.h | 40 ---- payloads/libpayload/configs/config.bayou | 11 + 24 files changed, 1001 insertions(+), 912 deletions(-) diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc index 2d7edb6..cc8f0d6 100644 --- a/payloads/Makefile.inc +++ b/payloads/Makefile.inc @@ -13,6 +13,10 @@ ## GNU General Public License for more details. ## +ifeq ($(CONFIG_PAYLOAD_BAYOU),y) +PAYLOAD_CONFIG=payloads/bayou/build/bayou_payload_table +endif + cbfs-files-$(CONFIG_COREINFO_SECONDARY_PAYLOAD) += img/coreinfo img/coreinfo-file := payloads/coreinfo/build/coreinfo.elf img/coreinfo-type := payload @@ -21,7 +25,13 @@ cbfs-files-$(CONFIG_NVRAMCUI_SECONDARY_PAYLOAD) += img/nvramcui img/nvramcui-file := payloads/nvramcui/nvramcui.elf img/nvramcui-type := payload +cbfs-files-$(CONFIG_PAYLOAD_BAYOU) += bayou_payload_table +bayou_payload_table-file := $(PAYLOAD_CONFIG) +bayou_payload_table-type := raw + + PAYLOADS_LIST=\ +payloads/bayou \ payloads/coreinfo \ payloads/nvramcui \ payloads/libpayload \ @@ -38,6 +48,11 @@ payloads/coreinfo/build/coreinfo.elf coreinfo: payloads/nvramcui/nvramcui.elf nvramcui: $(MAKE) -C payloads/nvramcui +payloads/bayou/build/bayou.elf bayou: + $(MAKE) -C payloads/bayou + +payloads/bayou/build/bayou_payload_table: payloads/bayou/build/bayou.elf + clean-payloads: $(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) clean; ) @@ -47,4 +62,4 @@ distclean-payloads: print-repo-info-payloads: -$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; ) -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads nvramcui coreinfo +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads nvramcui coreinfo bayou diff --git a/payloads/bayou/Kconfig b/payloads/bayou/Kconfig new file mode 100644 index 0000000..2e4f317 --- /dev/null +++ b/payloads/bayou/Kconfig @@ -0,0 +1,6 @@ +if PAYLOAD_BAYOU + +config PAYLOAD_FILE + default "payloads/bayou/build/bayou.elf" + +endif diff --git a/payloads/bayou/Makefile b/payloads/bayou/Makefile index 7a4b08b..a3769a9 100644 --- a/payloads/bayou/Makefile +++ b/payloads/bayou/Makefile @@ -13,55 +13,80 @@ ## GNU General Public License for more details. ## -CONFIG_LZMA=y -CONFIG_NRV2B=y -CONFIG_BUILTIN_LAR=y - -PBUILDER_CONFIG=bayou.xml -BUILTIN_LAR=builtin.lar - export src := $(CURDIR) export obj := $(src)/build +export V := $(V) -LIBPAYLOAD_DIR := $(obj)/libpayload +# Make is silent per default, but 'make V=1' will show all compiler calls. +ifneq ($(V),1) +.SILENT: +endif -CC?=gcc -STRIP?=strip -OBJCOPY?=objcopy +BPTBUILDER_CONFIG=bayou.xml +BPTBUILDER_PATH := $(realpath ./bptbuilder) -FFLAGS-y= -FFLAGS-$(CONFIG_BUILTIN_LAR) += -DCONFIG_BUILTIN_LAR -FFLAGS-$(CONFIG_LZMA) += -DCONFIG_LZMA -FFLAGS-$(CONFIG_NRV2B) += -DCONFIG_NRV2B +LIBPAYLOAD_PATH := $(realpath ../libpayload) +LIBPAYLOAD_OBJ := $(obj)/libpayload +HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_OBJ)/lib/libpayload.a) +LIBPAYLOAD_CONFIG ?= configs/config.bayou +OBJCOPY ?= objcopy -OBJECTS-y=main.o payload.o config.o menu.o self.o -OBJECTS-$(CONFIG_LZMA) += lzma.o -OBJECTS-$(CONFIG_NRV2B) += nrv2b.o -OBJECTS-$(CONFIG_BUILTIN_LAR) += builtin-lar.o +OBJECTS-y = main.o menu.o payload.o config.o self.o cbfs_walker.o +OBJS = $(patsubst %,$(obj)/%,$(OBJECTS-y)) +TARGET = $(obj)/bayou.elf -CFLAGS= -Wall -Werror -Os $(FFLAGS-y) -LDFLAGS=-Wl,-T,bayou.ldscript -static -LIBGCC=$(shell $(CC) -m32 -print-libgcc-file-name) +# in addition to the dependency below, create the file if it doesn't exist +# to silence warnings about a file that would be generated anyway. +$(if $(wildcard .xcompile),,$(eval $(shell ../../util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) +.xcompile: ../../util/xcompile/xcompile + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null || rm -f $@.tmp $@ -LPCC=$(LIBPAYLOAD_DIR)/bin/lpgcc +CONFIG_COMPILER_GCC := y +ARCH-y := x86_32 -bayou.elf: $(OBJECTS-y) - $(LPCC) $(LDFLAGS) -m32 -o $@ $(OBJECTS-y) - @$(STRIP) $@ +include .xcompile -builtin-lar.o: $(BUILTIN_LAR) - @$(OBJCOPY) -I binary -B i386 -O elf32-i386 $(BUILTIN_LAR) $@ +CC := $(CC_$(ARCH-y)) +STRIP := $(STRIP_$(ARCH-y)) +OBJCOPY := $(OBJCOPY_$(ARCH-y)) -builtin.lar: util/pbuilder/pbuilder - @rm -f $@ - util/pbuilder/pbuilder -c $(PBUILDER_CONFIG) create $@ +LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc + +CFLAGS= -Wall -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) +LDFLAGS= -Wl,--build-id=none -static +LIBGCC=$(shell $(CC) -m32 -print-libgcc-file-name) -util/pbuilder/pbuilder: - $(MAKE) -C util/pbuilder +all: $(TARGET) -%.o: %.c +$(TARGET): libpayload $(OBJS) bptbuilder + $(LPCC) -o $@ $(OBJS) + $(OBJCOPY) --only-keep-debug $@ $(TARGET).debug + $(OBJCOPY) --strip-debug $@ + $(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ + +$(obj)/%.o: $(src)/%.c $(LPCC) $(CFLAGS) -c -o $@ $< +ifneq ($(strip $(HAVE_LIBPAYLOAD)),) +libpayload: + printf "Found Libpayload $(LIBPAYLOAD_OBJ).\n" +else +LPOPTS=obj="$(CURDIR)/lpbuild" DOTCONFIG="$(CURDIR)/lp.config" +libpayload: + printf "Building libpayload @ $(LIBPAYLOAD_PATH).\n" + $(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) distclean obj=$(obj)/libptmp + $(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) defconfig KBUILD_DEFCONFIG=$(LIBPAYLOAD_CONFIG) + $(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) install DESTDIR=$(obj) +endif + +bptbuilder: + printf "Building bptbuilder utility.\n" + $(MAKE) -C $(BPTBUILDER_PATH) all + $(BPTBUILDER_PATH)/bptbuilder -c $(src)/bayou.xml create $(obj)/bayou_payload_table + clean: - rm -f *.o bayou.elf builtin.lar - $(MAKE) -C util/pbuilder clean + rm -rf build lpbuild + $(MAKE) -C $(BPTBUILDER_PATH) clean + +.PHONY: $(PHONY) bptbuilder libpayload prepare clean distclean diff --git a/payloads/bayou/bayou.h b/payloads/bayou/bayou.h index 6bf10a5..4b262af 100644 --- a/payloads/bayou/bayou.h +++ b/payloads/bayou/bayou.h @@ -17,6 +17,7 @@ #define BAYOU_H_ #include <libpayload.h> +#include <cbfs.h> #define BAYOU_MAX_ENTRIES 10 @@ -53,7 +54,7 @@ enum bayou_params { struct payload { struct bpt_pentry pentry; - struct larstat stat; + struct cbfs_file stat; u8 *fptr; char *params[BAYOU_PARAMS_COUNT]; }; @@ -66,9 +67,12 @@ struct bayoucfg { extern struct bayoucfg bayoucfg; +extern char **cbfs_filenames; +extern int cbfs_filecount; + int verify_self(u8 *ptr); int self_get_params(u8 *fptr, u8 **params); -int self_load_and_run(struct payload *p, int *ret); +int self_load_and_run(struct payload *p); void menu(void); @@ -78,6 +82,7 @@ struct payload *payload_get_default(void); void run_payload_timeout(struct payload *p, int timeout); void payload_parse_params(struct payload *pload, u8 *params, int len); -int get_configuration(struct LAR *lar); +int get_configuration(struct region_device *cbfs); +int init_payload_filenames(void); #endif diff --git a/payloads/bayou/bayou.ldscript b/payloads/bayou/bayou.ldscript deleted file mode 100644 index 86baaec..0000000 --- a/payloads/bayou/bayou.ldscript +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -BASE_ADDRESS = 0x19000; - -OUTPUT_FORMAT(elf32-i386) -OUTPUT_ARCH(i386) - -ENTRY(_entry) - -HEAP_SIZE = 16384; -STACK_SIZE = 16384; - -SECTIONS -{ - . = BASE_ADDRESS; - - . = ALIGN(16); - _start = .; - - .text : { - *(.text._entry) - *(.text) - *(.text.*) - } - - .rodata : { - *(.rodata) - *(.rodata.*) - } - - .data : { - *(.data) - *(.data.*) - } - - _edata = .; - - .bss : { - *(.bss) - *(.bss.*) - *(COMMON) - - /* Stack and heap */ - - . = ALIGN(16); - _heap = .; - . += HEAP_SIZE; - . = ALIGN(16); - _eheap = .; - - _estack = .; - . += STACK_SIZE; - . = ALIGN(16); - _stack = .; - } - - _end = .; - - /DISCARD/ : { *(.comment) *(.note) *(.note.*) } -} diff --git a/payloads/bayou/bayou.xml.example b/payloads/bayou/bayou.xml.example index c52eaf2..c94281d 100644 --- a/payloads/bayou/bayou.xml.example +++ b/payloads/bayou/bayou.xml.example @@ -23,15 +23,15 @@ <payload type="chain" flags="default"> <title>Default Chain</title> <chain> - <file>payloads/passwd.elf</file> - <lar>passwd</lar> + <cbfs>img/coreinfo</cbfs> </chain> <chain> - <file>payloads/coreinfo.elf</file> + <cbfs>img/tint</cbfs> </chain> </payload> <payload type="chooser"> - <file>payloads/coreinfo.elf</file> + <title>coreinfo</title> + <cbfs>img/coreinfo</cbfs> </payload> </payloads> </BayouConfig> diff --git a/payloads/bayou/bptbuilder/Makefile b/payloads/bayou/bptbuilder/Makefile new file mode 100644 index 0000000..ca7df75 --- /dev/null +++ b/payloads/bayou/bptbuilder/Makefile @@ -0,0 +1,32 @@ +## +## This file is part of the bayou project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 as +## published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +BPTBUILDOBJS := config.o create.o show.o main.o +HOSTCXX=g++ +HOSTCC=gcc +HOSTCFLAGS=-Wall -Werror -Os + +all: bptbuilder + +bptbuilder: $(BPTBUILDOBJS) + $(HOSTCXX) -o $@ $(BPTBUILDOBJS) -lexpat + +%.o: %.c + $(HOSTCC) -c $(HOSTCFLAGS) -o $@ $< + +clean: + rm -f *.o bptbuilder + +.PHONY: $(PHONY) bptbuilder prepare clean distclean diff --git a/payloads/bayou/bptbuilder/bptbuilder.h b/payloads/bayou/bptbuilder/bptbuilder.h new file mode 100644 index 0000000..5027f4b --- /dev/null +++ b/payloads/bayou/bptbuilder/bptbuilder.h @@ -0,0 +1,70 @@ +/* + * This file is part of the bayou project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BPTBUILDER_H_ +#define BPTBUILDER_H_ + +#include <stdint.h> +#include <stdio.h> + +#define warn(fmt, args...) fprintf(stderr, fmt, ##args) +#define die(fmt, args...) \ + do { fprintf(stderr, fmt, ##args); exit(-1); } \ + while (0) + +struct pentry { + uint8_t index; + uint8_t parent; + uint8_t type; + uint8_t flags; + uint8_t title[64]; + char *pname; +}; + +struct config { + int timeout; + int n_entries; + struct pentry **entries; +}; + +struct bpt_config { + uint32_t id; + uint8_t timeout; + uint8_t entries; + uint8_t padding[10]; +}; + +struct bpt_pentry { + uint8_t index; + uint8_t parent; + uint8_t type; + uint8_t flags; + uint8_t title[64]; + uint8_t nlen; +}; + +#define BPT_ID 0x30545042 +#define BPT_TYPE_CHOOSER 0x01 +#define BPT_TYPE_CHAIN 0x02 +#define BPT_TYPE_SUBCHAIN 0x03 + +#define BPT_FLAG_DEFAULT 0x01 +#define BPT_FLAG_NOSHOW 0x02 + +int bptbuilder_show_binary(const char *input); +int create_binary_from_config(const char *input, const char *output); +void parseconfig(FILE *stream, struct config *config); + +#endif diff --git a/payloads/bayou/bptbuilder/config.c b/payloads/bayou/bptbuilder/config.c new file mode 100644 index 0000000..4e1a9e9 --- /dev/null +++ b/payloads/bayou/bptbuilder/config.c @@ -0,0 +1,252 @@ +/* + * This file is part of the bayou project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define _GNU_SOURCE + +#include <stdlib.h> +#include <string.h> +#include <expat.h> +#include <ctype.h> +#include "bptbuilder.h" + +#define STATE_NONE 0x00 +#define STATE_BAYOUCONFIG 0x01 +#define STATE_GLOBAL 0x02 +#define STATE_GLOBAL_TIMEOUT 0x03 +#define STATE_PAYLOADS 0x04 +#define STATE_PAYLOAD 0x05 +#define STATE_PAYLOAD_TITLE 0x06 +#define STATE_PAYLOAD_CBFS 0x07 +#define STATE_PAYLOAD_CHAIN 0x08 +#define STATE_PAYLOAD_CHAIN_CBFS 0x09 + +static struct userdata { + struct config *config; + struct pentry *payload; + struct pentry *chain; + int state; +} userdata; + +static char buffer[8192]; + +static struct { + char *element; + int pstate; + int state; +} states[] = { + {"BayouConfig", STATE_NONE, STATE_BAYOUCONFIG}, + {"global", STATE_BAYOUCONFIG, STATE_GLOBAL}, + {"timeout", STATE_GLOBAL, STATE_GLOBAL_TIMEOUT}, + {"payloads", STATE_BAYOUCONFIG, STATE_PAYLOADS}, + {"payload", STATE_PAYLOADS, STATE_PAYLOAD}, + {"title", STATE_PAYLOAD, STATE_PAYLOAD_TITLE}, + {"cbfs", STATE_PAYLOAD, STATE_PAYLOAD_CBFS}, + {"chain", STATE_PAYLOAD, STATE_PAYLOAD_CHAIN}, + {"cbfs", STATE_PAYLOAD_CHAIN, STATE_PAYLOAD_CHAIN_CBFS}, + {NULL}, +}; + +static struct pentry *newPayload(struct config *config) +{ + struct pentry **tmp, *ret; + + tmp = realloc(config->entries, + (config->n_entries + 1) * sizeof(struct pentry *)); + + if (tmp == NULL) + return NULL; + + config->entries = tmp; + + ret = config->entries[config->n_entries] = calloc(sizeof(*ret), 1); + + if (ret == NULL) + return NULL; + + /* Yes, I want this to be ++config->n_entries (the index is 1 based). */ + ret->index = ++config->n_entries; + + return ret; +} + +static void parseFlags(struct pentry *entry, const char *flags) +{ + char *p = (char *)flags; + char *n; + + while (*p) { + n = strchr(p, ','); + + if (n) + *(n++) = 0; + + if (!strcmp(p, "default")) + entry->flags |= BPT_FLAG_DEFAULT; + else if (!strcmp(p, "nolist")) + entry->flags |= BPT_FLAG_NOSHOW; + else + warn("W: Unknown payload flag %s\n", p); + + if (!n) + break; + + for (p = n; *p && isspace(*p); p++) + ; + } +} + +static struct pentry *addPayload(struct config *config, const char **attr) +{ + struct pentry *ret = newPayload(config); + int i = 0; + + if (ret == NULL) + die("E: Could not allocate memory for a new payload\n"); + + while (attr[i] != NULL) { + if (!strcmp(attr[i], "type")) { + if (!strcmp(attr[i + 1], "chain")) + ret->type = BPT_TYPE_CHAIN; + else if (!strcmp(attr[i + 1], "chooser")) + ret->type = BPT_TYPE_CHOOSER; + else + die("E: Invalid payload type %s\n", + attr[i + 1]); + } else if (!strcmp(attr[i], "flags")) + parseFlags(ret, attr[i + 1]); + + i += 2; + } + + return ret; +} + +static struct pentry *addChain(struct config *config, struct pentry *parent) +{ + struct pentry *ret = newPayload(config); + + if (ret == NULL) + die("E: Could not allocate memory for a new payload\n"); + + ret->parent = parent->index; + ret->type = BPT_TYPE_SUBCHAIN; + + return ret; +} + +static void start(void *data, const char *el, const char **attr) +{ + int i; + struct userdata *d = (struct userdata *)data; + + for (i = 0; states[i].element != NULL; i++) { + if (d->state != states[i].pstate) + continue; + + if (!strcmp(el, states[i].element)) { + d->state = states[i].state; + break; + } + } + + if (states[i].element == NULL) + die("E: Unknown element %s\n", el); + + if (d->state == STATE_PAYLOAD) + d->payload = addPayload(d->config, attr); + + if (d->state == STATE_PAYLOAD_CHAIN) + d->chain = addChain(d->config, d->payload); +} + +static void data(void *data, const char *val, int len) +{ + struct userdata *d = (struct userdata *)data; + int l; + + switch (d->state) { + case STATE_GLOBAL_TIMEOUT: + d->config->timeout = atoi(val); + break; + case STATE_PAYLOAD_TITLE: + l = sizeof(d->payload->title) - 1 > len ? + len : sizeof(d->payload->title) - 1; + + strncpy((char *)d->payload->title, (char *)val, l); + d->payload->title[l] = '\0'; + break; + case STATE_PAYLOAD_CBFS: + d->payload->pname = strndup(val, len); + break; + case STATE_PAYLOAD_CHAIN_CBFS: + d->chain->pname = strndup(val, len); + break; + default: + break; + } +} + +static void end(void *data, const char *el) +{ + struct userdata *d = (struct userdata *)data; + int i; + + if (d->state == STATE_PAYLOAD_CHAIN) + d->chain = NULL; + + if (d->state == STATE_PAYLOAD) + d->payload = NULL; + + for (i = 0; states[i].element != NULL; i++) { + if (d->state != states[i].state) + continue; + + if (!strcmp(el, states[i].element)) { + d->state = states[i].pstate; + break; + } + } + + if (states[i].element == NULL) + die("E: Unable to find the reverse state for %s\n", el); +} + +void parseconfig(FILE *stream, struct config *config) +{ + XML_Parser p = XML_ParserCreate(NULL); + int eof = 0; + + if (p == NULL) + die("E: Could not create the parser\n"); + + XML_SetElementHandler(p, start, end); + XML_SetCharacterDataHandler(p, data); + + userdata.config = config; + + XML_SetUserData(p, &userdata); + + while (!eof) { + int len = fread(buffer, 1, 8192, stream); + + eof = feof(stream); + + if (ferror(stream)) + die("E: Error reading the stream\n"); + + if (!XML_Parse(p, buffer, len, eof)) + die("E: Error parsing the XML data\n"); + } +} diff --git a/payloads/bayou/bptbuilder/create.c b/payloads/bayou/bptbuilder/create.c new file mode 100644 index 0000000..110cbb0 --- /dev/null +++ b/payloads/bayou/bptbuilder/create.c @@ -0,0 +1,117 @@ +/* + * This file is part of the bayou project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <fcntl.h> +#include <libgen.h> +#include "bptbuilder.h" + +static int add_bpt_to_binary(FILE *binary, struct config *config) +{ + char *buffer; + int ret, i; + size_t len = sizeof(struct bpt_config); + struct bpt_config *cfg; + char *ptr; + + for (i = 0; i < config->n_entries; i++) { + len += sizeof(struct bpt_pentry); + + if (config->entries[i]->type != BPT_TYPE_CHAIN) + len += ((strlen(config->entries[i]->pname) + + 15) & ~0x0F); + } + + buffer = malloc(len); + + if (buffer == NULL) + return -1; + + cfg = (struct bpt_config *)buffer; + + cfg->id = BPT_ID; + cfg->timeout = config->timeout; + cfg->entries = config->n_entries; + + ptr = buffer + sizeof(struct bpt_config); + + for (i = 0; i < config->n_entries; i++) { + int nlen = 0; + struct bpt_pentry *pentry = (struct bpt_pentry *)ptr; + + pentry->index = config->entries[i]->index; + pentry->parent = config->entries[i]->parent; + pentry->type = config->entries[i]->type; + pentry->flags = config->entries[i]->flags; + + strncpy((char *)pentry->title, + (char *)config->entries[i]->title, + sizeof(pentry->title)); + + if (config->entries[i]->type != BPT_TYPE_CHAIN) { + nlen = strlen(config->entries[i]->pname); + nlen = (nlen + 15) & ~0x0F; + + strcpy((char *)(ptr + sizeof(struct bpt_pentry)), + config->entries[i]->pname); + + pentry->nlen = nlen; + } + + ptr += sizeof(struct bpt_pentry); + + if (config->entries[i]->type != BPT_TYPE_CHAIN) + ptr += nlen; + } + + ret = fwrite(buffer, len, 1, binary); + free(buffer); + return ret; +} + +int create_binary_from_config(const char *input, const char *output) +{ + struct config config; + FILE *stream_in; + FILE *stream_out; + int ret = -1; + + stream_in = fopen(input, "r"); + + if (stream_in == NULL) { + warn("E: Couldn't open %s for reading\n", input); + return -1; + } + + memset(&config, 0, sizeof(config)); + + parseconfig(stream_in, &config); + fclose(stream_in); + + stream_out = fopen(output, "wb"); + + if (stream_out == NULL) { + warn("E: Couldn't create new binary file %s\n", output); + return -1; + } + + ret = add_bpt_to_binary(stream_out, &config); + + fclose(stream_out); + + return ret; +} diff --git a/payloads/bayou/bptbuilder/main.c b/payloads/bayou/bptbuilder/main.c new file mode 100644 index 0000000..8427739 --- /dev/null +++ b/payloads/bayou/bptbuilder/main.c @@ -0,0 +1,79 @@ +/* + * This file is part of the bayou project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <string.h> +#include <getopt.h> +#include "bptbuilder.h" + +static void usage(void) +{ + printf("./bptbuilder [-c config] [create|show] [binary]\n"); +} + +int main(int argc, char **argv) +{ + char *config = NULL; + + while (1) { + signed ch = getopt(argc, argv, "c:"); + + if (ch == -1) + break; + + switch (ch) { + case 'c': + config = optarg; + break; + default: + usage(); + return -1; + } + } + + if (optind >= argc) { + usage(); + return 0; + } + + if (!strcmp(argv[optind], "create")) { + if (config == NULL) { + warn("E: No config was provided\n"); + usage(); + return -1; + } + + if (optind + 1 >= argc) { + warn("E: No binary file name was given\n"); + usage(); + return -1; + } + + create_binary_from_config((const char *)config, + (const char *)argv[optind + 1]); + } else if (!strcmp(argv[optind], "show")) { + if (optind + 1 >= argc) { + warn("E: No binary file name was given\n"); + usage(); + return -1; + } + bptbuilder_show_binary((const char *)argv[optind + 1]); + } else { + usage(); + return -1; + } + + return 0; +} diff --git a/payloads/bayou/bptbuilder/show.c b/payloads/bayou/bptbuilder/show.c new file mode 100644 index 0000000..1aa1d89 --- /dev/null +++ b/payloads/bayou/bptbuilder/show.c @@ -0,0 +1,134 @@ +/* + * This file is part of the bayou project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> +#include "bptbuilder.h" + +void show_subchain(struct bpt_config *cfg, char *fptr, int index) +{ + int i; + char *ptr = fptr + sizeof(struct bpt_config); + + for (i = 0; i < cfg->entries; i++) { + struct bpt_pentry *entry = (struct bpt_pentry *)ptr; + + if (entry->parent == index) + printf(" + %.64s\n", + ptr + sizeof(struct bpt_pentry)); + + ptr += (sizeof(struct bpt_pentry) + entry->nlen); + } +} + +int show_payloads(struct bpt_config *cfg, char *fptr) +{ + int i; + char *ptr = fptr + sizeof(struct bpt_config); + + for (i = 0; i < cfg->entries; i++) { + struct bpt_pentry *entry = (struct bpt_pentry *)ptr; + + /* If the current entry is a sub-chain, skip. */ + if (entry->parent != 0) { + ptr += (sizeof(struct bpt_pentry) + entry->nlen); + continue; + } + + printf(" "); + + if (entry->flags & BPT_FLAG_DEFAULT) + printf("D"); + else + printf(" "); + + if (entry->flags & BPT_FLAG_NOSHOW) + printf("N"); + else + printf(" "); + + switch (entry->type) { + case BPT_TYPE_CHOOSER: + printf(" MENU "); + break; + case BPT_TYPE_CHAIN: + printf(" CHAIN"); + break; + } + + if (entry->title[0] != 0) + printf(" %.64s\n", entry->title); + else + printf(" - no title -\n"); + + if (entry->type == BPT_TYPE_CHOOSER) + printf(" %.60s\n", + ptr + sizeof(struct bpt_pentry)); + else + show_subchain(cfg, fptr, entry->index); + + ptr += (sizeof(struct bpt_pentry) + entry->nlen); + } + + return 0; +} + +int bptbuilder_show_binary(const char *input) +{ + int ret = -1; + size_t fsz; + FILE *binary; + struct bpt_config *cfg; + char *buffer; + + binary = fopen(input, "rb"); + + if (binary == NULL) { + warn("E: Couldn't open binary file %s\n", input); + return -1; + } + + fseek(binary, 0L, SEEK_END); + fsz = ftell(binary); + buffer = malloc(fsz); + rewind(binary); + + if (buffer == NULL) { + warn("E: Couldn't malloc the memory needed\n"); + goto err; + } + + fread(buffer, fsz, 1, binary); + + cfg = (struct bpt_config *)buffer; + + if (cfg->id != BPT_ID) { + warn("E: BPT ID does not match\n"); + goto err; + } + + printf("Bayou Payload Configuration\n"); + printf("Timeout = %d seconds\n", cfg->timeout); + + printf("Payload List:\n"); + show_payloads(cfg, buffer); + ret = 0; + +err: + fclose(binary); + free(buffer); + + return ret; +} diff --git a/payloads/bayou/cbfs_walker.c b/payloads/bayou/cbfs_walker.c new file mode 100644 index 0000000..0a7d9f8 --- /dev/null +++ b/payloads/bayou/cbfs_walker.c @@ -0,0 +1,90 @@ +/* + * This file is part of the bayou project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "bayou.h" + +char **cbfs_filenames; +int cbfs_filecount; + +/* Functions used to walk through the CBFS and read filenames. */ +static struct cbfs_file *getfile(const struct cbfs_header *header, + struct cbfs_file *f) +{ + while (1) { + if (f < (struct cbfs_file *)(0xffffffff - + ntohl(header->romsize))) + return NULL; + if (f->magic == 0) + return NULL; + /* 8 is the max size of cbfs_file->magic */ + if (strncmp(f->magic, CBFS_FILE_MAGIC, 8) == 0) + return f; + f = (void *)f + ntohl(header->align); + } +} + +static struct cbfs_file *firstfile(const struct cbfs_header *header) +{ + return getfile(header, (void *)(0 - ntohl(header->romsize) + + ntohl(header->offset))); +} + +static struct cbfs_file *nextfile(const struct cbfs_header *header, + struct cbfs_file *f) +{ + f = (void *)f + ALIGN(ntohl(f->len) + ntohl(f->offset), + ntohl(header->align)); + + return getfile(header, f); +} + +static int check_payload(struct cbfs_file *file) +{ + char *name = file->filename; + + if (!strncmp(name, "img/", 4)) + return 1; + + return 0; +} + +int init_payload_filenames(void) +{ + const struct cbfs_header *header; + struct cbfs_file *file; + int index = 0; + + cbfs_filecount = 0; + header = get_cbfs_header(); + + if (header == CBFS_HEADER_INVALID_ADDRESS) + return -1; + + if (header->magic != ntohl(CBFS_HEADER_MAGIC)) + return -1; + + for (file = firstfile(header); file; file = nextfile(header, file)) + if (check_payload(file)) + cbfs_filecount++; + + cbfs_filenames = malloc(cbfs_filecount * sizeof(char *)); + if (!cbfs_filenames) + return -1; + + for (file = firstfile(header); file; file = nextfile(header, file)) + if (check_payload(file)) + cbfs_filenames[index++] = + strdup((const char *)file->filename); + + return 0; +} diff --git a/payloads/bayou/config.c b/payloads/bayou/config.c index ad315c8..d14c0b5 100644 --- a/payloads/bayou/config.c +++ b/payloads/bayou/config.c @@ -17,7 +17,8 @@ struct bayoucfg bayoucfg; -static int add_payload(struct LAR *lar, struct larent *larent) +/* Add the given cbfs_file/payloads to the entries in bayoucfg */ +static int add_payload(struct cbfs_file *file) { struct payload *payload; int plen; @@ -29,19 +30,15 @@ static int add_payload(struct LAR *lar, struct larent *larent) payload = &bayoucfg.entries[bayoucfg.n_entries]; - if (strncmp((char *)larent->name, "payload/", 8)) - return -1; - - if (larstat(lar, (const char *)larent->name, &payload->stat)) - return -1; - - /* Make sure the LAR entry is valid. */ - if (!lfverify(lar, (const char *)larent->name)) + if (strncmp((char *)file->filename, "img/", 4)) { + printf("Name comparison failed!\n"); return -1; + } /* Get a pointer to the start of the file. */ - fptr = larfptr(lar, (const char *)larent->name); + fptr = cbfs_find_file((const char *)file->filename, CBFS_TYPE_PAYLOAD); + printf("%s\n", file->filename); if (fptr == NULL) return -1; @@ -52,6 +49,8 @@ static int add_payload(struct LAR *lar, struct larent *larent) payload->pentry.parent = 0; payload->pentry.type = BPT_TYPE_CHOOSER; payload->pentry.flags = 0; + strncpy((char *) payload->pentry.title, file->filename, + sizeof(payload->pentry.title)); plen = self_get_params(fptr, &params); payload_parse_params(payload, params, plen); @@ -63,17 +62,19 @@ static int add_payload(struct LAR *lar, struct larent *larent) return 0; } -static int lar_walk_files(struct LAR *lar, - int (*cb) (struct LAR *, struct larent *)) +static int cbfs_walk_files(int (*cb) (struct cbfs_file *)) { - struct larent *larent; + struct cbfs_file *file; int ret = 0; - rewindlar(lar); + for (int i = 0; i < cbfs_filecount; i++) { + file = cbfs_find(cbfs_filenames[i]); - while ((larent = readlar(lar)) != NULL) { - if ((ret = cb(lar, larent))) - break; + if (file != NULL) { + ret = cb(file); + if (ret) + break; + } } return ret; @@ -83,37 +84,42 @@ static int lar_walk_files(struct LAR *lar, * If reading the bayou_payload_table fails for some reason, then construct * a dummy table. All valid payloads in the lar are added as chooser items. */ -static void build_dummy_table(struct LAR *lar) +static void build_dummy_table(void) { bayoucfg.timeout = 0xFF; bayoucfg.n_entries = 0; - lar_walk_files(lar, add_payload); + cbfs_walk_files(add_payload); } -int get_configuration(struct LAR *lar) +int get_configuration(struct region_device *cbfs) { - struct larstat stat; + struct cbfs_file *bpt_file; struct bpt_config *bptcfg; - u8 *fptr, *ptr; - int i; + u8 *bpt_buffer, *pt_ptr; /* * If bayou_payload_table doesn't exist, then dummy up - * a table from the LAR contents. + * a table from the CBFS contents. */ - if (larstat(lar, "bayou_payload_table", &stat) || - !lfverify(lar, "bayou_payload_table")) - build_dummy_table(lar); + bpt_file = cbfs_find("bayou_payload_table"); - /* Open up the BPT and get the creamy goodness within. */ + if (bpt_file == NULL) { + build_dummy_table(); + return -1; + } - fptr = larfptr(lar, "bayou_payload_table"); + /* Read the BPT and get the creamy goodness within. */ - if (fptr == NULL) - build_dummy_table(lar); + bpt_buffer = cbfs_find_file("bayou_payload_table", CBFS_TYPE_RAW); + + if (bpt_buffer == NULL) { + build_dummy_table(); + return -1; + } - bptcfg = (struct bpt_config *)fptr; + /* Store the Global configuration table. */ + bptcfg = (struct bpt_config *)bpt_buffer; bayoucfg.timeout = bptcfg->timeout; bayoucfg.n_entries = bptcfg->entries; @@ -124,37 +130,40 @@ int get_configuration(struct LAR *lar) bayoucfg.n_entries = BAYOU_MAX_ENTRIES; } - ptr = fptr + sizeof(struct bpt_config); + /* Start keeping track of the Payload tables. */ + pt_ptr = bpt_buffer + sizeof(struct bpt_config); - for (i = 0; i < bayoucfg.n_entries; i++) { - struct bpt_pentry *entry = (struct bpt_pentry *)ptr; + for (int i = 0; i < bayoucfg.n_entries; i++) { + struct bpt_pentry *entry = (struct bpt_pentry *)pt_ptr; struct payload *p = &(bayoucfg.entries[i]); int plen; - u8 *params = NULL; + uint8_t *params = NULL; memcpy(&p->pentry, entry, sizeof(struct bpt_pentry)); if (entry->type != BPT_TYPE_CHAIN) { - char *lname = (char *)ptr + sizeof(struct bpt_pentry); - - if (larstat(lar, (const char *)lname, &p->stat)) - build_dummy_table(lar); + char *lname = + (char *)pt_ptr + sizeof(struct bpt_pentry); + struct cbfs_handle *payload_handle = + cbfs_get_handle(cbfs, (const char *)lname); + uint8_t *payload_ptr; - if (!lfverify(lar, (const char *)lname)) - build_dummy_table(lar); + if (!payload_handle) + build_dummy_table(); - fptr = larfptr(lar, (const char *)lname); + payload_ptr = cbfs_get_contents(payload_handle, + (size_t *)payload_handle->content_size, 0); - if (verify_self(fptr)) - p->fptr = fptr; + if (verify_self(payload_ptr)) + p->fptr = payload_ptr; else - build_dummy_table(lar); + build_dummy_table(); - plen = self_get_params(fptr, &params); + plen = self_get_params(payload_ptr, &params); payload_parse_params(p, params, plen); } - ptr += sizeof(struct bpt_pentry) + entry->nlen; + pt_ptr += sizeof(struct bpt_pentry) + entry->nlen; } return 0; diff --git a/payloads/bayou/lzma.c b/payloads/bayou/lzma.c deleted file mode 100644 index a7a8717..0000000 --- a/payloads/bayou/lzma.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - -Coreboot interface to memory-saving variant of LZMA decoder - -(C)opyright 2006 Carl-Daniel Hailfinger -Released under the GNU GPL v2 or later - -Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA -SDK 4.42, which is written and distributed to public domain by Igor Pavlov. - -*/ - -#include <libpayload.h> -#include "lzmadecode.c" - -unsigned long ulzma(u8 *src, u8 *dst) -{ - unsigned char properties[LZMA_PROPERTIES_SIZE]; - UInt32 outSize; - SizeT inProcessed; - SizeT outProcessed; - int res; - CLzmaDecoderState state; - SizeT mallocneeds; - unsigned char scratchpad[15980]; - - memcpy(properties, src, LZMA_PROPERTIES_SIZE); - outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); - if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { - printf("Incorrect stream properties\n"); - } - mallocneeds = (LzmaGetNumProbs(&state.Properties) * sizeof(CProb)); - if (mallocneeds > 15980) { - printf("Decoder scratchpad too small!\n"); - } - state.Probs = (CProb *)scratchpad; - res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed, - dst, outSize, &outProcessed); - if (res != 0) { - printf("Decoding error = %d\n", res); - } - return outSize; -} diff --git a/payloads/bayou/lzmadecode.c b/payloads/bayou/lzmadecode.c deleted file mode 100644 index b03415f..0000000 --- a/payloads/bayou/lzmadecode.c +++ /dev/null @@ -1,398 +0,0 @@ -/* - LzmaDecode.c - LZMA Decoder (optimized for Speed version) - - LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#include "lzmadecode.h" - -#define kNumTopBits 24 -#define kTopValue ((UInt32)1 << kNumTopBits) - -#define kNumBitModelTotalBits 11 -#define kBitModelTotal (1 << kNumBitModelTotalBits) -#define kNumMoveBits 5 - -#define RC_READ_BYTE (*Buffer++) - -#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ - { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} - - -#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } - -#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - - -#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } - -#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) -#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; -#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; - -#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ - { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) - -#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ - { int i = numLevels; res = 1; \ - do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ - res -= (1 << numLevels); } - - -#define kNumPosBitsMax 4 -#define kNumPosStatesMax (1 << kNumPosBitsMax) - -#define kLenNumLowBits 3 -#define kLenNumLowSymbols (1 << kLenNumLowBits) -#define kLenNumMidBits 3 -#define kLenNumMidSymbols (1 << kLenNumMidBits) -#define kLenNumHighBits 8 -#define kLenNumHighSymbols (1 << kLenNumHighBits) - -#define LenChoice 0 -#define LenChoice2 (LenChoice + 1) -#define LenLow (LenChoice2 + 1) -#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) -#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) - - -#define kNumStates 12 -#define kNumLitStates 7 - -#define kStartPosModelIndex 4 -#define kEndPosModelIndex 14 -#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) - -#define kNumPosSlotBits 6 -#define kNumLenToPosStates 4 - -#define kNumAlignBits 4 -#define kAlignTableSize (1 << kNumAlignBits) - -#define kMatchMinLen 2 - -#define IsMatch 0 -#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) -#define IsRepG0 (IsRep + kNumStates) -#define IsRepG1 (IsRepG0 + kNumStates) -#define IsRepG2 (IsRepG1 + kNumStates) -#define IsRep0Long (IsRepG2 + kNumStates) -#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) -#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) -#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) -#define LenCoder (Align + kAlignTableSize) -#define RepLenCoder (LenCoder + kNumLenProbs) -#define Literal (RepLenCoder + kNumLenProbs) - -#if Literal != LZMA_BASE_SIZE -StopCompilingDueBUG -#endif - -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) -{ - unsigned char prop0; - if (size < LZMA_PROPERTIES_SIZE) - return LZMA_RESULT_DATA_ERROR; - prop0 = propsData[0]; - if (prop0 >= (9 * 5 * 5)) - return LZMA_RESULT_DATA_ERROR; - { - for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); - for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); - propsRes->lc = prop0; - /* - unsigned char remainder = (unsigned char)(prop0 / 9); - propsRes->lc = prop0 % 9; - propsRes->pb = remainder / 5; - propsRes->lp = remainder % 5; - */ - } - - return LZMA_RESULT_OK; -} - -#define kLzmaStreamWasFinishedId (-1) - -int LzmaDecode(CLzmaDecoderState *vs, - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) -{ - CProb *p = vs->Probs; - SizeT nowPos = 0; - Byte previousByte = 0; - UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; - UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; - int lc = vs->Properties.lc; - - - int state = 0; - UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; - int len = 0; - const Byte *Buffer; - const Byte *BufferLim; - UInt32 Range; - UInt32 Code; - - *inSizeProcessed = 0; - *outSizeProcessed = 0; - - { - UInt32 i; - UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); - for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - } - - RC_INIT(inStream, inSize); - - - while(nowPos < outSize) - { - CProb *prob; - UInt32 bound; - int posState = (int)( - (nowPos - ) - & posStateMask); - - prob = p + IsMatch + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - int symbol = 1; - UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * - ((( - (nowPos - ) - & literalPosMask) << lc) + (previousByte >> (8 - lc)))); - - if (state >= kNumLitStates) - { - int matchByte; - matchByte = outStream[nowPos - rep0]; - do - { - int bit; - CProb *probLit; - matchByte <<= 1; - bit = (matchByte & 0x100); - probLit = prob + 0x100 + bit + symbol; - RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) - } - while (symbol < 0x100); - } - while (symbol < 0x100) - { - CProb *probLit = prob + symbol; - RC_GET_BIT(probLit, symbol) - } - previousByte = (Byte)symbol; - - outStream[nowPos++] = previousByte; - if (state < 4) state = 0; - else if (state < 10) state -= 3; - else state -= 6; - } - else - { - UpdateBit1(prob); - prob = p + IsRep + state; - IfBit0(prob) - { - UpdateBit0(prob); - rep3 = rep2; - rep2 = rep1; - rep1 = rep0; - state = state < kNumLitStates ? 0 : 3; - prob = p + LenCoder; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG0 + state; - IfBit0(prob) - { - UpdateBit0(prob); - prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - UpdateBit0(prob); - - if (nowPos == 0) - return LZMA_RESULT_DATA_ERROR; - - state = state < kNumLitStates ? 9 : 11; - previousByte = outStream[nowPos - rep0]; - outStream[nowPos++] = previousByte; - - continue; - } - else - { - UpdateBit1(prob); - } - } - else - { - UInt32 distance; - UpdateBit1(prob); - prob = p + IsRepG1 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep1; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG2 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep2; - } - else - { - UpdateBit1(prob); - distance = rep3; - rep3 = rep2; - } - rep2 = rep1; - } - rep1 = rep0; - rep0 = distance; - } - state = state < kNumLitStates ? 8 : 11; - prob = p + RepLenCoder; - } - { - int numBits, offset; - CProb *probLen = prob + LenChoice; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenLow + (posState << kLenNumLowBits); - offset = 0; - numBits = kLenNumLowBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenChoice2; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenMid + (posState << kLenNumMidBits); - offset = kLenNumLowSymbols; - numBits = kLenNumMidBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenHigh; - offset = kLenNumLowSymbols + kLenNumMidSymbols; - numBits = kLenNumHighBits; - } - } - RangeDecoderBitTreeDecode(probLen, numBits, len); - len += offset; - } - - if (state < 4) - { - int posSlot; - state += kNumLitStates; - prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << - kNumPosSlotBits); - RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); - if (posSlot >= kStartPosModelIndex) - { - int numDirectBits = ((posSlot >> 1) - 1); - rep0 = (2 | ((UInt32)posSlot & 1)); - if (posSlot < kEndPosModelIndex) - { - rep0 <<= numDirectBits; - prob = p + SpecPos + rep0 - posSlot - 1; - } - else - { - numDirectBits -= kNumAlignBits; - do - { - RC_NORMALIZE - Range >>= 1; - rep0 <<= 1; - if (Code >= Range) - { - Code -= Range; - rep0 |= 1; - } - } - while (--numDirectBits != 0); - prob = p + Align; - rep0 <<= kNumAlignBits; - numDirectBits = kNumAlignBits; - } - { - int i = 1; - int mi = 1; - do - { - CProb *prob3 = prob + mi; - RC_GET_BIT2(prob3, mi, ; , rep0 |= i); - i <<= 1; - } - while(--numDirectBits != 0); - } - } - else - rep0 = posSlot; - if (++rep0 == (UInt32)(0)) - { - /* it's for stream version */ - len = kLzmaStreamWasFinishedId; - break; - } - } - - len += kMatchMinLen; - if (rep0 > nowPos) - return LZMA_RESULT_DATA_ERROR; - - - do - { - previousByte = outStream[nowPos - rep0]; - len--; - outStream[nowPos++] = previousByte; - } - while(len != 0 && nowPos < outSize); - } - } - RC_NORMALIZE; - - - *inSizeProcessed = (SizeT)(Buffer - inStream); - *outSizeProcessed = nowPos; - return LZMA_RESULT_OK; -} diff --git a/payloads/bayou/lzmadecode.h b/payloads/bayou/lzmadecode.h deleted file mode 100644 index 3771245..0000000 --- a/payloads/bayou/lzmadecode.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - LzmaDecode.h - LZMA Decoder interface - - LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#ifndef LZMADECODE_H -#define LZMADECODE_H - -typedef unsigned char Byte; -typedef unsigned short UInt16; -typedef unsigned int UInt32; -typedef UInt32 SizeT; - -#define CProb UInt16 - -#define LZMA_RESULT_OK 0 -#define LZMA_RESULT_DATA_ERROR 1 - - -#define LZMA_BASE_SIZE 1846 -#define LZMA_LIT_SIZE 768 - -#define LZMA_PROPERTIES_SIZE 5 - -typedef struct _CLzmaProperties -{ - int lc; - int lp; - int pb; -}CLzmaProperties; - -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); - -#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) - -#define kLzmaNeedInitId (-2) - -typedef struct _CLzmaDecoderState -{ - CLzmaProperties Properties; - CProb *Probs; - - -} CLzmaDecoderState; - - -int LzmaDecode(CLzmaDecoderState *vs, - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); - -#endif /* LZMADECODE_H */ diff --git a/payloads/bayou/main.c b/payloads/bayou/main.c index cdccea1..0299ea1 100644 --- a/payloads/bayou/main.c +++ b/payloads/bayou/main.c @@ -17,38 +17,35 @@ static void print_banner(void) { - printf("\e[H\e[JBayou Payload Chooser v0.3\n"); + printf("Bayou Payload Chooser v0.3\n"); } int main(void) { - extern unsigned long _binary_builtin_lar_start; - struct LAR *lar; + struct region_device *cbfs = NULL; print_banner(); - lar = openlar((void *)&_binary_builtin_lar_start); + console_init(); - if (lar == NULL) { - printf("[CHOOSER]: Unable to scan the attached LAR file\n"); - return -1; - } + init_payload_filenames(); - get_configuration(lar); + get_configuration(cbfs); if (bayoucfg.n_entries == 0) { - printf("[CHOOSER]: No payloads were found in the LAR\n"); + printf("[CHOOSER]: No payloads were found in the CBFS.\n"); + halt(); return -1; } /* - * If timeout == 0xFF, then show the menu immediately. - * If timeout is zero, then find and run the default item immediately. - * If there is no default item, then show the menu. - * If timeout is anything else, then show a message and wait for a - * keystroke. If there is no keystroke in time then run the default. - * If there is no default then show the menu. - */ + * If timeout == 0xFF, then show the menu immediately. + * If timeout is zero, then find and run the default item immediately. + * If there is no default item, then show the menu. + * If timeout is anything else, then show a message and wait for a + * keystroke. If there is no keystroke in time then run the default. + * If there is no default then show the menu. + */ if (bayoucfg.timeout != 0xFF) { struct payload *d = payload_get_default(); @@ -58,9 +55,11 @@ int main(void) else run_payload_timeout(d, bayoucfg.timeout); } + printf("HERE\n"); } menu(); + halt(); return 0; } diff --git a/payloads/bayou/menu.c b/payloads/bayou/menu.c index 0d312ca..ac9ef68 100644 --- a/payloads/bayou/menu.c +++ b/payloads/bayou/menu.c @@ -13,9 +13,8 @@ * GNU General Public License for more details. */ -#include <libpayload.h> -#include <curses.h> #include "bayou.h" +#include <curses.h> #define SCREEN_X 80 #define SCREEN_Y 25 diff --git a/payloads/bayou/nrv2b.c b/payloads/bayou/nrv2b.c deleted file mode 100644 index 53f7988..0000000 --- a/payloads/bayou/nrv2b.c +++ /dev/null @@ -1,86 +0,0 @@ -#include <libpayload.h> - -// This GETBIT is supposed to work on little endian -// 32bit systems. The algorithm will definitely need -// some fixing on other systems, but it might not be -// a problem since the nrv2b binary behaves the same.. - -#ifndef ENDIAN -#define ENDIAN 0 -#endif -#ifndef BITSIZE -#define BITSIZE 32 -#endif - -#define GETBIT_8(bb, src, ilen) \ - (((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1) - -#define GETBIT_LE16(bb, src, ilen) \ - (bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1)) -#define GETBIT_LE32(bb, src, ilen) \ - (bc > 0 ? ((bb>>--bc)&1) : (bc=31,\ - bb=*(const u32 *)((src)+ilen),ilen+=4,(bb>>31)&1)) - -#if ENDIAN == 0 && BITSIZE == 8 -#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen) -#endif -#if ENDIAN == 0 && BITSIZE == 16 -#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen) -#endif -#if ENDIAN == 0 && BITSIZE == 32 -#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen) -#endif - -unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p) -{ - unsigned long ilen = 0, olen = 0, last_m_off = 1; - u32 bb = 0; - unsigned bc = 0; - const u8 *m_pos; - - // skip length - src += 4; - /* FIXME: check olen with the length stored in first 4 bytes */ - - for (;;) { - unsigned int m_off, m_len; - while (GETBIT(bb, src, ilen)) { - dst[olen++] = src[ilen++]; - } - - m_off = 1; - do { - m_off = m_off * 2 + GETBIT(bb, src, ilen); - } while (!GETBIT(bb, src, ilen)); - if (m_off == 2) { - m_off = last_m_off; - } else { - m_off = (m_off - 3) * 256 + src[ilen++]; - if (m_off == 0xffffffffU) - break; - last_m_off = ++m_off; - } - - m_len = GETBIT(bb, src, ilen); - m_len = m_len * 2 + GETBIT(bb, src, ilen); - if (m_len == 0) { - m_len++; - do { - m_len = m_len * 2 + GETBIT(bb, src, ilen); - } while (!GETBIT(bb, src, ilen)); - m_len += 2; - } - m_len += (m_off > 0xd00); - - m_pos = dst + olen - m_off; - dst[olen++] = *m_pos++; - do { - dst[olen++] = *m_pos++; - } while (--m_len > 0); - } - - *ilen_p = ilen; - - return olen; - -} diff --git a/payloads/bayou/payload.c b/payloads/bayou/payload.c index a76e49f..9261b11 100644 --- a/payloads/bayou/payload.c +++ b/payloads/bayou/payload.c @@ -20,11 +20,11 @@ void run_payload(struct payload *p) { - int ret, i; + int i; /* For chooser entries, just run the payload. */ if (p->pentry.type == BPT_TYPE_CHOOSER) { - self_load_and_run(p, &ret); + self_load_and_run(p); return; } @@ -33,7 +33,7 @@ void run_payload(struct payload *p) struct payload *s = &(bayoucfg.entries[i]); if (s->pentry.parent == p->pentry.index) - self_load_and_run(s, &ret); + self_load_and_run(s); } } diff --git a/payloads/bayou/self.c b/payloads/bayou/self.c index 88e495b..8f48969 100644 --- a/payloads/bayou/self.c +++ b/payloads/bayou/self.c @@ -14,48 +14,28 @@ */ #include "bayou.h" -#include "self.h" -static int nop_decompress(void *dst, void *src, int len) +static void cbfs_decode_payload_segment(struct cbfs_payload_segment *segment, + const struct cbfs_payload_segment *src) { - memcpy(dst, src, len); - return len; -} - -#ifdef CONFIG_LZMA -extern int ulzma(u8 *, u8 *); - -static int lzma_decompress(void *dst, void *src, int len) -{ - return ulzma((u8 *) src, (u8 *) dst); -} -#endif - -#ifdef CONFIG_NRV2B -extern int unrv2b(u8 *, u8 *, unsigned long *); - -static int nrv2b_decompress(void *dst, void *src, int len) -{ - unsigned long l = (u32) len; - return unrv2b(src, dst, &l); -} -#endif - -static int zeros_decompress(void *dst, void *src, int len) -{ - memset(dst, 0, len); - return len; + /* TODO: Convert current segment macros into BE! */ + segment->type = src->type; + segment->compression = be32toh(src->compression); + segment->offset = be32toh(src->offset); + segment->load_addr = be64toh(src->load_addr); + segment->len = be32toh(src->len); + segment->mem_len = be32toh(src->mem_len); } int self_get_params(u8 *fptr, u8 **params) { - struct self_segment *seg = (struct self_segment *)fptr; + struct cbfs_payload_segment *seg = (struct cbfs_payload_segment *)fptr; - while (seg->type != SELF_TYPE_ENTRY) { + while (seg->type != PAYLOAD_SEGMENT_ENTRY) { if (seg->type == 0) return -1; - if (seg->type == SELF_TYPE_PARAMS) { + if (seg->type == PAYLOAD_SEGMENT_PARAMS) { *params = (u8 *) (fptr + seg->offset); return seg->len; } @@ -70,73 +50,60 @@ int self_get_params(u8 *fptr, u8 **params) int verify_self(u8 *ptr) { - struct self_segment *seg = (struct self_segment *)ptr; - - switch (seg->type) { - case SELF_TYPE_CODE: - case SELF_TYPE_DATA: - case SELF_TYPE_BSS: - case SELF_TYPE_PARAMS: - case SELF_TYPE_ENTRY: + struct cbfs_payload_segment seg; + + cbfs_decode_payload_segment(&seg, (struct cbfs_payload_segment *)ptr); + + switch (seg.type) { + case PAYLOAD_SEGMENT_CODE: + case PAYLOAD_SEGMENT_DATA: + case PAYLOAD_SEGMENT_BSS: + case PAYLOAD_SEGMENT_PARAMS: + case PAYLOAD_SEGMENT_ENTRY: return 1; } return 0; } -int self_load_and_run(struct payload *p, int *ret) +int self_load_and_run(struct payload *p) { - struct self_segment *seg = (struct self_segment *)p->fptr; - int (*dcmp) (void *, void *, int); + struct cbfs_payload_segment *orig_seg = + (struct cbfs_payload_segment *)p->fptr; + struct cbfs_payload_segment seg; int dlen; - switch (p->stat.compression) { -#ifdef CONFIG_LZMA - case ALGO_LZMA: - dcmp = lzma_decompress; - break; -#endif -#ifdef CONFIG_NRV2B - case ALGO_NRV2B: - dcmp = nrv2b_decompress; - break; -#endif - case ALGO_ZEROES: - dcmp = zeros_decompress; - break; - case ALGO_NONE: - dcmp = nop_decompress; - default: - printf("E: Unsupported decompression type\n"); - return -1; - } - while (1) { - u32 laddr = (u32) (seg->load_addr & 0xFFFFFFFF); + cbfs_decode_payload_segment(&seg, orig_seg); - switch (seg->type) { - case SELF_TYPE_CODE: - case SELF_TYPE_DATA: - dlen = dcmp((void *)laddr, - (void *)p->fptr + seg->offset, seg->len); + u32 laddr = (u32) (seg.load_addr & 0xFFFFFFFF); - if (dlen < seg->mem_len) { + switch (seg.type) { + case PAYLOAD_SEGMENT_PARAMS: + continue; + case PAYLOAD_SEGMENT_CODE: + case PAYLOAD_SEGMENT_DATA: + dlen = cbfs_decompress(seg.compression, + (void *)p->fptr + seg.offset, (void *)laddr, + seg.len); + + if (dlen < seg.mem_len) { memset((void *)(laddr + dlen), 0, - seg->mem_len - dlen); + seg.mem_len - dlen); } break; - case SELF_TYPE_BSS: - memset((void *)laddr, 0, seg->len); + case PAYLOAD_SEGMENT_BSS: + memset((void *)laddr, 0, seg.len); break; - case SELF_TYPE_ENTRY: - *ret = exec(laddr, 0, NULL); + case PAYLOAD_SEGMENT_ENTRY: + selfboot((void *)laddr); return 0; default: break; } - seg++; + orig_seg++; } return -1; diff --git a/payloads/bayou/self.h b/payloads/bayou/self.h deleted file mode 100644 index a341899..0000000 --- a/payloads/bayou/self.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the bayou project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SELF_H_ -#define SELF_H_ - -#include <libpayload.h> - -struct self_segment { - u32 type; - u32 offset; - u64 load_addr; - u32 len; - u32 mem_len; -}; - -struct self { - struct larstat stat; - void *fptr; -}; - -#define SELF_TYPE_CODE 0x45444F43 -#define SELF_TYPE_DATA 0x41544144 -#define SELF_TYPE_BSS 0x20535342 -#define SELF_TYPE_PARAMS 0x41524150 -#define SELF_TYPE_ENTRY 0x52544E45 - -#endif diff --git a/payloads/libpayload/configs/config.bayou b/payloads/libpayload/configs/config.bayou new file mode 100644 index 0000000..80b8370 --- /dev/null +++ b/payloads/libpayload/configs/config.bayou @@ -0,0 +1,11 @@ +# CONFIG_LP_MULTIBOOT is not set +CONFIG_LP_TINYCURSES=y +CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_UHCI=y +CONFIG_LP_USB_OHCI=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y +CONFIG_LP_BASE_ADDRESS=0x19000 +CONFIG_LP_HEAP_SIZE=16384 +CONFIG_LP_STACK_SIZE=16384

1 0

Patch merged into coreboot/master: mainboard/bap/ode_e21XX: Add board support
by gerrit＠coreboot.org 30 Jul '16

30 Jul '16

the following patch was just integrated into master: commit cf05183d1f952a903057038aee3a71698ce564b0 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Wed Jul 27 17:42:39 2016 +0200 mainboard/bap/ode_e21XX: Add board support Add next generation of BAPs (https://www.unibap.com/) SOC module, called ode_e21XX. Hardware is similar to e20XX (AMD G-Series GX-411GA Kabini), but it includes a new AMD G-Series GX-412HC (Steppe Eagle) and an updated Microsemi FPGA. Changes to Olivehillplus: - Add SuperIO Fintek F81866D - Soldered down DDR3 with ECC - User can choose between different DDR3 clk settings (lowest setting can save up to 1.2W) - Soldered down Microsemi M2S060 FPGA on PCIe lanes 2-3 Tested with: - Payload SeaBIOS 1.9.1 - Lubuntu 16.04, Kernel 4.4.0 - Windows 10 (UART functionality) Known problems: - S3 not working - IOMMU not working Change-Id: I41f6a3334ad2128695a3f7c0a6444f1678d2626e Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15918 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15918 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/bap/ode_e21XX: Add copy of amd/olivehillplus
by gerrit＠coreboot.org 30 Jul '16

30 Jul '16

the following patch was just integrated into master: commit 171e2c965aef8b47d39611280121fd2b66136df4 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Wed Jul 27 17:30:49 2016 +0200 mainboard/bap/ode_e21XX: Add copy of amd/olivehillplus Initial copy of olivehillplus. Change-Id: Ibe9b450c05bfad15a95852addb1465ac2d3cef61 Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15917 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15917 for details. -gerrit

1 0

Patch set updated for coreboot: Remove non-ascii & unprintable characters
by Martin Roth 30 Jul '16

30 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15977 -gerrit commit b8361b225d02166e9530be00151b1d406afd1694 Author: Martin Roth <martinroth(a)google.com> Date: Fri Jul 29 14:07:30 2016 -0600 Remove non-ascii & unprintable characters These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/arch/x86/acpigen.c | 6 ++-- src/arch/x86/smbios.c | 2 +- src/cpu/allwinner/a10/twi.c | 6 ++-- src/cpu/allwinner/a10/twi.h | 2 +- src/cpu/intel/slot_1/l2_cache.c | 2 +- src/drivers/xpowers/axp209/axp209.c | 18 +++++----- src/ec/quanta/ene_kb3940q/acpi/battery.asl | 2 +- src/lib/tpm_error_messages.h | 4 +-- src/mainboard/apple/macbook21/romstage.c | 4 +-- src/mainboard/cubietech/cubieboard/devicetree.cb | 2 +- src/mainboard/google/cosmos/chromeos.c | 2 +- src/mainboard/google/parrot/ec.h | 4 +-- src/mainboard/google/purin/chromeos.c | 2 +- src/mainboard/google/stout/ec.c | 4 +-- src/mainboard/google/stout/mainboard_smi.c | 4 +-- src/mainboard/google/veyron/chromeos.c | 2 +- src/mainboard/google/veyron_rialto/chromeos.c | 2 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 2 +- src/northbridge/amd/amdfam10/acpi.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 +- src/northbridge/intel/e7505/raminit.c | 4 +-- src/northbridge/intel/gm45/pcie.c | 2 +- src/northbridge/intel/i82830/smihandler.c | 4 +-- .../intel/sandybridge/report_platform.c | 2 +- src/northbridge/via/vx900/early_host_bus_ctl.c | 4 +-- src/northbridge/via/vx900/raminit_ddr3.c | 30 ++++++++-------- src/northbridge/via/vx900/sata.c | 6 ++-- src/soc/broadcom/cygnus/ddr_init.c | 4 +-- src/soc/intel/fsp_baytrail/acpi/irqroute.asl | 6 ++-- src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl | 6 ++-- src/southbridge/amd/agesa/hudson/fadt.c | 2 +- src/southbridge/amd/cimx/sb800/fadt.c | 2 +- src/southbridge/amd/pi/hudson/fadt.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 2 +- src/southbridge/intel/fsp_i89xx/smihandler.c | 2 +- .../intel/fsp_rangeley/acpi/irqroute.asl | 6 ++-- src/southbridge/intel/i82801dx/smihandler.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/i82801ix/smihandler.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- util/inteltool/cpu.c | 2 +- util/kconfig/regex.c | 42 +++++++++++----------- util/kconfig/regex.h | 12 +++---- 46 files changed, 114 insertions(+), 114 deletions(-) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index d37568c..915faac 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -222,9 +222,9 @@ void acpigen_write_string(const char *string) /* * The naming conventions for ACPI namespace names are a bit tricky as - * each element has to be 4 chars wide (»All names are a fixed 32 bits.«) - * and »By convention, when an ASL compiler pads a name shorter than 4 - * characters, it is done so with trailing underscores (‘_’).«. + * each element has to be 4 chars wide ("All names are a fixed 32 bits.") + * and "By convention, when an ASL compiler pads a name shorter than 4 + * characters, it is done so with trailing underscores ('_')". * * Check sections 5.3, 18.2.2 and 18.4 of ACPI spec 3.0 for details. */ diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 21ea2c1..9df95e9 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -16,7 +16,7 @@ */ /* - * Standard Manufacturer’s Identification Code + * Standard Manufacturer's Identification Code * JEP106AS (Revision of JEP106AR, October 2015) * MAY 2016 * http://www.jedec.org/standards-documents/results/JEP106AS diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c index 69e08ca..3ef5606 100644 --- a/src/cpu/allwinner/a10/twi.c +++ b/src/cpu/allwinner/a10/twi.c @@ -14,9 +14,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Setup helpers for Two Wire Interface (TWI) (I²C) Allwinner CPUs + * Setup helpers for Two Wire Interface (TWI) (I2C) Allwinner CPUs * - * Only functionality for I²C master is provided. + * Only functionality for I2C master is provided. * Largely based on the uboot-sunxi code. */ @@ -63,7 +63,7 @@ void a1x_twi_init(u8 bus, u32 speed_hz) configure_clock(twi, speed_hz); - /* Enable the I²C bus */ + /* Enable the I2C bus */ write32(&twi->ctl, TWI_CTL_BUS_EN); /* Issue soft reset */ write32(&twi->reset, 1); diff --git a/src/cpu/allwinner/a10/twi.h b/src/cpu/allwinner/a10/twi.h index a8ebdf3..1a33419 100644 --- a/src/cpu/allwinner/a10/twi.h +++ b/src/cpu/allwinner/a10/twi.h @@ -13,7 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Definitions Two Wire Interface (TWI) (I²C) Allwinner CPUs + * Definitions Two Wire Interface (TWI) (I2C) Allwinner CPUs */ #ifndef CPU_ALLWINNER_A10_TWI_H diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index 2699d92..7c127b3 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -339,7 +339,7 @@ int test_l2_address_alias(u32 address1, u32 address2, /* Calculates the L2 cache size. * - * Reference: Intel(R) 64 and IA-32 Architectures Software Developer�s Manual + * Reference: Intel(R) 64 and IA-32 Architectures Software Developer's Manual * Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172. * */ diff --git a/src/drivers/xpowers/axp209/axp209.c b/src/drivers/xpowers/axp209/axp209.c index f36c506..de11fbe 100644 --- a/src/drivers/xpowers/axp209/axp209.c +++ b/src/drivers/xpowers/axp209/axp209.c @@ -44,7 +44,7 @@ enum registers { * in one transaction. * These return the number of bytes read/written, or an error code. In this * case, they return 1 on success, or an error code otherwise. This is done to - * work with I²C drivers that return either 0 on success or the number of bytes + * work with I2C drivers that return either 0 on success or the number of bytes * actually transferred. */ static int axp209_read(u8 bus, u8 reg, u8 *val) @@ -62,9 +62,9 @@ static int axp209_write(u8 bus, u8 reg, u8 val) } /** - * \brief Identify and initialize an AXP209 on the I²C bus + * \brief Identify and initialize an AXP209 on the I2C bus * - * @param[in] bus I²C bus to which the AXP209 is connected + * @param[in] bus I2C bus to which the AXP209 is connected * @return CB_SUCCES on if an AXP209 is found, or an error code otherwise. */ enum cb_err axp209_init(u8 bus) @@ -91,7 +91,7 @@ enum cb_err axp209_init(u8 bus) * Valid values are between 700mV and 2275mV * * @param[in] millivolts voltage in mV units. - * @param[in] bus I²C bus to which the AXP209 is connected + * @param[in] bus I2C bus to which the AXP209 is connected * @return CB_SUCCES on success, * CB_ERR_ARG if voltage is out of range, or an error code otherwise. */ @@ -118,7 +118,7 @@ enum cb_err axp209_set_dcdc2_voltage(u8 bus, u16 millivolts) * Valid values are between 700mV and 3500mV * * @param[in] millivolts voltage in mV units. - * @param[in] bus I²C bus to which the AXP209 is connected + * @param[in] bus I2C bus to which the AXP209 is connected * @return CB_SUCCES on success, * CB_ERR_ARG if voltage is out of range, or an error code otherwise. */ @@ -145,7 +145,7 @@ enum cb_err axp209_set_dcdc3_voltage(u8 bus, u16 millivolts) * Valid values are between 700mV and 3300mV * * @param[in] millivolts voltage in mV units. - * @param[in] bus I²C bus to which the AXP209 is connected + * @param[in] bus I2C bus to which the AXP209 is connected * @return CB_SUCCES on success, * CB_ERR_ARG if voltage is out of range, or an error code otherwise. */ @@ -179,7 +179,7 @@ enum cb_err axp209_set_ldo2_voltage(u8 bus, u16 millivolts) * 2250mV, but hardware samples go as high as 3500mV. * * @param[in] millivolts voltage in mV units. - * @param[in] bus I²C bus to which the AXP209 is connected + * @param[in] bus I2C bus to which the AXP209 is connected * @return CB_SUCCES on success, * CB_ERR_ARG if voltage is out of range, or an error code otherwise. */ @@ -207,7 +207,7 @@ enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts) * Valid values are between 1250V and 3300mV * * @param[in] millivolts voltage in mV units. - * @param[in] bus I²C bus to which the AXP209 is connected + * @param[in] bus I2C bus to which the AXP209 is connected * @return CB_SUCCES on success, * CB_ERR_ARG if voltage is out of range, or an error code otherwise. */ @@ -290,7 +290,7 @@ static enum cb_err set_rail(u8 bus, int idx, u16 mv) * reconfigured, and retain its powerup voltage. * * @param[in] cfg pointer to @ref drivers_xpowers_axp209_config structure - * @param[in] bus I²C bus to which the AXP209 is connected + * @param[in] bus I2C bus to which the AXP209 is connected * @return CB_SUCCES on success, or an error code otherwise. */ enum cb_err axp209_set_voltages(u8 bus, const struct diff --git a/src/ec/quanta/ene_kb3940q/acpi/battery.asl b/src/ec/quanta/ene_kb3940q/acpi/battery.asl index 4467797..bcc9a98 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/battery.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/battery.asl @@ -67,7 +67,7 @@ Device (BATX) Store (Zero, BFWK) } - // Device insertion/removal control method that returns a device’s status. + // Device insertion/removal control method that returns a device's status. // Power resource object that evaluates to the current on or off state of // the Power Resource. Method (_STA, 0, Serialized) diff --git a/src/lib/tpm_error_messages.h b/src/lib/tpm_error_messages.h index 3b0f48c..279bc2b 100644 --- a/src/lib/tpm_error_messages.h +++ b/src/lib/tpm_error_messages.h @@ -158,7 +158,7 @@ and locality modifier not part of command transport" }, { "TPM_BAD_LOCALITY", TPM_E_BASE + 61, "The locality is incorrect for the attempted operation" }, { "TPM_READ_ONLY", TPM_E_BASE + 62, -"The NV area is read only and canât be written to" }, +"The NV area is read only and can't be written to" }, { "TPM_PER_NOWRITE", TPM_E_BASE + 63, "There is no protection on the write to the NV area" }, { "TPM_FAMILYCOUNT", TPM_E_BASE + 64, @@ -208,7 +208,7 @@ by the TPM Owner" }, "The atomic process indicated by the submitted DAA command is not\n\ the expected process" }, { "TPM_DAA_ISSUER_VALIDITY", TPM_E_BASE + 86, -"The issuerâs validity check has detected an inconsistency" }, +"The issuer's validity check has detected an inconsistency" }, { "TPM_DAA_WRONG_W", TPM_E_BASE + 87, "The consistency check on w has failed" }, { "TPM_BAD_HANDLE", TPM_E_BASE + 88, diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 296f898..4d49e89 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -85,8 +85,8 @@ static void ich7_enable_lpc(void) // Macbook21: 0x0010 == 00000000 00010000 // Bit 9:8 LPT Decode Range. This field determines which range to // decode for the LPT Port. - // 00 = 378h 37Fh and 778h 77Fh - // 10 = 3BCh 3BEh and 7BCh 7BEh + // 00 = 378h - 37Fh and 778h - 77Fh + // 10 = 3BCh - 3BEh and 7BCh - 7BEh pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); // LPC_EN--LPC I/F Enables Register diff --git a/src/mainboard/cubietech/cubieboard/devicetree.cb b/src/mainboard/cubietech/cubieboard/devicetree.cb index 65ea5ff..033a89e 100644 --- a/src/mainboard/cubietech/cubieboard/devicetree.cb +++ b/src/mainboard/cubietech/cubieboard/devicetree.cb @@ -1,7 +1,7 @@ chip cpu/allwinner/a10 device cpu_cluster 0 on end - chip drivers/xpowers/axp209 # AXP209 is on I²C 0 + chip drivers/xpowers/axp209 # AXP209 is on I2C 0 device i2c 0x34 on end register "dcdc2_voltage_mv" = "1400" # Vcore register "dcdc3_voltage_mv" = "1250" # DLL Vdd diff --git a/src/mainboard/google/cosmos/chromeos.c b/src/mainboard/google/cosmos/chromeos.c index ca80432..a405cf0 100644 --- a/src/mainboard/google/cosmos/chromeos.c +++ b/src/mainboard/google/cosmos/chromeos.c @@ -1,4 +1,4 @@ -/* +/* * This file is part of the coreboot project. * * Copyright 2014 Google Inc. diff --git a/src/mainboard/google/parrot/ec.h b/src/mainboard/google/parrot/ec.h index 200750a..e389a77 100644 --- a/src/mainboard/google/parrot/ec.h +++ b/src/mainboard/google/parrot/ec.h @@ -49,8 +49,8 @@ * AC power plug-out C8h * Modem Ring In CAh * PME signal active CEh - * Acer Hotkey Function – Make event D5h - * Acer Hotkey Function – Break event D6h + * Acer Hotkey Function - Make event D5h + * Acer Hotkey Function - Break event D6h */ #ifndef __ACPI__ diff --git a/src/mainboard/google/purin/chromeos.c b/src/mainboard/google/purin/chromeos.c index 0bd489a..e6843a1 100644 --- a/src/mainboard/google/purin/chromeos.c +++ b/src/mainboard/google/purin/chromeos.c @@ -1,4 +1,4 @@ -/* +/* * This file is part of the coreboot project. * * Copyright 2015 Google Inc. diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 004c492..a7006d9 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -48,10 +48,10 @@ void stout_ec_init(void) * Set USB Power off in S3 (enabled in S3 path if requested in gnvs) * Bit0 of 0x0D/Bit0 of 0x26 * 0/0 All USB port off - * 1/0 USB on, all USB port didn’t support wake up + * 1/0 USB on, all USB port didn't support wake up * 0/1 USB on, yellow port support wake up charge, but may not support * charge smart phone. - * 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system. + * 1/1 USB on, yellow port in AUTO mode and didn't support wake up system. */ ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) & 0xE); ec_write(EC_USB_S3_EN, ec_read(EC_USB_S3_EN) & 0xE); diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 7fed9cf..e25c576 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -58,10 +58,10 @@ void mainboard_smi_sleep(u8 slp_typ) * Tell the EC to Enable USB power for S3 if requested. * Bit0 of 0x0D/Bit0 of 0x26 * 0/0 All USB port off - * 1/0 USB on, all USB port didn’t support wake up + * 1/0 USB on, all USB port didn't support wake up * 0/1 USB on, yellow port support wake up charge, but may not support * charge smart phone. - * 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system. + * 1/1 USB on, yellow port in AUTO mode and didn't support wake up system. */ if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0) { ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) | 0x00); diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index 42be8ca..b730622 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -1,4 +1,4 @@ -/* +/* * This file is part of the coreboot project. * * Copyright 2014 Rockchip Inc. diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 74f84d4..ac1afd9 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -1,4 +1,4 @@ -/* +/* * This file is part of the coreboot project. * * Copyright 2014 Rockchip Inc. diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 606e68c..8d61564 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -49,7 +49,7 @@ #define PANEL_TABLE_ID8 8 // 1280x1024_108MHz #define PANEL_TABLE_ID9 9 // 1366x768_86MHz_chimei_V32B1L01 -// Callback Sub-Function 05h � Select Boot-up TV Standard +// Callback Sub-Function 05h - Select Boot-up TV Standard #define TV_MODE_00 0x00 /* NTSC */ #define TV_MODE_01 0x01 /* PAL */ #define TV_MODE_02 0x02 /* PALM */ diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 0362b90..f84b7a0 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -40,7 +40,7 @@ #define LCD_PANEL_ID_04 0x04 /* 1680x1050, 24 bits, 2 channels */ #define LCD_PANEL_ID_05 0x05 /* 1920x1200, 24 bits, 2 channels */ #define LCD_PANEL_ID_06 0x06 /* 1920x1080, 24 bits, 2 channels */ -//Callback Sub-Function 05h – Select Boot-up TV Standard +//Callback Sub-Function 05h - Select Boot-up TV Standard #define TV_MODE_00 0x00 /* NTSC */ #define TV_MODE_01 0x01 /* PAL */ #define TV_MODE_02 0x02 /* PALM */ diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 9f2c14e..83af426 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -187,7 +187,7 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { /* VT3409 no PCI-E */ { 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E }, // Set Exxxxxxx as pcie mmio config range { 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B }, // Support extended cfg address of pcie - // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control + // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control // Set ROMSIP value by software /* diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 960d468..d4ad9a4 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -129,7 +129,7 @@ static unsigned long acpi_fill_srat(unsigned long current) static unsigned long acpi_fill_slit(unsigned long current) { - /* Implement SLIT algorithm in BKDG Rev. 3.62 § 2.3.6.1 + /* Implement SLIT algorithm in BKDG Rev. 3.62 Section 2.3.6.1 * Fill the first 8 bytes with the node number, * then fill the next num*num byte with the distance, * Distance entries vary with topology; the local node diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 2501410..8974a08 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1541,7 +1541,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "+"); } else { if (read_iter < 16) - printk(BIOS_DEBUG, "°"); + printk(BIOS_DEBUG, ":"); else printk(BIOS_DEBUG, "."); } diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index b48328f..7734ca5 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1007,10 +1007,10 @@ static inline void __attribute__((always_inline)) unsigned int a1, a2; asm volatile("movd %%xmm2, %%eax;" : "=a" (a1) ::); asm volatile("movd %%xmm3, %%eax;" : "=a" (a2) ::); - printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2); + printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2); asm volatile("movd %%xmm0, %%eax;" : "=a" (a1) ::); asm volatile("movd %%xmm1, %%eax;" : "=a" (a2) ::); - printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2); + printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2); #endif } diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 30ceb36..cc1fde7 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -289,7 +289,7 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) * Maybe we just have to advertise ASPM through LCAP[11:10] * (LCAP[17:15] == 010b is the default, will be locked, as it's R/WO), * set 0x208[31:24,23:22] to zero, 0x224[24:21] = 1 and let the - * generic ASPM code do the rest? – Nico + * generic ASPM code do the rest? - Nico */ /* TODO: Prepare PEG for ASPM. */ } diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c index 12da698..667f874 100644 --- a/src/northbridge/intel/i82830/smihandler.c +++ b/src/northbridge/intel/i82830/smihandler.c @@ -166,11 +166,11 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) } case 0x0002: printk(BIOS_DEBUG, "|- MBI_Attach\n"); - printk(BIOS_DEBUG, "| |- Not Implemented!\n"); + printk(BIOS_DEBUG, "| |- Not Implemented!\n"); break; case 0x0003: printk(BIOS_DEBUG, "|- MBI_Detach\n"); - printk(BIOS_DEBUG, "| |- Not Implemented!\n"); + printk(BIOS_DEBUG, "| |- Not Implemented!\n"); break; case 0x0201: { obj_header_t *obj_header = (obj_header_t *)banner_id; diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index aa758c8..39bff65 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -62,7 +62,7 @@ static struct { /* 6-series PCI ids from * Intel® 6 Series Chipset and * Intel® C200 Series Chipset - * Specification Update – NDA + * Specification Update - NDA * October 2013 * CDI / IBP#: 440377 */ diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c index 64680c5..159b2a4 100644 --- a/src/northbridge/via/vx900/early_host_bus_ctl.c +++ b/src/northbridge/via/vx900/early_host_bus_ctl.c @@ -20,9 +20,9 @@ static void vx900_cpu_bus_preram_setup(void) { /* Faster CPU to DRAM Cycle */ pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08); - /* CPU Interface Control – Basic Options */ + /* CPU Interface Control - Basic Options */ pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c); - /*CPU Interface Control – Advanced Options */ + /*CPU Interface Control - Advanced Options */ pci_write_config8(HOST_BUS, 0x52, 0xc7); /* Enable 8QW burst and 4QW request merging [4] and [2] * and special mode for read cycles bit[3] */ diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index e0c5579..f4b61de 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -186,14 +186,14 @@ static pci_reg8 mcu_drv_ctrl_config[] = { {0xd4, 0x80}, /* Set internal ODT to dynamically turn on or off */ {0xd6, 0x20}, /* Enable strong driving for MA and DRAM commands */ {0xd0, 0x88}, /* (ODT) Strength ?has effect? */ - {0xe0, 0x88}, /* DRAM Driving – Group DQS (MDQS) */ + {0xe0, 0x88}, /* DRAM Driving - Group DQS (MDQS) */ {0xe1, 0x00}, /* Disable offset mode for driving strength control */ - {0xe2, 0x88}, /* DRAM Driving – Group DQ (MD, MDQM) */ - {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */ - {0xe8, 0x88}, /* DRAM Driving – Group MA (MA, MBA, MSRAS, MSCAS, MSWE) */ - {0xe6, 0xff}, /* DRAM Driving – Group DCLK0 (DCLK[2:0] for DIMM0) */ - {0xe7, 0xff}, /* DRAM Driving – Group DCLK1 (DCLK[5:3] for DIMM1) */ - {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */ + {0xe2, 0x88}, /* DRAM Driving - Group DQ (MD, MDQM) */ + {0xe4, 0xcc}, /* DRAM Driving - Group CSA (MCS, MCKE, MODT) */ + {0xe8, 0x88}, /* DRAM Driving - Group MA (MA, MBA, MSRAS, MSCAS, MSWE) */ + {0xe6, 0xff}, /* DRAM Driving - Group DCLK0 (DCLK[2:0] for DIMM0) */ + {0xe7, 0xff}, /* DRAM Driving - Group DCLK1 (DCLK[5:3] for DIMM1) */ + {0xe4, 0xcc}, /* DRAM Driving - Group CSA (MCS, MCKE, MODT) */ {0x91, 0x08}, /* MCLKO Output Phase Delay - I */ {0x92, 0x08}, /* MCLKO Output Phase Delay - II */ {0x93, 0x16}, /* CS/CKE Output Phase Delay */ @@ -807,8 +807,8 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom, /* Step 08 - Set Fun3_RX6B[2:0] to 011b (MSR Enable). */ pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */ - /* Step 09 – Issue MR2 cycle. Read a double word from the address - * depended on DRAM’s Rtt_WR and CWL settings. */ + /* Step 09 - Issue MR2 cycle. Read a double word from the address + * depended on DRAM's Rtt_WR and CWL settings. */ mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl); if (ma_swap) mrs = ddr3_mrs_mirror_pins(mrs); @@ -816,7 +816,7 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom, printram("MR2: %.5x\n", mrs); udelay(1000); - /* Step 10 – Issue MR3 cycle. Read a double word from the address 60000h + /* Step 10 - Issue MR3 cycle. Read a double word from the address 60000h * to set DRAM to normal operation mode. */ mrs = ddr3_get_mr3(0); if (ma_swap) @@ -825,8 +825,8 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom, printram("MR3: %.5x\n", mrs); udelay(1000); - /* Step 11 –Issue MR1 cycle. Read a double word from the address - * depended on DRAM’s output driver impedance and Rtt_Nom settings. + /* Step 11 -Issue MR1 cycle. Read a double word from the address + * depended on DRAM's output driver impedance and Rtt_Nom settings. * The DLL enable field, TDQS field, write leveling enable field, * additive latency field and Qoff field should be set to 0. */ mrs = ddr3_get_mr1(DDR3_MR1_QOFF_ENABLE, DDR3_MR1_TQDS_DISABLE, rtt_nom, @@ -839,7 +839,7 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom, udelay(1000); /* Step 12 - Issue MR0 cycle. Read a double word from the address - * depended on DRAM’s burst length, CAS latency and write recovery time + * depended on DRAM's burst length, CAS latency and write recovery time * settings. * The read burst type field should be set to interleave. * The mode field should be set to normal mode. @@ -942,13 +942,13 @@ static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl, vx900_map_pr_vr(i, 3); } - /* Step 16 – Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ + /* Step 16 - Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */ pci_mod_config8(MCU, 0x6b, 0x07, 0x00); /* Set BA[0/1/2] to [A13/14/15] */ vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP); - /* Step 17 – Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */ + /* Step 17 - Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */ pci_mod_config8(MCU, 0x69, 0x00, (1 << 0)); printram("DIMM initialization sequence complete\n"); diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c index 98e4bd2..e0a54bd 100644 --- a/src/northbridge/via/vx900/sata.c +++ b/src/northbridge/via/vx900/sata.c @@ -199,7 +199,7 @@ static void vx900_sata_init(device_t dev) /* Resend COMRESET When Recovering SATA Gen2 Device Error */ pci_mod_config8(dev, 0x62, 1 << 1, 1 << 7); - /* Fix "PMP Device Can’t Detect HDD Normally" (VIA Porting Guide) + /* Fix "PMP Device Can't Detect HDD Normally" (VIA Porting Guide) * SATA device detection will not work unless we clear these bits. * Without doing this, SeaBIOS (and potentially other payloads) will * timeout when detecting SATA devices */ @@ -211,8 +211,8 @@ static void vx900_sata_init(device_t dev) * reset and check the BSY bit of one port only, and the BSY bit of * other port would be 1, then it does another software reset * immediately and causes the system hang. - * This is because the first software reset doesn’t finish, and the - * state machine of the host controller conflicts, it can’t finish the + * This is because the first software reset doesn't finish, and the + * state machine of the host controller conflicts, it can't finish the * second one anymore. The BSY bit of slave port would be always 1 after * the second software reset issues. BIOS should set the following * bit to avoid this issue. */ diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index b08e3c0..abf034b 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -97,8 +97,8 @@ void PRE_SRX(void) readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); - // Turn on PHY_CONTROL AUTO_OEB ¨C not required - // Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL ¨C already set 180114c8: 000f000a + // Turn on PHY_CONTROL AUTO_OEB C not required + // Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a printk(BIOS_INFO, "\n....PLL power up.\n"); reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN))); diff --git a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl index 232e5bd..4f3a744 100644 --- a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl +++ b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl @@ -19,9 +19,9 @@ Method(_PRT) { /* * PICM comes from _PIC, which returns the following: - * 0 – PIC mode - * 1 – APIC mode - * 2 – SAPIC mode + * 0 - PIC mode + * 1 - APIC mode + * 2 - SAPIC mode */ If (PICM) { Return (Package() { diff --git a/src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl b/src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl index a4ce5ea..8a54d33 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl +++ b/src/soc/intel/fsp_broadwell_de/acpi/irqroute.asl @@ -19,9 +19,9 @@ Method(_PRT) { /* * PICM comes from _PIC, which returns the following: - * 0 – PIC mode - * 1 – APIC mode - * 2 – SAPIC mode + * 0 - PIC mode + * 1 - APIC mode + * 2 - SAPIC mode */ If (PICM) { Return (Package() { diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 4ac4833..276ded2 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -67,7 +67,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; - fadt->sci_int = 9; /* HUDSON - IRQ 09 – ACPI SCI */ + fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index e6572f3..ad47ad7 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -71,7 +71,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; - fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */ + fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 - ACPI SCI */ fadt->smi_cmd = 0; /* disable system management mode */ fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 8a5fbd9..ce8ce6d 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -59,7 +59,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->dsdt = (u32) dsdt; fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; - fadt->sci_int = 9; /* HUDSON - IRQ 09 – ACPI SCI */ + fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 0be526c..e4e5b81 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -782,7 +782,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 8a66369..987d6d1 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index 4943525..e0d19d6 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl b/src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl index 0ec7545..b523a76 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/irqroute.asl @@ -19,9 +19,9 @@ Method(_PRT) { /* * PICM comes from _PIC, which returns the following: - * 0 – PIC mode - * 1 – APIC mode - * 2 – SAPIC mode + * 0 - PIC mode + * 1 - APIC mode + * 2 - SAPIC mode */ If (PICM) { Return (Package() { diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 7004764..326a9e5 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -549,7 +549,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index bcc7641..b128280 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -586,7 +586,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st /* IOTRAP(0) SMIC: currently unused */ printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 9e04328..4f30865 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -409,7 +409,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 6a48277..d4fbed4 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -768,7 +768,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 0ed2ccb..9bdc1eb 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -1003,7 +1003,7 @@ int print_intel_core_msrs(void) /* * The following two tables are the Silvermont registers listed in Table 35-6 - * Intel® 64 and IA-32 Architectures Software Developer’s Manual + * Intel® 64 and IA-32 Architectures Software Developer's Manual * September 2014 * Vol. 3C 35-59 */ diff --git a/util/kconfig/regex.c b/util/kconfig/regex.c index e63c814..428653c 100644 --- a/util/kconfig/regex.c +++ b/util/kconfig/regex.c @@ -120,7 +120,7 @@ init_syntax_once () #define SYNTAX(c) re_syntax_table[c] #endif /* not emacs */ - + /* Get the interface, including the syntax bits. */ #include "regex.h" @@ -168,7 +168,7 @@ init_syntax_once () /* As in Harbison and Steele. */ #define SIGN_EXTEND_CHAR(c) ((((unsigned char) (c)) ^ 128) - 128) #endif - + /* Should we use malloc or alloca? If REGEX_MALLOC is not defined, we use `alloca' instead of `malloc'. This is because using malloc in re_search* or re_match* could cause memory leaks when C-g is used in @@ -236,7 +236,7 @@ char *alloca (); typedef char boolean; #define false 0 #define true 1 - + /* These are the command codes that appear in compiled regular expressions. Some opcodes are followed by argument bytes. A command code can specify any interpretation whatsoever for its @@ -376,7 +376,7 @@ typedef enum notsyntaxspec #endif /* emacs */ } re_opcode_t; - + /* Common operations on the compiled pattern. */ /* Store NUMBER in two contiguous bytes starting at DESTINATION. */ @@ -450,7 +450,7 @@ extract_number_and_incr (destination, source) #endif /* not EXTRACT_MACROS */ #endif /* DEBUG */ - + /* If DEBUG is defined, Regex prints many voluminous messages about what it is doing (if the variable `debug' is nonzero). If linked with the main program in `iregex.c', you can enter patterns and strings @@ -790,7 +790,7 @@ print_double_string (where, string1, size1, string2, size2) #define DEBUG_PRINT_DOUBLE_STRING(w, s1, sz1, s2, sz2) #endif /* not DEBUG */ - + /* Set by `re_set_syntax' to the current regexp syntax to recognize. Can also be assigned to arbitrarily: each pattern buffer stores its own syntax, so it can be changed between regex compilations. */ @@ -813,7 +813,7 @@ re_set_syntax (syntax) re_syntax_options = syntax; return ret; } - + /* This table gives an error message for each of the error codes listed in regex.h. Obviously the order here has to be same as there. */ @@ -836,7 +836,7 @@ static const char *re_error_msg[] = "Regular expression too big", /* REG_ESIZE */ "Unmatched ) or \\)", /* REG_ERPAREN */ }; - + /* Subroutine declarations and macros for regex_compile. */ static void store_op1 (), store_op2 (); @@ -1039,7 +1039,7 @@ typedef struct || STREQ (string, "space") || STREQ (string, "print") \ || STREQ (string, "punct") || STREQ (string, "graph") \ || STREQ (string, "cntrl") || STREQ (string, "blank")) - + /* `regex_compile' compiles PATTERN (of length SIZE) according to SYNTAX. Returns one of error codes defined in `regex.h', or zero for success. @@ -2054,7 +2054,7 @@ regex_compile (pattern, size, syntax, bufp) return REG_NOERROR; } /* regex_compile */ - + /* Subroutines for `regex_compile'. */ /* Store OP at LOC followed by two-byte integer parameter ARG. */ @@ -2240,7 +2240,7 @@ compile_range (p_ptr, pend, translate, syntax, b) return REG_NOERROR; } - + /* Failure stack declarations and macros; both re_compile_fastmap and re_match_2 use a failure stack. These have to be macros because of REGEX_ALLOCATE. */ @@ -2514,7 +2514,7 @@ typedef struct \ DEBUG_STATEMENT (nfailure_points_popped++); \ } /* POP_FAILURE_POINT */ - + /* re_compile_fastmap computes a ``fastmap'' for the compiled pattern in BUFP. A fastmap records which of the (1 << BYTEWIDTH) possible characters can start a string that matches the pattern. This fastmap @@ -2799,7 +2799,7 @@ re_compile_fastmap (bufp) bufp->can_be_null |= path_can_be_null; return 0; } /* re_compile_fastmap */ - + /* Set REGS to hold NUM_REGS registers, storing them in STARTS and ENDS. Subsequent matches using PATTERN_BUFFER and REGS will use this memory for recording register information. STARTS and ENDS @@ -2834,7 +2834,7 @@ re_set_registers (bufp, regs, num_regs, starts, ends) regs->start = regs->end = (regoff_t) 0; } } - + /* Searching routines. */ /* Like re_search_2, below, but only one string is specified, and @@ -2988,7 +2988,7 @@ re_search_2 (bufp, string1, size1, string2, size2, startpos, range, regs, stop) } return -1; } /* re_search_2 */ - + /* Declarations and macros for re_match_2. */ static int bcmp_translate (); @@ -3126,7 +3126,7 @@ typedef union to actually save any registers when none are active. */ #define NO_HIGHEST_ACTIVE_REG (1 << BYTEWIDTH) #define NO_LOWEST_ACTIVE_REG (NO_HIGHEST_ACTIVE_REG + 1) - + /* Matching routines. */ #ifndef emacs /* Emacs never uses this. */ @@ -4339,7 +4339,7 @@ re_match_2 (bufp, string1, size1, string2, size2, pos, regs, stop) return -1; /* Failure to match. */ } /* re_match_2 */ - + /* Subroutine definitions for re_match_2. */ @@ -4601,7 +4601,7 @@ bcmp_translate (s1, s2, len, translate) } return 0; } - + /* Entry points for GNU code. */ /* re_compile_pattern is the GNU regular expression compiler: it @@ -4637,7 +4637,7 @@ re_compile_pattern (pattern, length, bufp) return re_error_msg[(int) ret]; } - + /* Entry points compatible with 4.2 BSD regex library. We don't define them if this is an Emacs or POSIX compilation. */ @@ -4693,7 +4693,7 @@ re_exec (s) 0 <= re_search (&re_comp_buf, s, len, 0, len, (struct re_registers *) 0); } #endif /* not emacs and not _POSIX_SOURCE */ - + /* POSIX.2 functions. Don't define these for Emacs. */ #ifndef emacs @@ -4938,7 +4938,7 @@ regfree (preg) } #endif /* not emacs */ - + /* Local variables: make-backup-files: t diff --git a/util/kconfig/regex.h b/util/kconfig/regex.h index 9124397..89e02d4 100644 --- a/util/kconfig/regex.h +++ b/util/kconfig/regex.h @@ -135,7 +135,7 @@ typedef unsigned reg_syntax_t; stored in the pattern buffer, so changing this does not affect already-compiled regexps. */ extern reg_syntax_t re_syntax_options; - + /* Define combinations of the above bits for the standard possibilities. (The [[[ comments delimit what gets put into the Texinfo file, so don't delete them!) */ @@ -198,7 +198,7 @@ extern reg_syntax_t re_syntax_options; | RE_NO_BK_PARENS | RE_NO_BK_REFS \ | RE_NO_BK_VBAR | RE_UNMATCHED_RIGHT_PAREN_ORD) /* [[[end syntaxes]]] */ - + /* Maximum number of duplicates an interval can allow. Some systems (erroneously) define this in other header files, but we want our value, so remove any previous define. */ @@ -268,7 +268,7 @@ typedef enum REG_ESIZE, /* Compiled pattern bigger than 2^16 bytes. */ REG_ERPAREN /* Unmatched ) or \); not returned from regcomp. */ } reg_errcode_t; - + /* This data structure represents a compiled pattern. Before calling the pattern compiler, the fields `buffer', `allocated', `fastmap', `translate', and `no_sub' can be set. After the pattern has been @@ -349,7 +349,7 @@ typedef struct re_pattern_buffer regex_t; /* search.c (search_buffer) in Emacs needs this one opcode value. It is defined both in `regex.c' and here. */ #define RE_EXACTN_VALUE 1 - + /* Type for byte offsets within the string. POSIX mandates this. */ typedef int regoff_t; @@ -380,7 +380,7 @@ typedef struct regoff_t rm_so; /* Byte offset from string's start to substring's start. */ regoff_t rm_eo; /* Byte offset from string's start to substring's end. */ } regmatch_t; - + /* Declarations for routines. */ /* To avoid duplicating every routine declaration -- once with a @@ -480,7 +480,7 @@ extern size_t regerror extern void regfree _RE_ARGS ((regex_t *preg)); #endif /* not __REGEXP_LIBRARY_H__ */ - + /* Local variables: make-backup-files: t

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Cache cbmem region
by Andrey Petrov 30 Jul '16

30 Jul '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15456 -gerrit commit d115cc2ed1ac97287125ffa7ec32ebde3efc3244 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 24 18:40:28 2016 -0700 WIP: soc/intel/apollolake: Cache cbmem region Configure write-back MTRRs so that 8 MiB under cbmem_top is cached. This allows caching of FSP reserved memory and postcar stage itself. On CAR teardown the memory is flushed with clflush instruction. Depending on what cache configuration is used, either L1 (NEM) or both L1 and L2 (CQOS) storage is used for caching purposes. This is WIP patch, because currently location of cbmem_top can not be known before memory is trained. So addresses are hardcoded. BUG=chrome-os-partner:51959 TEST=boot, notice cbmem showing MemoryInit getting ~140ms faster Change-Id: I62aad238a3056f9bbe5327dfb33a2a1112d61194 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/exit_car.S | 8 ++++++++ src/soc/intel/apollolake/romstage.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index 86aadf5d..e5e8194 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -33,6 +33,14 @@ chipset_teardown_car: and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr + /* Flush all cache lines into the DRAM. */ + mov $0x7a800000, %eax +loop: + clflush (%eax) + add $CACHE_LINE_SIZE, %eax + cmp $0x7b000000, %eax + jl loop + #if IS_ENABLED(CONFIG_CAR_CQOS) mov $MTRR_L2_QOS_MASK(0), %ecx rdmsr diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index da7fcf1..b8aa52e 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -104,6 +104,7 @@ asmlinkage void car_stage_entry(void) struct postcar_frame pcf; uintptr_t top_of_ram; bool s3wake; + int mtrr; struct chipset_power_state *ps = car_get_var_ptr(&power_state); timestamp_add_now(TS_START_ROMSTAGE); @@ -115,6 +116,13 @@ asmlinkage void car_stage_entry(void) s3wake = fill_power_state(ps) == ACPI_S3; + mtrr = get_free_var_mtrr(); + if (mtrr==-1) + printk(BIOS_CRIT, "no available MTRRs to cache cbmem!\n"); + else + /* Make sure cbmem 8 MiB under CBMEM is cachable */ + set_var_mtrr(mtrr, 0x7a800000, 8*MiB, MTRR_TYPE_WRBACK); + if (fsp_memory_init(s3wake) != FSP_SUCCESS) { die("FSP memory init failed. Giving up."); }

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Patch set updated for coreboot: WIP: soc/intel/apollolake: Handle CAR sizes other than 1MiB
by Andrey Petrov 30 Jul '16

30 Jul '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15453 -gerrit commit aa79c97f8125715ab85a29d96e6e1065b90203bd Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 15:21:26 2016 -0700 WIP: soc/intel/apollolake: Handle CAR sizes other than 1MiB Since whole L2 (1MiB) is not used, it is possible to shrink CAR size to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to setup it. This is a part of preparation for CQOS enabling. BUG=chrome-os-partner:51959 Change-Id: I56326a1790df202a0e428e092dd90286c58763c5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 2 +- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 27 +++++++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0745679..3c0b588 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -94,7 +94,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x100000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 8647206..eee458d 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -17,6 +17,7 @@ */ #include <device/pci_def.h> +#include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> @@ -70,6 +71,7 @@ clear_var_mtrr: post_code(0x24) +#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) /* Configure CAR region as write-back (WB) */ mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax @@ -82,6 +84,31 @@ clear_var_mtrr: mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ or $MTRR_PHYS_MASK_VALID, %eax wrmsr +#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(0), %ecx + mov $~(512 * KiB - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + mov $MTRR_PHYS_BASE(1), %ecx + mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + mov $MTRR_PHYS_MASK(1), %ecx + mov $~(0x256 * KiB - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr +#else +#error "DCACHE_RAM_SIZE is not power of 2, and we don't know how to handle this value" +#endif post_code(0x25)

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Patch set updated for coreboot: soc/intel/apollolake: Add CQOS CAR implementation
by Andrey Petrov 30 Jul '16

30 Jul '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15455 -gerrit commit 7fd0b227e219e2804030eff129cbed0bf76d3ed0 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Jun 27 13:39:34 2016 -0700 soc/intel/apollolake: Add CQOS CAR implementation Add new Cache Quality of Service option that allows to configure cache non-evict mode by manipulating CQOS settings. Also, CQOS allows using cache non-evict mode simultaneously with regular evicting caching. BUG=chrome-os-partner:51959 Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 22 +++++++++ src/soc/intel/apollolake/bootblock/bootblock.c | 4 ++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 55 ++++++++++++++++++++++- src/soc/intel/apollolake/car.c | 7 +++ src/soc/intel/apollolake/exit_car.S | 24 +++++++++- src/soc/intel/apollolake/include/soc/cpu.h | 19 ++++++++ 6 files changed, 127 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index dbf7d51..657ed56 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -224,5 +224,27 @@ config NHLT_DA7219 default n help Include DSP firmware settings for headset codec. +choice + prompt "Cache-as-ram implementation" + default CAR_CQOS + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config CAR_NEM + bool "Non-evict mode" + help + Traditionally, CAR is set up by using Non-Evict mode. This method + does not allow CAR and cache to co-exist, because cache fills are + block in NEM mode. + + +config CAR_CQOS + bool "Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up portion of L2 cache for + CAR and use remainded for actual caching. + +endchoice endif diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 31144ff..03408b6 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -171,5 +171,9 @@ void bootblock_soc_early_init(void) enable_spibar(); +#if IS_ENABLED(CONFIG_CAR_CQOS) + cache_qos_select_mask(1); +#endif + cache_bios_region(); } diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index eee458d..1065f48 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -103,11 +103,11 @@ clear_var_mtrr: wrmsr mov $MTRR_PHYS_MASK(1), %ecx - mov $~(0x256 * KiB - 1), %eax /* size mask */ + mov $~(256 * KiB - 1), %eax /* size mask */ or $MTRR_PHYS_MASK_VALID, %eax wrmsr #else -#error "DCACHE_RAM_SIZE is not power of 2, and we don't know how to handle this value" +#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing" #endif post_code(0x25) @@ -124,12 +124,55 @@ clear_var_mtrr: invd mov %eax, %cr0 +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr +#else + /* + * Disable both L1 and L2 prefetcher. For yet-to-understood reason, + * prefetchers slow down filling cache with rep stos in CQOS mode. + */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr +#endif + +#if IS_ENABLED(CONFIG_CAR_CQOS) +#if (CONFIG_DCACHE_RAM_SIZE == L2_CACHE_SIZE) +/* + * If CAR size is set to full L2 size, mask is calculated as all-zeros. + * This is not supported by the CPU/uCode. + */ +#error "CQOS CAR may not use whole L2 cache area" +#endif + /* Calculate how many bits to be used for CAR */ + xor %edx, %edx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */ + mov $CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */ + div %ecx /* result is in eax */ + mov %eax, %ecx /* save to ecx */ + mov $1, %ebx + shl %cl, %ebx + sub $1, %ebx /* resulting mask is is in ebx */ + + /* Mask 0 is used for CAR */ + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + mov %ebx, %eax + wrmsr + /* Mask 1 is used for evicatable cache */ + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov %ebx, %eax + xor $~0, %al /* invert 8 bits */ + wrmsr +#endif post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ @@ -140,11 +183,19 @@ clear_var_mtrr: post_code(0x27) +#if IS_ENABLED(CONFIG_CAR_NEM) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr +#else + /* Enable prefetchers */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr +#endif post_code(0x28) diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index 68bcb31..bb96419 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -56,3 +56,10 @@ void platform_segment_loaded(uintptr_t start, size_t size, int flags) flush_l1d_to_l2(); } + +void cache_qos_select_mask(uint8_t mask) +{ + msr_t msr = rdmsr(MTRR_IA32_PQR_ASSOC); + msr.hi |= mask; + wrmsr(MTRR_IA32_PQR_ASSOC, msr); +} diff --git a/src/soc/intel/apollolake/exit_car.S b/src/soc/intel/apollolake/exit_car.S index 339242b..86aadf5d 100644 --- a/src/soc/intel/apollolake/exit_car.S +++ b/src/soc/intel/apollolake/exit_car.S @@ -27,14 +27,33 @@ chipset_teardown_car: */ pop %ebx - /* invalidate cache contents. */ - invd /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx rdmsr and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax wrmsr +#if IS_ENABLED(CONFIG_CAR_CQOS) + mov $MTRR_L2_QOS_MASK(0), %ecx + rdmsr + mov $~0, %al + wrmsr + + mov $MTRR_L2_QOS_MASK(1), %ecx + rdmsr + mov $~0, %al + wrmsr + + /* reset CLOS selector */ + mov $MTRR_IA32_PQR_ASSOC, %ecx + rdmsr + and $~(1 << 0 | 1 << 1), %edx + wrmsr +#endif + /* invalidate cache contents. */ + invd + +#if IS_ENABLED(CONFIG_CAR_NEM) /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ mov $(MSR_EVICT_CTL), %ecx rdmsr @@ -42,6 +61,7 @@ chipset_teardown_car: wrmsr and $(~(1 << 0)), %eax wrmsr +#endif /* Return to caller. */ jmp *%ebx diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 78fc0b0..388eca7 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -23,6 +23,7 @@ #include <device/device.h> void apollolake_init_cpus(struct device *dev); +void cache_qos_select_mask(uint8_t mask); #endif #define CPUID_APOLLOLAKE_A0 0x506c8 @@ -34,6 +35,24 @@ void apollolake_init_cpus(struct device *dev); #define MSR_EVICT_CTL 0x2e0 #define MSR_EMULATE_PM_TMR 0x121 #define EMULATE_PM_TMR_EN (1 << 16) +#define MSR_PREFETCH_CTL 0x1a4 +#define PREFETCH_L1_DISABLE (1 << 0) +#define PREFETCH_L2_DISABLE (1 << 2) + + +#define MTRR_L2_QOS_MASK(reg) (0xd10 + reg) +#define MTRR_IA32_PQR_ASSOC 0xc8f +/* 16 way cache, 8 bits per QOS, 64 byte cache line, 1024 sets */ +#define CACHE_WAYS 16 +#define CACHE_BITS_PER_MASK 8 +#define CACHE_LINE_SIZE 64 +#define CACHE_SETS 1024 +/* + * Each bit in QOS mask controls this many bytes. This is calculated as: + * (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS + */ +#define CACHE_QOS_SIZE_PER_BIT 128 * KiB +#define L2_CACHE_SIZE 0x100000 #define BASE_CLOCK_MHZ 100

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coreboot-gerrit July 2016