coreboot-gerrit July 2016

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Patch set updated for coreboot: spi/tpm: read TPM version in larger chunks
by Vadim Bendebury 31 Jul '16

31 Jul '16

Vadim Bendebury (vbendeb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16000 -gerrit commit dd5b4565b4b9fd4b9c58448b62532dff90dc9ab9 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sun Jul 31 11:19:20 2016 -0700 spi/tpm: read TPM version in larger chunks The TPM version string has become much longer recently, and the TPM_FW_VER register available on VID 1ae0 devices supports reading in arbitrary size quantities. Let's read 50 bytes at a time to reduce the SPI register read wrapper overhead. TEST=verified on the Kevin device: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:* cr50_v1.1.5005-444ddb7 RW_B: cr50_v1.1.5005-5aac83c cr50_v1.1.5005-444ddb7 private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735 cryptoc:v0.0.4-5319e83 2016-07-31 10:58:05 vbendeb@kvasha Change-Id: Ifaf28c1a9a3990372a9cec108c098edbe50d3243 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/drivers/spi/tpm/tpm.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 4de62d9..a63bc9b 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -359,8 +359,14 @@ int tpm2_init(struct spi_slave *spi_if) /* Let's report device FW version if available. */ if (tpm_info.vendor_id == 0x1ae0) { int chunk_count = 0; - uint32_t chunk = 0; - char vstr[sizeof(chunk) + 1]; /* room for 4 chars + zero */ + size_t chunk_size; + /* + * let's read 50 bytes at a time; leave room for the trailing + * zero. + */ + char vstr[51]; + + chunk_size = sizeof(vstr) - 1; printk(BIOS_INFO, "Firmware version: "); @@ -368,21 +374,20 @@ int tpm2_init(struct spi_slave *spi_if) * Does not really matter what's written, this just makes sure * the version is reported from the beginning. */ - tpm2_write_reg(TPM_FW_VER, &chunk, sizeof(chunk)); + tpm2_write_reg(TPM_FW_VER, &chunk_size, sizeof(chunk_size)); - /* Print it out in 4 byte chunks. */ - vstr[sizeof(vstr) - 1] = 0; + /* Print it out in sizeof(vstr) - 1 byte chunks. */ + vstr[chunk_size] = 0; do { - tpm2_read_reg(TPM_FW_VER, vstr, sizeof(chunk)); + tpm2_read_reg(TPM_FW_VER, vstr, chunk_size); printk(BIOS_INFO, "%s", vstr); /* - * While string is not over, and no more than 200 + * While string is not over, and is no longer than 300 * characters. - * This is likely result in one extra printk() - * invocation with an empty string, not a big deal. */ - } while (vstr[0] && (chunk_count++ < (200 / sizeof(chunk)))); + } while (vstr[chunk_size - 1] && + (chunk_count++ < (300 / chunk_size))); printk(BIOS_INFO, "\n"); }

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New patch to review for coreboot: spi/tpm: read TPM version in larger chunks
by Vadim Bendebury 31 Jul '16

31 Jul '16

Vadim Bendebury (vbendeb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16000 -gerrit commit 393781e43c8f3f4f073f009a04437b0fd25268c7 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sun Jul 31 11:19:20 2016 -0700 spi/tpm: read TPM version in larger chunks The TPM version string has become much longer recently, and the TPM_FW_VER register available on VID 1ae0 devices supports reading in arbitrary size quantities. Let's read 50 bytes at a time to reduce the SPI register read wrapper overhead. TEST=verified on the Kevin device: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:* cr50_v1.1.5005-444ddb7 RW_B: cr50_v1.1.5005-5aac83c cr50_v1.1.5005-444ddb7 private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735 cryptoc:v0.0.4-5319e83 2016-07-31 10:58:05 vbendeb@kvasha Change-Id: Ifaf28c1a9a3990372a9cec108c098edbe50d3243 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/drivers/spi/tpm/tpm.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 4de62d9..b038eda 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -359,8 +359,10 @@ int tpm2_init(struct spi_slave *spi_if) /* Let's report device FW version if available. */ if (tpm_info.vendor_id == 0x1ae0) { int chunk_count = 0; - uint32_t chunk = 0; - char vstr[sizeof(chunk) + 1]; /* room for 4 chars + zero */ + size_t chunk_size; + char vstr[51]; /* let's read 50 bytes at a time, leave room for the trailing zero. */ + + chunk_size = sizeof(vstr) - 1; printk(BIOS_INFO, "Firmware version: "); @@ -368,21 +370,20 @@ int tpm2_init(struct spi_slave *spi_if) * Does not really matter what's written, this just makes sure * the version is reported from the beginning. */ - tpm2_write_reg(TPM_FW_VER, &chunk, sizeof(chunk)); + tpm2_write_reg(TPM_FW_VER, &chunk_size, sizeof(chunk_size)); - /* Print it out in 4 byte chunks. */ - vstr[sizeof(vstr) - 1] = 0; + /* Print it out in sizeof(vstr) - 1 byte chunks. */ + vstr[chunk_size] = 0; do { - tpm2_read_reg(TPM_FW_VER, vstr, sizeof(chunk)); + tpm2_read_reg(TPM_FW_VER, vstr, chunk_size); printk(BIOS_INFO, "%s", vstr); /* - * While string is not over, and no more than 200 + * While string is not over, and is no longer than 300 * characters. - * This is likely result in one extra printk() - * invocation with an empty string, not a big deal. */ - } while (vstr[0] && (chunk_count++ < (200 / sizeof(chunk)))); + } while (vstr[chunk_size - 1] && + (chunk_count++ < (300 / chunk_size))); printk(BIOS_INFO, "\n"); }

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Patch merged into coreboot/master: libpayload: fix leak in libcbfs
by gerrit＠coreboot.org 31 Jul '16

31 Jul '16

the following patch was just integrated into master: commit 33ab4fea23d8e57b4abab0e10d556ff6344ecf37 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Jul 29 16:36:23 2016 +0200 libpayload: fix leak in libcbfs stage wasn't freed on errors. Change-Id: I10d2f42f3e484955619addbef2898981f6f90a35 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1347345 Reviewed-on: https://review.coreboot.org/15958 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15958 for details. -gerrit

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Patch merged into coreboot/master: mainboard/bap/ode_e20XX: Enable UART 3/4 in devicetree
by gerrit＠coreboot.org 31 Jul '16

31 Jul '16

the following patch was just integrated into master: commit 41b3196bc88b0c869bba0f3e806904c390341306 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Tue Jul 12 11:32:37 2016 +0200 mainboard/bap/ode_e20XX: Enable UART 3/4 in devicetree This patch adds IO and IRQ information for UART 3/4 to the devicetree. Patch with Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e is needed. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: I1d8fa16950079a47775f48166486415bd5d24f42 Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15621 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15621 for details. -gerrit

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Patch merged into coreboot/master: mainboard/bap/ode_e20XX: Add different DDR3 clk settings
by gerrit＠coreboot.org 31 Jul '16

31 Jul '16

the following patch was just integrated into master: commit 8cab72e1d857d430b5c9c4b748f4b46a84374168 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Tue Jul 26 22:46:23 2016 +0200 mainboard/bap/ode_e20XX: Add different DDR3 clk settings This patch adds two SPD files with different DDR3 clk settings. The user can choose which setting to use. Lower clk settings saves power under load. SoC Model GX-411GA supports only up to DDR3-1066 clk mode. Both SPD settings were tested with memtest for several hours. Power saving is around half a watt under heavy memory load. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: Ibb81e22e19297fdf64360bc3e213529e9d183586 Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15907 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15907 for details. -gerrit

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Patch merged into coreboot/master: mainboard/bap/ode_e20XX: Change PCIe lines
by gerrit＠coreboot.org 31 Jul '16

31 Jul '16

the following patch was just integrated into master: commit 1f9c07fcd735e2e55104d1b3a2672298a460d5fb Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Tue Jul 26 22:11:07 2016 +0200 mainboard/bap/ode_e20XX: Change PCIe lines This patch binds PCIe lanes 2 and 3 to one PCIe device. PCIe device 2.4 becomes x2. Tested with the connected FPGA on PCIe 2.4. FPGA doubles transfer rate from/to the AMD. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: Icee567272312a7df4c3b5a6db5b420a054ec3230 Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15905 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15905 for details. -gerrit

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Patch merged into coreboot/master: superio/nuvoton: Add Nuvoton NCT6791D
by gerrit＠coreboot.org 31 Jul '16

31 Jul '16

the following patch was just integrated into master: commit 449fb9b6eb886a6bd364f9f5c5617e30152c013d Author: Omar Pakker <omarpakker+coreboot(a)gmail.com> Date: Fri Jul 29 19:05:33 2016 +0200 superio/nuvoton: Add Nuvoton NCT6791D This adds support for Nuvoton NCT6791D Super I/O chips. Makes use of the common Nuvoton early_serial.c. Based on the Datasheet supplied by Nuvoton. Datasheet Version: January 8th, 2016 Revision 1.11 Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40 Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com> Reviewed-on: https://review.coreboot.org/15967 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See https://review.coreboot.org/15967 for details. -gerrit

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Patch merged into coreboot/master: src/vboot: Capitalize RAM and CPU
by gerrit＠coreboot.org 31 Jul '16

31 Jul '16

the following patch was just integrated into master: commit 2a600263dcd49249467bec43c483ddfae91a4cde Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Jul 30 16:18:46 2016 +0200 src/vboot: Capitalize RAM and CPU Change-Id: Iff6b1b08b8159588b964d9637b16e1e0bfcca940 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/15986 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15986 for details. -gerrit

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Patch merged into coreboot/master: src/lib: Capitalize ROM, RAM, NVRAM and CPU
by gerrit＠coreboot.org 31 Jul '16

31 Jul '16

the following patch was just integrated into master: commit 91e0e3ccbe9e2ed7cf91a94e03ee576598e63f54 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Jul 30 15:51:13 2016 +0200 src/lib: Capitalize ROM, RAM, NVRAM and CPU Change-Id: Id0871b0c2eb31e2d728180b44cc5b518b751add4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/15985 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15985 for details. -gerrit

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Patch merged into coreboot/master: src/drivers: Capitalize CPU, RAM and ACPI
by gerrit＠coreboot.org 31 Jul '16

31 Jul '16

the following patch was just integrated into master: commit 7753731f0cce2216574756e3e0101e4166fa3ef3 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Jul 30 15:37:26 2016 +0200 src/drivers: Capitalize CPU, RAM and ACPI Change-Id: I720469ea1df75544f5b1e0cab718502d8a9cf197 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/15983 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15983 for details. -gerrit

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coreboot-gerrit July 2016