Patch merged into coreboot/master: util/chromeos: Make scripts executable
by gerrit＠coreboot.org 30 Jul '16
by gerrit＠coreboot.org 30 Jul '16
30 Jul '16
the following patch was just integrated into master:
commit 28434a9ca7d13e1046212ddc0941ebd23f768af8
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Jul 27 13:08:25 2016 -0700
util/chromeos: Make scripts executable
crosfirmware.sh and extract_blobs.sh are not executable, change that.
Change-Id: Ib04df580a9acd4a422aedbdc15013b2ef505459a
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-on: https://review.coreboot.org/15922
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/15922 for details.
-gerrit
1
0
Patch set updated for coreboot: src/mainboard: Capitalize ROM, RAM, CPU and APIC
by HAOUAS Elyes 30 Jul '16
by HAOUAS Elyes 30 Jul '16
30 Jul '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15987
-gerrit
commit 9f84a07c49c4c59634c997257bb1a9c0f668cfab
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Sat Jul 30 17:46:17 2016 +0200
src/mainboard: Capitalize ROM, RAM, CPU and APIC
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/mainboard/amd/db-ft3b-lc/Makefile.inc | 2 +-
src/mainboard/amd/db800/irq_tables.c | 2 +-
src/mainboard/amd/dbm690t/fadt.c | 2 +-
src/mainboard/amd/dinar/buildOpts.c | 4 ++--
src/mainboard/amd/dinar/romstage.c | 2 +-
src/mainboard/amd/f2950/irq_tables.c | 2 +-
src/mainboard/amd/inagua/buildOpts.c | 4 ++--
src/mainboard/amd/norwich/irq_tables.c | 2 +-
src/mainboard/amd/parmer/buildOpts.c | 4 ++--
src/mainboard/amd/persimmon/buildOpts.c | 4 ++--
src/mainboard/amd/pistachio/fadt.c | 2 +-
src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl | 2 +-
src/mainboard/amd/serengeti_cheetah/fadt.c | 2 +-
src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 2 +-
src/mainboard/amd/serengeti_cheetah/readme_acpi.txt | 2 +-
src/mainboard/amd/serengeti_cheetah/romstage.c | 2 +-
.../amd/serengeti_cheetah_fam10/acpi/amd8111.asl | 2 +-
src/mainboard/amd/serengeti_cheetah_fam10/fadt.c | 2 +-
.../amd/serengeti_cheetah_fam10/get_bus_conf.c | 2 +-
src/mainboard/amd/south_station/buildOpts.c | 4 ++--
src/mainboard/amd/thatcher/buildOpts.c | 4 ++--
src/mainboard/amd/torpedo/buildOpts.c | 4 ++--
src/mainboard/amd/torpedo/fadt.c | 2 +-
src/mainboard/amd/torpedo/mptable.c | 2 +-
src/mainboard/amd/union_station/buildOpts.c | 4 ++--
src/mainboard/apple/macbook21/cmos.layout | 2 +-
src/mainboard/artecgroup/dbe61/irq_tables.c | 2 +-
src/mainboard/asrock/e350m1/buildOpts.c | 4 ++--
src/mainboard/asus/f2a85-m/buildOpts.c | 4 ++--
src/mainboard/asus/f2a85-m_le/buildOpts.c | 4 ++--
src/mainboard/asus/kcma-d8/resourcemap.c | 8 ++++----
src/mainboard/asus/kcma-d8/romstage.c | 2 +-
src/mainboard/asus/kfsn4-dre/resourcemap.c | 4 ++--
src/mainboard/asus/kfsn4-dre_k8/resourcemap.c | 4 ++--
src/mainboard/asus/kgpe-d16/resourcemap.c | 8 ++++----
src/mainboard/asus/kgpe-d16/romstage.c | 2 +-
src/mainboard/asus/m2n-e/resourcemap.c | 2 +-
src/mainboard/asus/p2b/dsdt.asl | 2 +-
src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex | 2 +-
src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex | 2 +-
src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex | 2 +-
src/mainboard/bap/ode_e21XX/Makefile.inc | 2 +-
src/mainboard/emulation/qemu-armv7/media.c | 2 +-
.../emulation/qemu-i440fx/acpi/cpu-hotplug.asl | 4 ++--
src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 18 +++++++++---------
src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 ++--
src/mainboard/emulation/qemu-power8/mainboard.c | 2 +-
src/mainboard/getac/p470/cmos.layout | 2 +-
src/mainboard/getac/p470/cstates.c | 6 +++---
src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c | 2 +-
src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 +-
src/mainboard/gigabyte/m57sli/resourcemap.c | 2 +-
src/mainboard/gigabyte/m57sli/romstage.c | 2 +-
src/mainboard/gizmosphere/gizmo/Makefile.inc | 2 +-
src/mainboard/gizmosphere/gizmo/buildOpts.c | 4 ++--
src/mainboard/gizmosphere/gizmo2/Makefile.inc | 2 +-
src/mainboard/google/auron/spd/Makefile.inc | 2 +-
src/mainboard/google/auron_paine/spd/Makefile.inc | 2 +-
src/mainboard/google/chell/spd/Makefile.inc | 2 +-
src/mainboard/google/cyan/spd/Makefile.inc | 2 +-
src/mainboard/google/falco/Makefile.inc | 2 +-
src/mainboard/google/glados/spd/Makefile.inc | 2 +-
src/mainboard/google/lars/spd/Makefile.inc | 2 +-
src/mainboard/google/link/Makefile.inc | 2 +-
src/mainboard/google/ninja/spd/Makefile.inc | 2 +-
src/mainboard/google/peppy/Makefile.inc | 2 +-
src/mainboard/google/rambi/spd/Makefile.inc | 2 +-
src/mainboard/google/samus/spd/Makefile.inc | 2 +-
src/mainboard/hp/dl145_g1/acpi/amd8111.asl | 2 +-
src/mainboard/hp/dl145_g1/dsdt.asl | 2 +-
src/mainboard/hp/dl145_g1/fadt.c | 2 +-
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 4 ++--
src/mainboard/ibase/mb899/cmos.layout | 2 +-
src/mainboard/intel/d945gclf/cmos.layout | 2 +-
src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +-
src/mainboard/iwave/iWRainbowG6/cmos.layout | 2 +-
src/mainboard/iwill/dk8_htx/acpi/amd8111.asl | 2 +-
src/mainboard/iwill/dk8_htx/fadt.c | 2 +-
src/mainboard/iwill/dk8_htx/get_bus_conf.c | 2 +-
src/mainboard/iwill/dk8_htx/romstage.c | 2 +-
src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 4 ++--
src/mainboard/kontron/986lcd-m/cmos.layout | 2 +-
src/mainboard/kontron/kt690/fadt.c | 2 +-
src/mainboard/lenovo/g505s/buildOpts.c | 4 ++--
src/mainboard/lenovo/t400/cmos.layout | 2 +-
src/mainboard/lenovo/t400/cstates.c | 4 ++--
src/mainboard/lenovo/t60/cmos.layout | 2 +-
src/mainboard/lenovo/x200/cmos.layout | 2 +-
src/mainboard/lenovo/x200/cstates.c | 4 ++--
src/mainboard/lenovo/x60/cmos.layout | 2 +-
src/mainboard/lippert/frontrunner-af/buildOpts.c | 4 ++--
src/mainboard/lippert/toucan-af/buildOpts.c | 4 ++--
src/mainboard/msi/ms7260/resourcemap.c | 2 +-
src/mainboard/msi/ms9652_fam10/resourcemap.c | 2 +-
src/mainboard/nvidia/l1_2pvv/get_bus_conf.c | 2 +-
src/mainboard/nvidia/l1_2pvv/resourcemap.c | 4 ++--
src/mainboard/nvidia/l1_2pvv/romstage.c | 2 +-
src/mainboard/pcengines/apu1/Makefile.inc | 2 +-
src/mainboard/pcengines/apu1/buildOpts.c | 4 ++--
src/mainboard/roda/rk886ex/cmos.layout | 2 +-
src/mainboard/roda/rk886ex/m3885.c | 6 +++---
src/mainboard/roda/rk9/cmos.layout | 2 +-
src/mainboard/roda/rk9/cstates.c | 4 ++--
src/mainboard/roda/rk9/mainboard.c | 2 +-
src/mainboard/samsung/lumpy/Makefile.inc | 2 +-
src/mainboard/siemens/sitemp_g1p1/fadt.c | 2 +-
src/mainboard/sunw/ultra40/get_bus_conf.c | 2 +-
src/mainboard/sunw/ultra40m2/get_bus_conf.c | 2 +-
src/mainboard/sunw/ultra40m2/resourcemap.c | 4 ++--
src/mainboard/sunw/ultra40m2/romstage.c | 2 +-
src/mainboard/supermicro/h8dme/resourcemap.c | 2 +-
src/mainboard/supermicro/h8dme/romstage.c | 2 +-
src/mainboard/supermicro/h8dmr/resourcemap.c | 2 +-
src/mainboard/supermicro/h8dmr/romstage.c | 2 +-
src/mainboard/supermicro/h8dmr_fam10/resourcemap.c | 2 +-
src/mainboard/supermicro/h8qgi/romstage.c | 2 +-
src/mainboard/supermicro/h8qme_fam10/resourcemap.c | 2 +-
src/mainboard/supermicro/h8scm/romstage.c | 2 +-
src/mainboard/technexion/tim5690/fadt.c | 2 +-
src/mainboard/technexion/tim8690/fadt.c | 2 +-
src/mainboard/traverse/geos/irq_tables.c | 2 +-
src/mainboard/tyan/s2912/resourcemap.c | 4 ++--
src/mainboard/tyan/s2912/romstage.c | 2 +-
src/mainboard/tyan/s2912_fam10/resourcemap.c | 4 ++--
src/mainboard/tyan/s8226/romstage.c | 2 +-
src/mainboard/winent/pl6064/irq_tables.c | 2 +-
126 files changed, 173 insertions(+), 173 deletions(-)
diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
index 8b160e2..97c761f 100644
--- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc
+++ b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
@@ -27,7 +27,7 @@ SPD_SOURCES = Memphis_MEM4G16D3EABG
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/amd/db800/irq_tables.c b/src/mainboard/amd/db800/irq_tables.c
index 00a19db..8cf172a 100644
--- a/src/mainboard/amd/db800/irq_tables.c
+++ b/src/mainboard/amd/db800/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */
diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/amd/dbm690t/fadt.c
+++ b/src/mainboard/amd/dbm690t/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index 3fd9c48..e237ff0 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -54,10 +54,10 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-/* Select the cpu family. */
+/* Select the CPU family. */
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT TRUE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 70cd5e3..bc5d312 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43);
- printk(BIOS_DEBUG, "Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as RAM ");
disable_cache_as_ram();
printk(BIOS_DEBUG, "done\n");
diff --git a/src/mainboard/amd/f2950/irq_tables.c b/src/mainboard/amd/f2950/irq_tables.c
index b438f02..dae29a1 100644
--- a/src/mainboard/amd/f2950/irq_tables.c
+++ b/src/mainboard/amd/f2950/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
}
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index ffaf79a..1cefc69 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/norwich/irq_tables.c b/src/mainboard/amd/norwich/irq_tables.c
index dfb1ef4..a59dc26 100644
--- a/src/mainboard/amd/norwich/irq_tables.c
+++ b/src/mainboard/amd/norwich/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 11d36bc..dc1c705 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -30,13 +30,13 @@
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index fe4e779..2377827 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/amd/pistachio/fadt.c
+++ b/src/mainboard/amd/pistachio/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
index cc9b65b..aaa778b 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
+++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
@@ -61,7 +61,7 @@
Device (SBC3)
{
- /* acpi smbus it should be 0x00040003 if 8131 present */
+ /* ACPI smbus it should be 0x00040003 if 8131 present */
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c
index 4fe4efd..bd00961 100644
--- a/src/mainboard/amd/serengeti_cheetah/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah/fadt.c
@@ -21,7 +21,7 @@
#include <console/console.h>
#include <arch/acpi.h>
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
index 0492e9a..1eb97b5 100644
--- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
@@ -77,7 +77,7 @@ static unsigned get_hcid(unsigned i)
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
index b999dfa..0dbf303 100644
--- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
+++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
@@ -1,4 +1,4 @@
-At this time, For acpi support We got
+At this time, For ACPI support We got
1. support AMK K8 SRAT --- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
2. support MADT ---- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{acpi/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index ded74a5..51fce31 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -224,5 +224,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
index 46fe121..f6a1954 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
@@ -53,7 +53,7 @@
Device (SBC3)
{
- // acpi smbus it should be 0x00040003 if 8131 present
+ // ACPI smbus it should be 0x00040003 if 8131 present
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
index 544df8e..3183a7e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
@@ -24,7 +24,7 @@
#include <console/console.h>
#include <arch/acpi.h>
-extern u32 pm_base; /* pm_base should be set in sb acpi */
+extern u32 pm_base; /* pm_base should be set in sb ACPI */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index 6113f0e..66dee18 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -81,7 +81,7 @@ static u32 get_hcid(u32 i)
break;
}
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 2f696ef..05c3a38 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 45569df..bd43181 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -30,13 +30,13 @@
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index 40f1f97..c80b7d9 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -31,13 +31,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT TRUE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c
index 9a615c1..fba8fc8 100644
--- a/src/mainboard/amd/torpedo/fadt.c
+++ b/src/mainboard/amd/torpedo/fadt.c
@@ -27,7 +27,7 @@
#include "SbPlatform.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of sb900. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index bf551a9..c5c908d 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -77,7 +77,7 @@ static void *smp_write_config_table(void *v)
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
- /*Inagua used dure core cpu with one die */
+ /*Inagua used dure core CPU with one die */
boot_apic_id = lapicid();
apic_version = lapic_read(LAPIC_LVR) & 0xff;
result = cpuid(1);
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 2f696ef..05c3a38 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout
index c11997c..a6483458 100644
--- a/src/mainboard/apple/macbook21/cmos.layout
+++ b/src/mainboard/apple/macbook21/cmos.layout
@@ -72,7 +72,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c
index 7adac7e..e1af4d7 100644
--- a/src/mainboard/artecgroup/dbe61/irq_tables.c
+++ b/src/mainboard/artecgroup/dbe61/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
}
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index d030423..fbfe61d 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -31,13 +31,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 5413b7c..559fa85 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -43,13 +43,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c
index f702396..6c81e7d 100644
--- a/src/mainboard/asus/f2a85-m_le/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c
@@ -43,13 +43,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c
index f7a2133..937f4b7 100644
--- a/src/mainboard/asus/kcma-d8/resourcemap.c
+++ b/src/mainboard/asus/kcma-d8/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
@@ -451,7 +451,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -522,7 +522,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 3f96c52..e06e02b 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -532,7 +532,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3B);
- /* Wait for all APs to be stopped, otherwise ram initialization may hang */
+ /* Wait for all APs to be stopped, otherwise RAM initialization may hang */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
wait_all_other_cores_stopped(bsp_apicid);
diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c
index 3718dfd..cfbade6 100644
--- a/src/mainboard/asus/kfsn4-dre/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
index 3718dfd..cfbade6 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c
index 8bcb28b..d1fcad7 100644
--- a/src/mainboard/asus/kgpe-d16/resourcemap.c
+++ b/src/mainboard/asus/kgpe-d16/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
@@ -451,7 +451,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -522,7 +522,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index fd3411a..e5550bd 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -573,7 +573,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3B);
- /* Wait for all APs to be stopped, otherwise ram initialization may hang */
+ /* Wait for all APs to be stopped, otherwise RAM initialization may hang */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
wait_all_other_cores_stopped(bsp_apicid);
diff --git a/src/mainboard/asus/m2n-e/resourcemap.c b/src/mainboard/asus/m2n-e/resourcemap.c
index 784fe0f..57e7389 100644
--- a/src/mainboard/asus/m2n-e/resourcemap.c
+++ b/src/mainboard/asus/m2n-e/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index b97ba40..00bea29 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -28,7 +28,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
* 3: powered on suspend, CPU context lost S1
* Note: Looks like 'CPU context lost' does _not_ mean the
* CPU restarts at the reset vector. Most likely only
- * caches are lost, so both 0x3 and 0x4 map to acpi S1
+ * caches are lost, so both 0x3 and 0x4 map to ACPI S1
* 4: powered on suspend, context maintained S1
* 5: working (clock control) S0
* 6: reserved
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
index 507c9f1..51e3501 100644
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
@@ -15,7 +15,7 @@
# GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
# Memory setting for DDR-1066
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
index 1991f84..7949ce8 100644
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
@@ -15,7 +15,7 @@
# GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
# Memory setting for DDR-1333
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
index e657179..6653aa4 100644
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
@@ -15,7 +15,7 @@
# GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
# Memory setting for DDR-800
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc
index 4f4a11d..b0ce627 100644
--- a/src/mainboard/bap/ode_e21XX/Makefile.inc
+++ b/src/mainboard/bap/ode_e21XX/Makefile.inc
@@ -27,7 +27,7 @@ SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066 BAP_Q7_1333
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c
index 71f3c75..27c3af1 100644
--- a/src/mainboard/emulation/qemu-armv7/media.c
+++ b/src/mainboard/emulation/qemu-armv7/media.c
@@ -14,7 +14,7 @@
*/
#include <boot_device.h>
-/* Maps directly to NOR flash up to rom size. */
+/* Maps directly to NOR flash up to ROM size. */
static const struct mem_region_device boot_dev =
MEM_REGION_DEV_RO_INIT((void *)0x0, CONFIG_ROM_SIZE);
diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
index 0f3e83b..17e166c 100644
--- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
+++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
@@ -43,7 +43,7 @@ Scope(\_SB) {
PRS, 256
}
Method(PRSC, 0) {
- // Local5 = active cpu bitmap
+ // Local5 = active CPU bitmap
Store(PRS, Local5)
// Local2 = last read byte from bitmap
Store(Zero, Local2)
@@ -56,7 +56,7 @@ Scope(\_SB) {
// Shift down previously read bitmap byte
ShiftRight(Local2, 1, Local2)
} Else {
- // Read next byte from cpu bitmap
+ // Read next byte from CPU bitmap
Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
}
// Local3 = active state for this cpu
diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
index 9f6a55c..565b855 100644
--- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
+++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
@@ -118,21 +118,21 @@ int fw_cfg_max_cpus(void)
/* ---------------------------------------------------------------------- */
/*
- * Starting with release 1.7 qemu provides acpi tables via fw_cfg.
+ * Starting with release 1.7 qemu provides ACPI tables via fw_cfg.
* Main advantage is that new (virtual) hardware which needs acpi
* support JustWorks[tm] without having to patch & update the firmware
* (seabios, coreboot, ...) accordingly.
*
* Qemu provides a etc/table-loader file with instructions for the
* firmware:
- * - A "load" instruction to fetch acpi data from fw_cfg.
+ * - A "load" instruction to fetch ACPI data from fw_cfg.
* - A "pointer" instruction to patch a pointer. This is needed to
* get table-to-table references right, it is basically a
- * primitive dynamic linker for acpi tables.
- * - A "checksum" instruction to generate acpi table checksums.
+ * primitive dynamic linker for ACPI tables.
+ * - A "checksum" instruction to generate ACPI table checksums.
*
* If a etc/table-loader file is found we'll go try loading the acpi
- * tables from fw_cfg, otherwise we'll fallback to the acpi tables
+ * tables from fw_cfg, otherwise we'll fallback to the ACPI tables
* compiled in.
*/
@@ -211,7 +211,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
if (rc < 0)
return 0;
- printk(BIOS_DEBUG, "QEMU: found acpi tables in fw_cfg.\n");
+ printk(BIOS_DEBUG, "QEMU: found ACPI tables in fw_cfg.\n");
max = rc / sizeof(*s);
s = malloc(rc);
@@ -259,7 +259,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
default:
/*
- * Should not happen. acpi knows 1 and 2 byte ptrs
+ * Should not happen. ACPI knows 1 and 2 byte ptrs
* too, but we are operating with 32bit offsets which
* would simply not fit in there ...
*/
@@ -293,13 +293,13 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
};
}
- printk(BIOS_DEBUG, "QEMU: loaded acpi tables from fw_cfg.\n");
+ printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n");
free(s);
free(addrs);
return ALIGN(current, 16);
err:
- printk(BIOS_DEBUG, "QEMU: loading acpi tables from fw_cfg failed.\n");
+ printk(BIOS_DEBUG, "QEMU: loading ACPI tables from fw_cfg failed.\n");
free(s);
free(addrs);
return 0;
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 26cbda5..575069c 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -72,7 +72,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
fw_cfg_load_file("etc/e820", list);
for (i = 0; i < size/sizeof(*list); i++) {
switch (list[i].type) {
- case 1: /* ram */
+ case 1: /* RAM */
printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n",
list[i].address, list[i].length);
if (list[i].address == 0) {
@@ -135,7 +135,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
* Reserve the region between top-of-ram and the
* mmconf xbar (ar 0xb0000000), so coreboot doesn't
* place pci bars there. The region isn't declared as
- * pci io window in the acpi tables (\_SB.PCI0._CRS).
+ * pci io window in the ACPI tables (\_SB.PCI0._CRS).
*/
res = new_resource(dev, idx++);
res->base = tomk * 1024;
diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c
index b7a7213..102f54c 100644
--- a/src/mainboard/emulation/qemu-power8/mainboard.c
+++ b/src/mainboard/emulation/qemu-power8/mainboard.c
@@ -26,7 +26,7 @@ static void mainboard_enable(device_t dev)
;
}
- // Where does ram live?
+ // Where does RAM live?
ram_resource(dev, 0, 2048, 32768);
cbmem_recovery(0);
}
diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout
index 023bdfa..177bdfe 100644
--- a/src/mainboard/getac/p470/cmos.layout
+++ b/src/mainboard/getac/p470/cmos.layout
@@ -72,7 +72,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c
index 7a2a3e5..d70c4fa 100644
--- a/src/mainboard/getac/p470/cstates.c
+++ b/src/mainboard/getac/p470/cstates.c
@@ -4,17 +4,17 @@
static acpi_cstate_t cst_entries[] = {
{
- /* acpi C1 / cpu C1 */
+ /* ACPI C1 / CPU C1 */
1, 0x01, 1000,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
},
{
- /* acpi C2 / cpu C2 */
+ /* ACPI C2 / CPU C2 */
2, 0x01, 500,
{ ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 }
},
{
- /* acpi C3 / cpu C2 */
+ /* ACPI C3 / CPU C2 */
2, 0x11, 250,
{ ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 }
},
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
index 17b95e1..35c54c8 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 35a5cb4..8bc71a9 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -193,5 +193,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
sis_init_stage2();
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c
index 17b95e1..35c54c8 100644
--- a/src/mainboard/gigabyte/m57sli/resourcemap.c
+++ b/src/mainboard/gigabyte/m57sli/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 67bf503..b1c849b 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -199,5 +199,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc
index 6d51373..a2a8dad 100644
--- a/src/mainboard/gizmosphere/gizmo/Makefile.inc
+++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc
@@ -37,7 +37,7 @@ SPD_SOURCES = Elpida_EDJ2116DEBG
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index f26559f..3a63038 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -32,13 +32,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc
index 8fa32da..8a24bea 100644
--- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc
+++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc
@@ -30,7 +30,7 @@ SPD_SOURCES = Micron_MT41J128M16JT
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/auron/spd/Makefile.inc b/src/mainboard/google/auron/spd/Makefile.inc
index 507bf0c..1695871 100644
--- a/src/mainboard/google/auron/spd/Makefile.inc
+++ b/src/mainboard/google/auron/spd/Makefile.inc
@@ -29,7 +29,7 @@ SPD_SOURCES += empty # 0b0111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron_paine/spd/Makefile.inc
index 7846c84..6350fc9 100644
--- a/src/mainboard/google/auron_paine/spd/Makefile.inc
+++ b/src/mainboard/google/auron_paine/spd/Makefile.inc
@@ -42,7 +42,7 @@ SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.xxd)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do xxd -rg1 $$f; \
diff --git a/src/mainboard/google/chell/spd/Makefile.inc b/src/mainboard/google/chell/spd/Makefile.inc
index f0aa6de..f78f3f6 100644
--- a/src/mainboard/google/chell/spd/Makefile.inc
+++ b/src/mainboard/google/chell/spd/Makefile.inc
@@ -28,7 +28,7 @@ SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0101
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc
index b1cd16d..dd62025 100644
--- a/src/mainboard/google/cyan/spd/Makefile.inc
+++ b/src/mainboard/google/cyan/spd/Makefile.inc
@@ -25,7 +25,7 @@ SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc
index 5c60d4e..34de87a 100644
--- a/src/mainboard/google/falco/Makefile.inc
+++ b/src/mainboard/google/falco/Makefile.inc
@@ -36,7 +36,7 @@ SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111)
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/glados/spd/Makefile.inc b/src/mainboard/google/glados/spd/Makefile.inc
index 78e00c1..0d6da9e 100644
--- a/src/mainboard/google/glados/spd/Makefile.inc
+++ b/src/mainboard/google/glados/spd/Makefile.inc
@@ -26,7 +26,7 @@ SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR # 0b0011
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/lars/spd/Makefile.inc b/src/mainboard/google/lars/spd/Makefile.inc
index 7f49cdb..d6d789e 100644
--- a/src/mainboard/google/lars/spd/Makefile.inc
+++ b/src/mainboard/google/lars/spd/Makefile.inc
@@ -38,7 +38,7 @@ SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc
index b79e4d3..a25e95c 100644
--- a/src/mainboard/google/link/Makefile.inc
+++ b/src/mainboard/google/link/Makefile.inc
@@ -31,7 +31,7 @@ SPD_SOURCES += micron_4Gb_1600_1.35v_x16
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/ninja/spd/Makefile.inc b/src/mainboard/google/ninja/spd/Makefile.inc
index 9b4e8c1..b2552d3 100644
--- a/src/mainboard/google/ninja/spd/Makefile.inc
+++ b/src/mainboard/google/ninja/spd/Makefile.inc
@@ -36,7 +36,7 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc
index 49165ad..b49f98e 100644
--- a/src/mainboard/google/peppy/Makefile.inc
+++ b/src/mainboard/google/peppy/Makefile.inc
@@ -35,7 +35,7 @@ SPD_SOURCES += Elpida_EDJ4216EFBG # 6: 2GB / CH0 + CH1
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc
index 6a19f0f..85956b0 100644
--- a/src/mainboard/google/rambi/spd/Makefile.inc
+++ b/src/mainboard/google/rambi/spd/Makefile.inc
@@ -32,7 +32,7 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc
index ef122a0..c7c8a75 100644
--- a/src/mainboard/google/samus/spd/Makefile.inc
+++ b/src/mainboard/google/samus/spd/Makefile.inc
@@ -37,7 +37,7 @@ SPD_SOURCES += elpida_16 # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
index 77389f0..8de268b 100644
--- a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
@@ -597,7 +597,7 @@ Device (IDE0) {
}
}
Device (PMF) {
- // acpi smbus it should be 0x00040003 if 8131 present
+ // ACPI smbus it should be 0x00040003 if 8131 present
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/hp/dl145_g1/dsdt.asl b/src/mainboard/hp/dl145_g1/dsdt.asl
index 9e131b5..8d97c89 100644
--- a/src/mainboard/hp/dl145_g1/dsdt.asl
+++ b/src/mainboard/hp/dl145_g1/dsdt.asl
@@ -172,7 +172,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
Notify (\_SB.PWRB, 0x02)
}
}
- OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?)
+ OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS RAM (?)
Field (KSB0, ByteAcc, NoLock, Preserve) {
KSBI, 8, // Index
KSBD, 8 // Data
diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c
index b81caee..fb0c62b 100644
--- a/src/mainboard/hp/dl145_g1/fadt.c
+++ b/src/mainboard/hp/dl145_g1/fadt.c
@@ -8,7 +8,7 @@
#include <console/console.h>
#include <arch/acpi.h>
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 7300771..9d8f505 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -45,13 +45,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout
index 1ef4361..b8bd0c1 100644
--- a/src/mainboard/ibase/mb899/cmos.layout
+++ b/src/mainboard/ibase/mb899/cmos.layout
@@ -82,7 +82,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout
index 31f2b20..c280627 100644
--- a/src/mainboard/intel/d945gclf/cmos.layout
+++ b/src/mainboard/intel/d945gclf/cmos.layout
@@ -68,7 +68,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
index 6944664..62d6fd4 100644
--- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
@@ -38,7 +38,7 @@ SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/iwave/iWRainbowG6/cmos.layout b/src/mainboard/iwave/iWRainbowG6/cmos.layout
index 0b1845e..e2ff2c5 100644
--- a/src/mainboard/iwave/iWRainbowG6/cmos.layout
+++ b/src/mainboard/iwave/iWRainbowG6/cmos.layout
@@ -75,7 +75,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
index 4d41c60..df722f8 100644
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
+++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
@@ -49,7 +49,7 @@
Device (SBC3)
{
- /* acpi smbus it should be 0x00040003 if 8131 present */
+ /* ACPI smbus it should be 0x00040003 if 8131 present */
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c
index f677b4e..43d7c16 100644
--- a/src/mainboard/iwill/dk8_htx/fadt.c
+++ b/src/mainboard/iwill/dk8_htx/fadt.c
@@ -7,7 +7,7 @@
#include <console/console.h>
#include <arch/acpi.h>
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
index 19255fa..25dcab1 100644
--- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c
+++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
@@ -64,7 +64,7 @@ static unsigned get_hcid(unsigned i)
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 9b5b38d..4cf89b1 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -159,5 +159,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 24337ef..5646670 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -43,13 +43,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout
index f9fb424..2a99e50 100644
--- a/src/mainboard/kontron/986lcd-m/cmos.layout
+++ b/src/mainboard/kontron/986lcd-m/cmos.layout
@@ -85,7 +85,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/kontron/kt690/fadt.c
+++ b/src/mainboard/kontron/kt690/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index a1abfc8..0294c89 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -45,13 +45,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout
index b4b7766..43d2b49 100644
--- a/src/mainboard/lenovo/t400/cmos.layout
+++ b/src/mainboard/lenovo/t400/cmos.layout
@@ -87,7 +87,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 unused
-# ram initialization internal data
+# RAM initialization internal data
1024 128 r 0 read_training_results
# -----------------------------------------------------------------
diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c
index 827f76e..3ce2ed1 100644
--- a/src/mainboard/lenovo/t400/cstates.c
+++ b/src/mainboard/lenovo/t400/cstates.c
@@ -19,12 +19,12 @@
static acpi_cstate_t cst_entries[] = {
{
- /* acpi C1 / cpu C1 */
+ /* ACPI C1 / CPU C1 */
1, 0x01, 1000,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
},
{
- /* acpi C2 / cpu C2 */
+ /* ACPI C2 / CPU C2 */
2, 0x01, 500,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
},
diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout
index e5879d6..5068fac 100644
--- a/src/mainboard/lenovo/t60/cmos.layout
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -74,7 +74,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout
index a00d703..1791897 100644
--- a/src/mainboard/lenovo/x200/cmos.layout
+++ b/src/mainboard/lenovo/x200/cmos.layout
@@ -84,7 +84,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 unused
-# ram initialization internal data
+# RAM initialization internal data
1024 128 r 0 read_training_results
# -----------------------------------------------------------------
diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c
index 827f76e..3ce2ed1 100644
--- a/src/mainboard/lenovo/x200/cstates.c
+++ b/src/mainboard/lenovo/x200/cstates.c
@@ -19,12 +19,12 @@
static acpi_cstate_t cst_entries[] = {
{
- /* acpi C1 / cpu C1 */
+ /* ACPI C1 / CPU C1 */
1, 0x01, 1000,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
},
{
- /* acpi C2 / cpu C2 */
+ /* ACPI C2 / CPU C2 */
2, 0x01, 500,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
},
diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout
index 54a2799..9f10fbc 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -74,7 +74,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 345bff8..7c90bd0 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -31,13 +31,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 345bff8..7c90bd0 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -31,13 +31,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/msi/ms7260/resourcemap.c b/src/mainboard/msi/ms7260/resourcemap.c
index a7d520d..f17fadf 100644
--- a/src/mainboard/msi/ms7260/resourcemap.c
+++ b/src/mainboard/msi/ms7260/resourcemap.c
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c
index 76fbaa3..610baf3 100644
--- a/src/mainboard/msi/ms9652_fam10/resourcemap.c
+++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c
@@ -269,7 +269,7 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
/* Verified against board configuration registers after normal proprietary BIOS boot */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
index c70cbec..b57f957 100644
--- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
+++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
@@ -79,7 +79,7 @@ static unsigned get_hcid(unsigned i)
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/nvidia/l1_2pvv/resourcemap.c b/src/mainboard/nvidia/l1_2pvv/resourcemap.c
index 2950687..85782b7 100644
--- a/src/mainboard/nvidia/l1_2pvv/resourcemap.c
+++ b/src/mainboard/nvidia/l1_2pvv/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
+// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 01095f6..cfe5beb 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -185,5 +185,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc
index 97373de..324e4aa 100644
--- a/src/mainboard/pcengines/apu1/Makefile.inc
+++ b/src/mainboard/pcengines/apu1/Makefile.inc
@@ -39,7 +39,7 @@ SPD_SOURCES = HYNIX-H5TQ2G83CFR HYNIX-H5TQ4G83MFR
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index f7d99c0..798b385 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout
index 023bdfa..177bdfe 100644
--- a/src/mainboard/roda/rk886ex/cmos.layout
+++ b/src/mainboard/roda/rk886ex/cmos.layout
@@ -72,7 +72,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c
index 6fd4be9..6a9b26c 100644
--- a/src/mainboard/roda/rk886ex/m3885.c
+++ b/src/mainboard/roda/rk886ex/m3885.c
@@ -235,7 +235,7 @@ void m3885_configure_multikey(void)
u8 reg8;
u8 kstate5_flags, offs, maxvars;
- /* ram bank 0 */
+ /* RAM bank 0 */
kstate5_flags = m3885_get_variable(0x0c);
m3885_set_variable(0x0c, kstate5_flags & ~(7 << 4));
@@ -245,7 +245,7 @@ void m3885_configure_multikey(void)
}
- /* ram bank 2 */
+ /* RAM bank 2 */
m3885_set_variable(0x0c, (kstate5_flags & (~(7 << 4))) | (2 << 4));
/* Get the number of variables */
@@ -254,7 +254,7 @@ void m3885_configure_multikey(void)
if (maxvars >= 35) {
offs = m3885_get_variable(0x23);
if ((offs > 0xc0) || (offs < 0x80)) {
- printk(BIOS_DEBUG, "M388x does not have a valid ram offset (0x%x)\n", offs);
+ printk(BIOS_DEBUG, "M388x does not have a valid RAM offset (0x%x)\n", offs);
} else {
printk(BIOS_DEBUG, "Writing Fn-Table to M388x RAM offset 0x%x\n", offs);
for (i=0; i < ARRAY_SIZE(function_ram); i++) {
diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout
index c0ea4fc..3d75784 100644
--- a/src/mainboard/roda/rk9/cmos.layout
+++ b/src/mainboard/roda/rk9/cmos.layout
@@ -74,7 +74,7 @@ entries
#1004 20 r 0 unused
-# ram initialization internal data
+# RAM initialization internal data
1024 128 r 0 read_training_results
# -----------------------------------------------------------------
diff --git a/src/mainboard/roda/rk9/cstates.c b/src/mainboard/roda/rk9/cstates.c
index 827f76e..3ce2ed1 100644
--- a/src/mainboard/roda/rk9/cstates.c
+++ b/src/mainboard/roda/rk9/cstates.c
@@ -19,12 +19,12 @@
static acpi_cstate_t cst_entries[] = {
{
- /* acpi C1 / cpu C1 */
+ /* ACPI C1 / CPU C1 */
1, 0x01, 1000,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
},
{
- /* acpi C2 / cpu C2 */
+ /* ACPI C2 / CPU C2 */
2, 0x01, 500,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
},
diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c
index 8e8f10b..395bf4a 100644
--- a/src/mainboard/roda/rk9/mainboard.c
+++ b/src/mainboard/roda/rk9/mainboard.c
@@ -24,7 +24,7 @@
static void ec_setup(void)
{
- /* Thermal limits? Values are from ectool's ram dump. */
+ /* Thermal limits? Values are from ectool's RAM dump. */
ec_write(0xd1, 0x57); /* CPUH */
ec_write(0xd2, 0xc9); /* CPUL */
ec_write(0xd4, 0x64); /* SYSH */
diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc
index 26526c9..85c5e58 100644
--- a/src/mainboard/samsung/lumpy/Makefile.inc
+++ b/src/mainboard/samsung/lumpy/Makefile.inc
@@ -20,7 +20,7 @@ ramstage-y += chromeos.c
SPD_BIN = $(obj)/spd.bin
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN):
xxd -rg1 $(src)/mainboard/samsung/lumpy/spd.hex >| $@
diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c
index bf06c5d..7d7221d 100644
--- a/src/mainboard/siemens/sitemp_g1p1/fadt.c
+++ b/src/mainboard/siemens/sitemp_g1p1/fadt.c
@@ -25,7 +25,7 @@
#include <../southbridge/amd/sb600/sb600.h>
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c
index a74048b..4ed5746 100644
--- a/src/mainboard/sunw/ultra40/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40/get_bus_conf.c
@@ -188,7 +188,7 @@ void get_bus_conf(void)
/* CK804b */
- if (pci1234[2] & 0xf) { //if the second cpu is installed
+ if (pci1234[2] & 0xf) { //if the second CPU is installed
bus_ck804b_0 = (pci1234[2] >> 16) & 0xff;
#if 0
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09, 0));
diff --git a/src/mainboard/sunw/ultra40m2/get_bus_conf.c b/src/mainboard/sunw/ultra40m2/get_bus_conf.c
index c70cbec..b57f957 100644
--- a/src/mainboard/sunw/ultra40m2/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40m2/get_bus_conf.c
@@ -79,7 +79,7 @@ static unsigned get_hcid(unsigned i)
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/sunw/ultra40m2/resourcemap.c b/src/mainboard/sunw/ultra40m2/resourcemap.c
index 5235b0d..30ce9ea 100644
--- a/src/mainboard/sunw/ultra40m2/resourcemap.c
+++ b/src/mainboard/sunw/ultra40m2/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of cpu 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of CPU 0 --> Nvidia MCP55 Pro */
+// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c
index 014c3b6..7a5ce93 100644
--- a/src/mainboard/sunw/ultra40m2/romstage.c
+++ b/src/mainboard/sunw/ultra40m2/romstage.c
@@ -181,5 +181,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/supermicro/h8dme/resourcemap.c b/src/mainboard/supermicro/h8dme/resourcemap.c
index 2c6fef0..22c61f4 100644
--- a/src/mainboard/supermicro/h8dme/resourcemap.c
+++ b/src/mainboard/supermicro/h8dme/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index b48ea46..aeff991 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -204,5 +204,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/supermicro/h8dmr/resourcemap.c b/src/mainboard/supermicro/h8dmr/resourcemap.c
index 2c6fef0..22c61f4 100644
--- a/src/mainboard/supermicro/h8dmr/resourcemap.c
+++ b/src/mainboard/supermicro/h8dmr/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 96672e9..eb73817 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -181,5 +181,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
index b71448a..b35d3e5 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
@@ -268,7 +268,7 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
// WARD CHANGED
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 1a32abf..bab438e 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- printk(BIOS_DEBUG, "Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as RAM ");
disable_cache_as_ram();
printk(BIOS_DEBUG, "done\n");
diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
index b71448a..b35d3e5 100644
--- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
@@ -268,7 +268,7 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
// WARD CHANGED
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index 071f247..fecb91a 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- printk(BIOS_DEBUG, "Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as RAM ");
disable_cache_as_ram();
printk(BIOS_DEBUG, "done\n");
diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/technexion/tim5690/fadt.c
+++ b/src/mainboard/technexion/tim5690/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/technexion/tim8690/fadt.c
+++ b/src/mainboard/technexion/tim8690/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/traverse/geos/irq_tables.c b/src/mainboard/traverse/geos/irq_tables.c
index 35d5fa6..3e2e1d9 100644
--- a/src/mainboard/traverse/geos/irq_tables.c
+++ b/src/mainboard/traverse/geos/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth0 */
{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth1 */
{0x00, (0x0C << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x2, 0x0}, /* xilinx */
diff --git a/src/mainboard/tyan/s2912/resourcemap.c b/src/mainboard/tyan/s2912/resourcemap.c
index f0ae405..9ac7ae4 100644
--- a/src/mainboard/tyan/s2912/resourcemap.c
+++ b/src/mainboard/tyan/s2912/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
+// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 751cf71..c80e2d6 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -184,5 +184,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c
index a78643a..14e3c53 100644
--- a/src/mainboard/tyan/s2912_fam10/resourcemap.c
+++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index 13b4054..ea877b7 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -106,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- printk(BIOS_DEBUG, "Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as RAM ");
disable_cache_as_ram();
printk(BIOS_DEBUG, "done\n");
diff --git a/src/mainboard/winent/pl6064/irq_tables.c b/src/mainboard/winent/pl6064/irq_tables.c
index 4de63c4..019e713 100644
--- a/src/mainboard/winent/pl6064/irq_tables.c
+++ b/src/mainboard/winent/pl6064/irq_tables.c
@@ -53,7 +53,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x09 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 0*/
{0x00, (0x0A << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1*/
1
0
New patch to review for coreboot: src/mainboard: Capitalize ROM, RAM, CPU and APIC
by HAOUAS Elyes 30 Jul '16
by HAOUAS Elyes 30 Jul '16
30 Jul '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15987
-gerrit
commit 0d1c214dbc1b8b1e67c7d27c28b15513afabde00
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Sat Jul 30 17:46:17 2016 +0200
src/mainboard: Capitalize ROM, RAM, CPU and APIC
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/mainboard/amd/db-ft3b-lc/Makefile.inc | 2 +-
src/mainboard/amd/db800/irq_tables.c | 2 +-
src/mainboard/amd/dbm690t/fadt.c | 2 +-
src/mainboard/amd/dinar/buildOpts.c | 4 ++--
src/mainboard/amd/dinar/romstage.c | 2 +-
src/mainboard/amd/f2950/irq_tables.c | 2 +-
src/mainboard/amd/inagua/buildOpts.c | 4 ++--
src/mainboard/amd/norwich/irq_tables.c | 2 +-
src/mainboard/amd/parmer/buildOpts.c | 4 ++--
src/mainboard/amd/persimmon/buildOpts.c | 4 ++--
src/mainboard/amd/pistachio/fadt.c | 2 +-
src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl | 2 +-
src/mainboard/amd/serengeti_cheetah/fadt.c | 2 +-
src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 2 +-
src/mainboard/amd/serengeti_cheetah/readme_acpi.txt | 2 +-
src/mainboard/amd/serengeti_cheetah/romstage.c | 2 +-
.../amd/serengeti_cheetah_fam10/acpi/amd8111.asl | 2 +-
src/mainboard/amd/serengeti_cheetah_fam10/fadt.c | 2 +-
.../amd/serengeti_cheetah_fam10/get_bus_conf.c | 2 +-
src/mainboard/amd/south_station/buildOpts.c | 4 ++--
src/mainboard/amd/thatcher/buildOpts.c | 4 ++--
src/mainboard/amd/torpedo/buildOpts.c | 4 ++--
src/mainboard/amd/torpedo/fadt.c | 2 +-
src/mainboard/amd/torpedo/mptable.c | 2 +-
src/mainboard/amd/union_station/buildOpts.c | 4 ++--
src/mainboard/apple/macbook21/cmos.layout | 2 +-
src/mainboard/artecgroup/dbe61/irq_tables.c | 2 +-
src/mainboard/asrock/e350m1/buildOpts.c | 4 ++--
src/mainboard/asus/f2a85-m/buildOpts.c | 4 ++--
src/mainboard/asus/f2a85-m_le/buildOpts.c | 4 ++--
src/mainboard/asus/kcma-d8/resourcemap.c | 8 ++++----
src/mainboard/asus/kcma-d8/romstage.c | 2 +-
src/mainboard/asus/kfsn4-dre/resourcemap.c | 4 ++--
src/mainboard/asus/kfsn4-dre_k8/resourcemap.c | 4 ++--
src/mainboard/asus/kgpe-d16/resourcemap.c | 8 ++++----
src/mainboard/asus/kgpe-d16/romstage.c | 2 +-
src/mainboard/asus/m2n-e/resourcemap.c | 2 +-
src/mainboard/asus/p2b/dsdt.asl | 2 +-
src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex | 2 +-
src/mainboard/bap/ode_e20XX/Makefile.inc | 2 +-
src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex | 2 +-
src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex | 2 +-
src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex | 2 +-
src/mainboard/bap/ode_e21XX/Makefile.inc | 2 +-
src/mainboard/emulation/qemu-armv7/media.c | 2 +-
.../emulation/qemu-i440fx/acpi/cpu-hotplug.asl | 4 ++--
src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 18 +++++++++---------
src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 ++--
src/mainboard/emulation/qemu-power8/mainboard.c | 2 +-
src/mainboard/getac/p470/cmos.layout | 2 +-
src/mainboard/getac/p470/cstates.c | 6 +++---
src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c | 2 +-
src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 +-
src/mainboard/gigabyte/m57sli/resourcemap.c | 2 +-
src/mainboard/gigabyte/m57sli/romstage.c | 2 +-
src/mainboard/gizmosphere/gizmo/Makefile.inc | 2 +-
src/mainboard/gizmosphere/gizmo/buildOpts.c | 4 ++--
src/mainboard/gizmosphere/gizmo2/Makefile.inc | 2 +-
src/mainboard/google/auron/spd/Makefile.inc | 2 +-
src/mainboard/google/auron_paine/spd/Makefile.inc | 2 +-
src/mainboard/google/chell/spd/Makefile.inc | 2 +-
src/mainboard/google/cyan/spd/Makefile.inc | 2 +-
src/mainboard/google/falco/Makefile.inc | 2 +-
src/mainboard/google/glados/spd/Makefile.inc | 2 +-
src/mainboard/google/lars/spd/Makefile.inc | 2 +-
src/mainboard/google/link/Makefile.inc | 2 +-
src/mainboard/google/ninja/spd/Makefile.inc | 2 +-
src/mainboard/google/peppy/Makefile.inc | 2 +-
src/mainboard/google/rambi/spd/Makefile.inc | 2 +-
src/mainboard/google/samus/spd/Makefile.inc | 2 +-
src/mainboard/hp/dl145_g1/acpi/amd8111.asl | 2 +-
src/mainboard/hp/dl145_g1/dsdt.asl | 2 +-
src/mainboard/hp/dl145_g1/fadt.c | 2 +-
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 4 ++--
src/mainboard/ibase/mb899/cmos.layout | 2 +-
src/mainboard/intel/d945gclf/cmos.layout | 2 +-
src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +-
src/mainboard/iwave/iWRainbowG6/cmos.layout | 2 +-
src/mainboard/iwill/dk8_htx/acpi/amd8111.asl | 2 +-
src/mainboard/iwill/dk8_htx/fadt.c | 2 +-
src/mainboard/iwill/dk8_htx/get_bus_conf.c | 2 +-
src/mainboard/iwill/dk8_htx/romstage.c | 2 +-
src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 4 ++--
src/mainboard/kontron/986lcd-m/cmos.layout | 2 +-
src/mainboard/kontron/kt690/fadt.c | 2 +-
src/mainboard/lenovo/g505s/buildOpts.c | 4 ++--
src/mainboard/lenovo/t400/cmos.layout | 2 +-
src/mainboard/lenovo/t400/cstates.c | 4 ++--
src/mainboard/lenovo/t60/cmos.layout | 2 +-
src/mainboard/lenovo/x200/cmos.layout | 2 +-
src/mainboard/lenovo/x200/cstates.c | 4 ++--
src/mainboard/lenovo/x60/cmos.layout | 2 +-
src/mainboard/lippert/frontrunner-af/buildOpts.c | 4 ++--
src/mainboard/lippert/toucan-af/buildOpts.c | 4 ++--
src/mainboard/msi/ms7260/resourcemap.c | 2 +-
src/mainboard/msi/ms9652_fam10/resourcemap.c | 2 +-
src/mainboard/nvidia/l1_2pvv/get_bus_conf.c | 2 +-
src/mainboard/nvidia/l1_2pvv/resourcemap.c | 4 ++--
src/mainboard/nvidia/l1_2pvv/romstage.c | 2 +-
src/mainboard/pcengines/apu1/Makefile.inc | 2 +-
src/mainboard/pcengines/apu1/buildOpts.c | 4 ++--
src/mainboard/roda/rk886ex/cmos.layout | 2 +-
src/mainboard/roda/rk886ex/m3885.c | 6 +++---
src/mainboard/roda/rk9/cmos.layout | 2 +-
src/mainboard/roda/rk9/cstates.c | 4 ++--
src/mainboard/roda/rk9/mainboard.c | 2 +-
src/mainboard/samsung/lumpy/Makefile.inc | 2 +-
src/mainboard/siemens/sitemp_g1p1/fadt.c | 2 +-
src/mainboard/sunw/ultra40/get_bus_conf.c | 2 +-
src/mainboard/sunw/ultra40m2/get_bus_conf.c | 2 +-
src/mainboard/sunw/ultra40m2/resourcemap.c | 4 ++--
src/mainboard/sunw/ultra40m2/romstage.c | 2 +-
src/mainboard/supermicro/h8dme/resourcemap.c | 2 +-
src/mainboard/supermicro/h8dme/romstage.c | 2 +-
src/mainboard/supermicro/h8dmr/resourcemap.c | 2 +-
src/mainboard/supermicro/h8dmr/romstage.c | 2 +-
src/mainboard/supermicro/h8dmr_fam10/resourcemap.c | 2 +-
src/mainboard/supermicro/h8qgi/romstage.c | 2 +-
src/mainboard/supermicro/h8qme_fam10/resourcemap.c | 2 +-
src/mainboard/supermicro/h8scm/romstage.c | 2 +-
src/mainboard/technexion/tim5690/fadt.c | 2 +-
src/mainboard/technexion/tim8690/fadt.c | 2 +-
src/mainboard/traverse/geos/irq_tables.c | 2 +-
src/mainboard/tyan/s2912/resourcemap.c | 4 ++--
src/mainboard/tyan/s2912/romstage.c | 2 +-
src/mainboard/tyan/s2912_fam10/resourcemap.c | 4 ++--
src/mainboard/tyan/s8226/romstage.c | 2 +-
src/mainboard/winent/pl6064/irq_tables.c | 2 +-
128 files changed, 175 insertions(+), 175 deletions(-)
diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
index 8b160e2..97c761f 100644
--- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc
+++ b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
@@ -27,7 +27,7 @@ SPD_SOURCES = Memphis_MEM4G16D3EABG
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/amd/db800/irq_tables.c b/src/mainboard/amd/db800/irq_tables.c
index 00a19db..8cf172a 100644
--- a/src/mainboard/amd/db800/irq_tables.c
+++ b/src/mainboard/amd/db800/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */
diff --git a/src/mainboard/amd/dbm690t/fadt.c b/src/mainboard/amd/dbm690t/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/amd/dbm690t/fadt.c
+++ b/src/mainboard/amd/dbm690t/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
index 3fd9c48..e237ff0 100644
--- a/src/mainboard/amd/dinar/buildOpts.c
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -54,10 +54,10 @@
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
-/* Select the cpu family. */
+/* Select the CPU family. */
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT TRUE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 70cd5e3..bc5d312 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43);
- printk(BIOS_DEBUG, "Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as RAM ");
disable_cache_as_ram();
printk(BIOS_DEBUG, "done\n");
diff --git a/src/mainboard/amd/f2950/irq_tables.c b/src/mainboard/amd/f2950/irq_tables.c
index b438f02..dae29a1 100644
--- a/src/mainboard/amd/f2950/irq_tables.c
+++ b/src/mainboard/amd/f2950/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
}
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index ffaf79a..1cefc69 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/norwich/irq_tables.c b/src/mainboard/amd/norwich/irq_tables.c
index dfb1ef4..a59dc26 100644
--- a/src/mainboard/amd/norwich/irq_tables.c
+++ b/src/mainboard/amd/norwich/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 11d36bc..dc1c705 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -30,13 +30,13 @@
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index fe4e779..2377827 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/pistachio/fadt.c b/src/mainboard/amd/pistachio/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/amd/pistachio/fadt.c
+++ b/src/mainboard/amd/pistachio/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
index cc9b65b..aaa778b 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
+++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl
@@ -61,7 +61,7 @@
Device (SBC3)
{
- /* acpi smbus it should be 0x00040003 if 8131 present */
+ /* ACPI smbus it should be 0x00040003 if 8131 present */
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c
index 4fe4efd..bd00961 100644
--- a/src/mainboard/amd/serengeti_cheetah/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah/fadt.c
@@ -21,7 +21,7 @@
#include <console/console.h>
#include <arch/acpi.h>
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
index 0492e9a..1eb97b5 100644
--- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
@@ -77,7 +77,7 @@ static unsigned get_hcid(unsigned i)
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
index b999dfa..0dbf303 100644
--- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
+++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
@@ -1,4 +1,4 @@
-At this time, For acpi support We got
+At this time, For ACPI support We got
1. support AMK K8 SRAT --- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
2. support MADT ---- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{acpi/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index ded74a5..51fce31 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -224,5 +224,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
index 46fe121..f6a1954 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111.asl
@@ -53,7 +53,7 @@
Device (SBC3)
{
- // acpi smbus it should be 0x00040003 if 8131 present
+ // ACPI smbus it should be 0x00040003 if 8131 present
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
index 544df8e..3183a7e 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c
@@ -24,7 +24,7 @@
#include <console/console.h>
#include <arch/acpi.h>
-extern u32 pm_base; /* pm_base should be set in sb acpi */
+extern u32 pm_base; /* pm_base should be set in sb ACPI */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index 6113f0e..66dee18 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -81,7 +81,7 @@ static u32 get_hcid(u32 i)
break;
}
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 2f696ef..05c3a38 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 45569df..bd43181 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -30,13 +30,13 @@
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index 40f1f97..c80b7d9 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -31,13 +31,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT TRUE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c
index 9a615c1..fba8fc8 100644
--- a/src/mainboard/amd/torpedo/fadt.c
+++ b/src/mainboard/amd/torpedo/fadt.c
@@ -27,7 +27,7 @@
#include "SbPlatform.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of sb900. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index bf551a9..c5c908d 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -77,7 +77,7 @@ static void *smp_write_config_table(void *v)
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
- /*Inagua used dure core cpu with one die */
+ /*Inagua used dure core CPU with one die */
boot_apic_id = lapicid();
apic_version = lapic_read(LAPIC_LVR) & 0xff;
result = cpuid(1);
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
index 2f696ef..05c3a38 100644
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ b/src/mainboard/amd/union_station/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout
index c11997c..a6483458 100644
--- a/src/mainboard/apple/macbook21/cmos.layout
+++ b/src/mainboard/apple/macbook21/cmos.layout
@@ -72,7 +72,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c
index 7adac7e..e1af4d7 100644
--- a/src/mainboard/artecgroup/dbe61/irq_tables.c
+++ b/src/mainboard/artecgroup/dbe61/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
}
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index d030423..fbfe61d 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -31,13 +31,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index 5413b7c..559fa85 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -43,13 +43,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c
index f702396..6c81e7d 100644
--- a/src/mainboard/asus/f2a85-m_le/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c
@@ -43,13 +43,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c
index f7a2133..937f4b7 100644
--- a/src/mainboard/asus/kcma-d8/resourcemap.c
+++ b/src/mainboard/asus/kcma-d8/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
@@ -451,7 +451,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -522,7 +522,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 3f96c52..e06e02b 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -532,7 +532,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3B);
- /* Wait for all APs to be stopped, otherwise ram initialization may hang */
+ /* Wait for all APs to be stopped, otherwise RAM initialization may hang */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
wait_all_other_cores_stopped(bsp_apicid);
diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c
index 3718dfd..cfbade6 100644
--- a/src/mainboard/asus/kfsn4-dre/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
index 3718dfd..cfbade6 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> Nvidia CK 804 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> Nvidia CK 804 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c
index 8bcb28b..d1fcad7 100644
--- a/src/mainboard/asus/kgpe-d16/resourcemap.c
+++ b/src/mainboard/asus/kgpe-d16/resourcemap.c
@@ -196,7 +196,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
@@ -451,7 +451,7 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -522,7 +522,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of cpu 0 --> AMD SR5690 */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index fd3411a..e5550bd 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -573,7 +573,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3B);
- /* Wait for all APs to be stopped, otherwise ram initialization may hang */
+ /* Wait for all APs to be stopped, otherwise RAM initialization may hang */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
wait_all_other_cores_stopped(bsp_apicid);
diff --git a/src/mainboard/asus/m2n-e/resourcemap.c b/src/mainboard/asus/m2n-e/resourcemap.c
index 784fe0f..57e7389 100644
--- a/src/mainboard/asus/m2n-e/resourcemap.c
+++ b/src/mainboard/asus/m2n-e/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index b97ba40..00bea29 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -28,7 +28,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
* 3: powered on suspend, CPU context lost S1
* Note: Looks like 'CPU context lost' does _not_ mean the
* CPU restarts at the reset vector. Most likely only
- * caches are lost, so both 0x3 and 0x4 map to acpi S1
+ * caches are lost, so both 0x3 and 0x4 map to ACPI S1
* 4: powered on suspend, context maintained S1
* 5: working (clock control) S0
* 6: reserved
diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex
index d5fde6d..7883191 100644
--- a/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex
+++ b/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex
@@ -14,7 +14,7 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-# BAP ODE E20XX has 2GB ram soldered down on the Q7
+# BAP ODE E20XX has 2GB RAM soldered down on the Q7
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
# bits[3:0]: 1 = 128 SPD Bytes Used
diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc
index f1c946a..2fd37a9 100644
--- a/src/mainboard/bap/ode_e20XX/Makefile.inc
+++ b/src/mainboard/bap/ode_e20XX/Makefile.inc
@@ -30,7 +30,7 @@ SPD_SOURCES = BAP_Q7
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
index 507c9f1..51e3501 100644
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
@@ -15,7 +15,7 @@
# GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
# Memory setting for DDR-1066
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
index 1991f84..7949ce8 100644
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
@@ -15,7 +15,7 @@
# GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
# Memory setting for DDR-1333
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
index e657179..6653aa4 100644
--- a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
@@ -15,7 +15,7 @@
# GNU General Public License for more details.
# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
-# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# BAP ODE E21XX has 2GB RAM soldered down on the Q7
# Memory setting for DDR-800
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc
index 4f4a11d..b0ce627 100644
--- a/src/mainboard/bap/ode_e21XX/Makefile.inc
+++ b/src/mainboard/bap/ode_e21XX/Makefile.inc
@@ -27,7 +27,7 @@ SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066 BAP_Q7_1333
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c
index 71f3c75..27c3af1 100644
--- a/src/mainboard/emulation/qemu-armv7/media.c
+++ b/src/mainboard/emulation/qemu-armv7/media.c
@@ -14,7 +14,7 @@
*/
#include <boot_device.h>
-/* Maps directly to NOR flash up to rom size. */
+/* Maps directly to NOR flash up to ROM size. */
static const struct mem_region_device boot_dev =
MEM_REGION_DEV_RO_INIT((void *)0x0, CONFIG_ROM_SIZE);
diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
index 0f3e83b..17e166c 100644
--- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
+++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl
@@ -43,7 +43,7 @@ Scope(\_SB) {
PRS, 256
}
Method(PRSC, 0) {
- // Local5 = active cpu bitmap
+ // Local5 = active CPU bitmap
Store(PRS, Local5)
// Local2 = last read byte from bitmap
Store(Zero, Local2)
@@ -56,7 +56,7 @@ Scope(\_SB) {
// Shift down previously read bitmap byte
ShiftRight(Local2, 1, Local2)
} Else {
- // Read next byte from cpu bitmap
+ // Read next byte from CPU bitmap
Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
}
// Local3 = active state for this cpu
diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
index 9f6a55c..565b855 100644
--- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
+++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c
@@ -118,21 +118,21 @@ int fw_cfg_max_cpus(void)
/* ---------------------------------------------------------------------- */
/*
- * Starting with release 1.7 qemu provides acpi tables via fw_cfg.
+ * Starting with release 1.7 qemu provides ACPI tables via fw_cfg.
* Main advantage is that new (virtual) hardware which needs acpi
* support JustWorks[tm] without having to patch & update the firmware
* (seabios, coreboot, ...) accordingly.
*
* Qemu provides a etc/table-loader file with instructions for the
* firmware:
- * - A "load" instruction to fetch acpi data from fw_cfg.
+ * - A "load" instruction to fetch ACPI data from fw_cfg.
* - A "pointer" instruction to patch a pointer. This is needed to
* get table-to-table references right, it is basically a
- * primitive dynamic linker for acpi tables.
- * - A "checksum" instruction to generate acpi table checksums.
+ * primitive dynamic linker for ACPI tables.
+ * - A "checksum" instruction to generate ACPI table checksums.
*
* If a etc/table-loader file is found we'll go try loading the acpi
- * tables from fw_cfg, otherwise we'll fallback to the acpi tables
+ * tables from fw_cfg, otherwise we'll fallback to the ACPI tables
* compiled in.
*/
@@ -211,7 +211,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
if (rc < 0)
return 0;
- printk(BIOS_DEBUG, "QEMU: found acpi tables in fw_cfg.\n");
+ printk(BIOS_DEBUG, "QEMU: found ACPI tables in fw_cfg.\n");
max = rc / sizeof(*s);
s = malloc(rc);
@@ -259,7 +259,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
default:
/*
- * Should not happen. acpi knows 1 and 2 byte ptrs
+ * Should not happen. ACPI knows 1 and 2 byte ptrs
* too, but we are operating with 32bit offsets which
* would simply not fit in there ...
*/
@@ -293,13 +293,13 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
};
}
- printk(BIOS_DEBUG, "QEMU: loaded acpi tables from fw_cfg.\n");
+ printk(BIOS_DEBUG, "QEMU: loaded ACPI tables from fw_cfg.\n");
free(s);
free(addrs);
return ALIGN(current, 16);
err:
- printk(BIOS_DEBUG, "QEMU: loading acpi tables from fw_cfg failed.\n");
+ printk(BIOS_DEBUG, "QEMU: loading ACPI tables from fw_cfg failed.\n");
free(s);
free(addrs);
return 0;
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 26cbda5..575069c 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -72,7 +72,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
fw_cfg_load_file("etc/e820", list);
for (i = 0; i < size/sizeof(*list); i++) {
switch (list[i].type) {
- case 1: /* ram */
+ case 1: /* RAM */
printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n",
list[i].address, list[i].length);
if (list[i].address == 0) {
@@ -135,7 +135,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
* Reserve the region between top-of-ram and the
* mmconf xbar (ar 0xb0000000), so coreboot doesn't
* place pci bars there. The region isn't declared as
- * pci io window in the acpi tables (\_SB.PCI0._CRS).
+ * pci io window in the ACPI tables (\_SB.PCI0._CRS).
*/
res = new_resource(dev, idx++);
res->base = tomk * 1024;
diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c
index b7a7213..102f54c 100644
--- a/src/mainboard/emulation/qemu-power8/mainboard.c
+++ b/src/mainboard/emulation/qemu-power8/mainboard.c
@@ -26,7 +26,7 @@ static void mainboard_enable(device_t dev)
;
}
- // Where does ram live?
+ // Where does RAM live?
ram_resource(dev, 0, 2048, 32768);
cbmem_recovery(0);
}
diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout
index 023bdfa..177bdfe 100644
--- a/src/mainboard/getac/p470/cmos.layout
+++ b/src/mainboard/getac/p470/cmos.layout
@@ -72,7 +72,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c
index 7a2a3e5..d70c4fa 100644
--- a/src/mainboard/getac/p470/cstates.c
+++ b/src/mainboard/getac/p470/cstates.c
@@ -4,17 +4,17 @@
static acpi_cstate_t cst_entries[] = {
{
- /* acpi C1 / cpu C1 */
+ /* ACPI C1 / CPU C1 */
1, 0x01, 1000,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
},
{
- /* acpi C2 / cpu C2 */
+ /* ACPI C2 / CPU C2 */
2, 0x01, 500,
{ ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 }
},
{
- /* acpi C3 / cpu C2 */
+ /* ACPI C3 / CPU C2 */
2, 0x11, 250,
{ ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 }
},
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
index 17b95e1..35c54c8 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 35a5cb4..8bc71a9 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -193,5 +193,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
sis_init_stage2();
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c
index 17b95e1..35c54c8 100644
--- a/src/mainboard/gigabyte/m57sli/resourcemap.c
+++ b/src/mainboard/gigabyte/m57sli/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 67bf503..b1c849b 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -199,5 +199,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc
index 6d51373..a2a8dad 100644
--- a/src/mainboard/gizmosphere/gizmo/Makefile.inc
+++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc
@@ -37,7 +37,7 @@ SPD_SOURCES = Elpida_EDJ2116DEBG
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
index f26559f..3a63038 100644
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c
@@ -32,13 +32,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/gizmosphere/gizmo2/Makefile.inc b/src/mainboard/gizmosphere/gizmo2/Makefile.inc
index 8fa32da..8a24bea 100644
--- a/src/mainboard/gizmosphere/gizmo2/Makefile.inc
+++ b/src/mainboard/gizmosphere/gizmo2/Makefile.inc
@@ -30,7 +30,7 @@ SPD_SOURCES = Micron_MT41J128M16JT
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/auron/spd/Makefile.inc b/src/mainboard/google/auron/spd/Makefile.inc
index 507bf0c..1695871 100644
--- a/src/mainboard/google/auron/spd/Makefile.inc
+++ b/src/mainboard/google/auron/spd/Makefile.inc
@@ -29,7 +29,7 @@ SPD_SOURCES += empty # 0b0111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/auron_paine/spd/Makefile.inc b/src/mainboard/google/auron_paine/spd/Makefile.inc
index 7846c84..6350fc9 100644
--- a/src/mainboard/google/auron_paine/spd/Makefile.inc
+++ b/src/mainboard/google/auron_paine/spd/Makefile.inc
@@ -42,7 +42,7 @@ SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.xxd)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do xxd -rg1 $$f; \
diff --git a/src/mainboard/google/chell/spd/Makefile.inc b/src/mainboard/google/chell/spd/Makefile.inc
index f0aa6de..f78f3f6 100644
--- a/src/mainboard/google/chell/spd/Makefile.inc
+++ b/src/mainboard/google/chell/spd/Makefile.inc
@@ -28,7 +28,7 @@ SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0101
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc
index b1cd16d..dd62025 100644
--- a/src/mainboard/google/cyan/spd/Makefile.inc
+++ b/src/mainboard/google/cyan/spd/Makefile.inc
@@ -25,7 +25,7 @@ SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc
index 5c60d4e..34de87a 100644
--- a/src/mainboard/google/falco/Makefile.inc
+++ b/src/mainboard/google/falco/Makefile.inc
@@ -36,7 +36,7 @@ SPD_SOURCES += Samsung_M471B5674QH0 # 2GB / CH0 only (RAM_ID=111)
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/glados/spd/Makefile.inc b/src/mainboard/google/glados/spd/Makefile.inc
index 78e00c1..0d6da9e 100644
--- a/src/mainboard/google/glados/spd/Makefile.inc
+++ b/src/mainboard/google/glados/spd/Makefile.inc
@@ -26,7 +26,7 @@ SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR # 0b0011
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/lars/spd/Makefile.inc b/src/mainboard/google/lars/spd/Makefile.inc
index 7f49cdb..d6d789e 100644
--- a/src/mainboard/google/lars/spd/Makefile.inc
+++ b/src/mainboard/google/lars/spd/Makefile.inc
@@ -38,7 +38,7 @@ SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc
index b79e4d3..a25e95c 100644
--- a/src/mainboard/google/link/Makefile.inc
+++ b/src/mainboard/google/link/Makefile.inc
@@ -31,7 +31,7 @@ SPD_SOURCES += micron_4Gb_1600_1.35v_x16
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/ninja/spd/Makefile.inc b/src/mainboard/google/ninja/spd/Makefile.inc
index 9b4e8c1..b2552d3 100644
--- a/src/mainboard/google/ninja/spd/Makefile.inc
+++ b/src/mainboard/google/ninja/spd/Makefile.inc
@@ -36,7 +36,7 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63CFR-PBA
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc
index 49165ad..b49f98e 100644
--- a/src/mainboard/google/peppy/Makefile.inc
+++ b/src/mainboard/google/peppy/Makefile.inc
@@ -35,7 +35,7 @@ SPD_SOURCES += Elpida_EDJ4216EFBG # 6: 2GB / CH0 + CH1
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc
index 6a19f0f..85956b0 100644
--- a/src/mainboard/google/rambi/spd/Makefile.inc
+++ b/src/mainboard/google/rambi/spd/Makefile.inc
@@ -32,7 +32,7 @@ SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc
index ef122a0..c7c8a75 100644
--- a/src/mainboard/google/samus/spd/Makefile.inc
+++ b/src/mainboard/google/samus/spd/Makefile.inc
@@ -37,7 +37,7 @@ SPD_SOURCES += elpida_16 # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
index 77389f0..8de268b 100644
--- a/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
+++ b/src/mainboard/hp/dl145_g1/acpi/amd8111.asl
@@ -597,7 +597,7 @@ Device (IDE0) {
}
}
Device (PMF) {
- // acpi smbus it should be 0x00040003 if 8131 present
+ // ACPI smbus it should be 0x00040003 if 8131 present
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/hp/dl145_g1/dsdt.asl b/src/mainboard/hp/dl145_g1/dsdt.asl
index 9e131b5..8d97c89 100644
--- a/src/mainboard/hp/dl145_g1/dsdt.asl
+++ b/src/mainboard/hp/dl145_g1/dsdt.asl
@@ -172,7 +172,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
Notify (\_SB.PWRB, 0x02)
}
}
- OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?)
+ OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS RAM (?)
Field (KSB0, ByteAcc, NoLock, Preserve) {
KSBI, 8, // Index
KSBD, 8 // Data
diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c
index b81caee..fb0c62b 100644
--- a/src/mainboard/hp/dl145_g1/fadt.c
+++ b/src/mainboard/hp/dl145_g1/fadt.c
@@ -8,7 +8,7 @@
#include <console/console.h>
#include <arch/acpi.h>
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 7300771..9d8f505 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -45,13 +45,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout
index 1ef4361..b8bd0c1 100644
--- a/src/mainboard/ibase/mb899/cmos.layout
+++ b/src/mainboard/ibase/mb899/cmos.layout
@@ -82,7 +82,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout
index 31f2b20..c280627 100644
--- a/src/mainboard/intel/d945gclf/cmos.layout
+++ b/src/mainboard/intel/d945gclf/cmos.layout
@@ -68,7 +68,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
index 6944664..62d6fd4 100644
--- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
@@ -38,7 +38,7 @@ SPD_SOURCES += empty # 0b1111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/iwave/iWRainbowG6/cmos.layout b/src/mainboard/iwave/iWRainbowG6/cmos.layout
index 0b1845e..e2ff2c5 100644
--- a/src/mainboard/iwave/iWRainbowG6/cmos.layout
+++ b/src/mainboard/iwave/iWRainbowG6/cmos.layout
@@ -75,7 +75,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
index 4d41c60..df722f8 100644
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
+++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl
@@ -49,7 +49,7 @@
Device (SBC3)
{
- /* acpi smbus it should be 0x00040003 if 8131 present */
+ /* ACPI smbus it should be 0x00040003 if 8131 present */
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c
index f677b4e..43d7c16 100644
--- a/src/mainboard/iwill/dk8_htx/fadt.c
+++ b/src/mainboard/iwill/dk8_htx/fadt.c
@@ -7,7 +7,7 @@
#include <console/console.h>
#include <arch/acpi.h>
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
+extern unsigned pm_base; /* pm_base should be set in sb ACPI */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
index 19255fa..25dcab1 100644
--- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c
+++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
@@ -64,7 +64,7 @@ static unsigned get_hcid(unsigned i)
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 9b5b38d..4cf89b1 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -159,5 +159,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_devices();
#endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 24337ef..5646670 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -43,13 +43,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout
index f9fb424..2a99e50 100644
--- a/src/mainboard/kontron/986lcd-m/cmos.layout
+++ b/src/mainboard/kontron/986lcd-m/cmos.layout
@@ -85,7 +85,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/kontron/kt690/fadt.c b/src/mainboard/kontron/kt690/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/kontron/kt690/fadt.c
+++ b/src/mainboard/kontron/kt690/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index a1abfc8..0294c89 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -45,13 +45,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout
index b4b7766..43d2b49 100644
--- a/src/mainboard/lenovo/t400/cmos.layout
+++ b/src/mainboard/lenovo/t400/cmos.layout
@@ -87,7 +87,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 unused
-# ram initialization internal data
+# RAM initialization internal data
1024 128 r 0 read_training_results
# -----------------------------------------------------------------
diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c
index 827f76e..3ce2ed1 100644
--- a/src/mainboard/lenovo/t400/cstates.c
+++ b/src/mainboard/lenovo/t400/cstates.c
@@ -19,12 +19,12 @@
static acpi_cstate_t cst_entries[] = {
{
- /* acpi C1 / cpu C1 */
+ /* ACPI C1 / CPU C1 */
1, 0x01, 1000,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
},
{
- /* acpi C2 / cpu C2 */
+ /* ACPI C2 / CPU C2 */
2, 0x01, 500,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
},
diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout
index e5879d6..5068fac 100644
--- a/src/mainboard/lenovo/t60/cmos.layout
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -74,7 +74,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout
index a00d703..1791897 100644
--- a/src/mainboard/lenovo/x200/cmos.layout
+++ b/src/mainboard/lenovo/x200/cmos.layout
@@ -84,7 +84,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 unused
-# ram initialization internal data
+# RAM initialization internal data
1024 128 r 0 read_training_results
# -----------------------------------------------------------------
diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c
index 827f76e..3ce2ed1 100644
--- a/src/mainboard/lenovo/x200/cstates.c
+++ b/src/mainboard/lenovo/x200/cstates.c
@@ -19,12 +19,12 @@
static acpi_cstate_t cst_entries[] = {
{
- /* acpi C1 / cpu C1 */
+ /* ACPI C1 / CPU C1 */
1, 0x01, 1000,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
},
{
- /* acpi C2 / cpu C2 */
+ /* ACPI C2 / CPU C2 */
2, 0x01, 500,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
},
diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout
index 54a2799..9f10fbc 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -74,7 +74,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
index 345bff8..7c90bd0 100644
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c
@@ -31,13 +31,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c
index 345bff8..7c90bd0 100644
--- a/src/mainboard/lippert/toucan-af/buildOpts.c
+++ b/src/mainboard/lippert/toucan-af/buildOpts.c
@@ -31,13 +31,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/msi/ms7260/resourcemap.c b/src/mainboard/msi/ms7260/resourcemap.c
index a7d520d..f17fadf 100644
--- a/src/mainboard/msi/ms7260/resourcemap.c
+++ b/src/mainboard/msi/ms7260/resourcemap.c
@@ -267,7 +267,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c
index 76fbaa3..610baf3 100644
--- a/src/mainboard/msi/ms9652_fam10/resourcemap.c
+++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c
@@ -269,7 +269,7 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
/* Verified against board configuration registers after normal proprietary BIOS boot */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
index c70cbec..b57f957 100644
--- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
+++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
@@ -79,7 +79,7 @@ static unsigned get_hcid(unsigned i)
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/nvidia/l1_2pvv/resourcemap.c b/src/mainboard/nvidia/l1_2pvv/resourcemap.c
index 2950687..85782b7 100644
--- a/src/mainboard/nvidia/l1_2pvv/resourcemap.c
+++ b/src/mainboard/nvidia/l1_2pvv/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
+// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 01095f6..cfe5beb 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -185,5 +185,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc
index 97373de..324e4aa 100644
--- a/src/mainboard/pcengines/apu1/Makefile.inc
+++ b/src/mainboard/pcengines/apu1/Makefile.inc
@@ -39,7 +39,7 @@ SPD_SOURCES = HYNIX-H5TQ2G83CFR HYNIX-H5TQ4G83MFR
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN): $(SPD_DEPS)
for f in $+; \
do for c in $$(cat $$f | grep -v ^#); \
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index f7d99c0..798b385 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -30,13 +30,13 @@
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-/* Select the cpu family. */
+/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT FALSE
-/* Select the cpu socket type. */
+/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout
index 023bdfa..177bdfe 100644
--- a/src/mainboard/roda/rk886ex/cmos.layout
+++ b/src/mainboard/roda/rk886ex/cmos.layout
@@ -72,7 +72,7 @@ entries
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
-# ram initialization internal data
+# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c
index 6fd4be9..6a9b26c 100644
--- a/src/mainboard/roda/rk886ex/m3885.c
+++ b/src/mainboard/roda/rk886ex/m3885.c
@@ -235,7 +235,7 @@ void m3885_configure_multikey(void)
u8 reg8;
u8 kstate5_flags, offs, maxvars;
- /* ram bank 0 */
+ /* RAM bank 0 */
kstate5_flags = m3885_get_variable(0x0c);
m3885_set_variable(0x0c, kstate5_flags & ~(7 << 4));
@@ -245,7 +245,7 @@ void m3885_configure_multikey(void)
}
- /* ram bank 2 */
+ /* RAM bank 2 */
m3885_set_variable(0x0c, (kstate5_flags & (~(7 << 4))) | (2 << 4));
/* Get the number of variables */
@@ -254,7 +254,7 @@ void m3885_configure_multikey(void)
if (maxvars >= 35) {
offs = m3885_get_variable(0x23);
if ((offs > 0xc0) || (offs < 0x80)) {
- printk(BIOS_DEBUG, "M388x does not have a valid ram offset (0x%x)\n", offs);
+ printk(BIOS_DEBUG, "M388x does not have a valid RAM offset (0x%x)\n", offs);
} else {
printk(BIOS_DEBUG, "Writing Fn-Table to M388x RAM offset 0x%x\n", offs);
for (i=0; i < ARRAY_SIZE(function_ram); i++) {
diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout
index c0ea4fc..3d75784 100644
--- a/src/mainboard/roda/rk9/cmos.layout
+++ b/src/mainboard/roda/rk9/cmos.layout
@@ -74,7 +74,7 @@ entries
#1004 20 r 0 unused
-# ram initialization internal data
+# RAM initialization internal data
1024 128 r 0 read_training_results
# -----------------------------------------------------------------
diff --git a/src/mainboard/roda/rk9/cstates.c b/src/mainboard/roda/rk9/cstates.c
index 827f76e..3ce2ed1 100644
--- a/src/mainboard/roda/rk9/cstates.c
+++ b/src/mainboard/roda/rk9/cstates.c
@@ -19,12 +19,12 @@
static acpi_cstate_t cst_entries[] = {
{
- /* acpi C1 / cpu C1 */
+ /* ACPI C1 / CPU C1 */
1, 0x01, 1000,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 }
},
{
- /* acpi C2 / cpu C2 */
+ /* ACPI C2 / CPU C2 */
2, 0x01, 500,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
},
diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c
index 8e8f10b..395bf4a 100644
--- a/src/mainboard/roda/rk9/mainboard.c
+++ b/src/mainboard/roda/rk9/mainboard.c
@@ -24,7 +24,7 @@
static void ec_setup(void)
{
- /* Thermal limits? Values are from ectool's ram dump. */
+ /* Thermal limits? Values are from ectool's RAM dump. */
ec_write(0xd1, 0x57); /* CPUH */
ec_write(0xd2, 0xc9); /* CPUL */
ec_write(0xd4, 0x64); /* SYSH */
diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc
index 26526c9..85c5e58 100644
--- a/src/mainboard/samsung/lumpy/Makefile.inc
+++ b/src/mainboard/samsung/lumpy/Makefile.inc
@@ -20,7 +20,7 @@ ramstage-y += chromeos.c
SPD_BIN = $(obj)/spd.bin
-# Include spd rom data
+# Include spd ROM data
$(SPD_BIN):
xxd -rg1 $(src)/mainboard/samsung/lumpy/spd.hex >| $@
diff --git a/src/mainboard/siemens/sitemp_g1p1/fadt.c b/src/mainboard/siemens/sitemp_g1p1/fadt.c
index bf06c5d..7d7221d 100644
--- a/src/mainboard/siemens/sitemp_g1p1/fadt.c
+++ b/src/mainboard/siemens/sitemp_g1p1/fadt.c
@@ -25,7 +25,7 @@
#include <../southbridge/amd/sb600/sb600.h>
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c
index a74048b..4ed5746 100644
--- a/src/mainboard/sunw/ultra40/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40/get_bus_conf.c
@@ -188,7 +188,7 @@ void get_bus_conf(void)
/* CK804b */
- if (pci1234[2] & 0xf) { //if the second cpu is installed
+ if (pci1234[2] & 0xf) { //if the second CPU is installed
bus_ck804b_0 = (pci1234[2] >> 16) & 0xff;
#if 0
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09, 0));
diff --git a/src/mainboard/sunw/ultra40m2/get_bus_conf.c b/src/mainboard/sunw/ultra40m2/get_bus_conf.c
index c70cbec..b57f957 100644
--- a/src/mainboard/sunw/ultra40m2/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40m2/get_bus_conf.c
@@ -79,7 +79,7 @@ static unsigned get_hcid(unsigned i)
// we may need more way to find out hcid: subsystem id? GPIO read ?
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
+ // we need use id for 1. bus num, 2. mptable, 3. ACPI table
return id;
}
diff --git a/src/mainboard/sunw/ultra40m2/resourcemap.c b/src/mainboard/sunw/ultra40m2/resourcemap.c
index 5235b0d..30ce9ea 100644
--- a/src/mainboard/sunw/ultra40m2/resourcemap.c
+++ b/src/mainboard/sunw/ultra40m2/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of cpu 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of CPU 0 --> Nvidia MCP55 Pro */
+// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c
index 014c3b6..7a5ce93 100644
--- a/src/mainboard/sunw/ultra40m2/romstage.c
+++ b/src/mainboard/sunw/ultra40m2/romstage.c
@@ -181,5 +181,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/supermicro/h8dme/resourcemap.c b/src/mainboard/supermicro/h8dme/resourcemap.c
index 2c6fef0..22c61f4 100644
--- a/src/mainboard/supermicro/h8dme/resourcemap.c
+++ b/src/mainboard/supermicro/h8dme/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index b48ea46..aeff991 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -204,5 +204,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/supermicro/h8dmr/resourcemap.c b/src/mainboard/supermicro/h8dmr/resourcemap.c
index 2c6fef0..22c61f4 100644
--- a/src/mainboard/supermicro/h8dmr/resourcemap.c
+++ b/src/mainboard/supermicro/h8dmr/resourcemap.c
@@ -265,7 +265,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 96672e9..eb73817 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -181,5 +181,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
index b71448a..b35d3e5 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
@@ -268,7 +268,7 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
// WARD CHANGED
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 1a32abf..bab438e 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- printk(BIOS_DEBUG, "Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as RAM ");
disable_cache_as_ram();
printk(BIOS_DEBUG, "done\n");
diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
index b71448a..b35d3e5 100644
--- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
@@ -268,7 +268,7 @@ static void setup_mb_resource_map(void)
* This field defines the highest bus number in configuration region i
*/
// WARD CHANGED
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
+ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of CPU 0 --> Nvidia MCP55 Pro */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index 071f247..fecb91a 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -97,7 +97,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- printk(BIOS_DEBUG, "Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as RAM ");
disable_cache_as_ram();
printk(BIOS_DEBUG, "done\n");
diff --git a/src/mainboard/technexion/tim5690/fadt.c b/src/mainboard/technexion/tim5690/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/technexion/tim5690/fadt.c
+++ b/src/mainboard/technexion/tim5690/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/technexion/tim8690/fadt.c b/src/mainboard/technexion/tim8690/fadt.c
index 4afb0b9..f9768b2 100644
--- a/src/mainboard/technexion/tim8690/fadt.c
+++ b/src/mainboard/technexion/tim8690/fadt.c
@@ -25,7 +25,7 @@
#include "southbridge/amd/sb600/sb600.h"
/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
+/* pm_base should be set in sb ACPI */
/* pm_base should be got from bar2 of rs690. Here I compact ACPI
* registers into 32 bytes limit.
* */
diff --git a/src/mainboard/traverse/geos/irq_tables.c b/src/mainboard/traverse/geos/irq_tables.c
index 35d5fa6..3e2e1d9 100644
--- a/src/mainboard/traverse/geos/irq_tables.c
+++ b/src/mainboard/traverse/geos/irq_tables.c
@@ -52,7 +52,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth0 */
{0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth1 */
{0x00, (0x0C << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x2, 0x0}, /* xilinx */
diff --git a/src/mainboard/tyan/s2912/resourcemap.c b/src/mainboard/tyan/s2912/resourcemap.c
index f0ae405..9ac7ae4 100644
--- a/src/mainboard/tyan/s2912/resourcemap.c
+++ b/src/mainboard/tyan/s2912/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
+// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 751cf71..c80e2d6 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -184,5 +184,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+ post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c
index a78643a..14e3c53 100644
--- a/src/mainboard/tyan/s2912_fam10/resourcemap.c
+++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c
@@ -265,8 +265,8 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */
+// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index 13b4054..ea877b7 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -106,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- printk(BIOS_DEBUG, "Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as RAM ");
disable_cache_as_ram();
printk(BIOS_DEBUG, "done\n");
diff --git a/src/mainboard/winent/pl6064/irq_tables.c b/src/mainboard/winent/pl6064/irq_tables.c
index 4de63c4..019e713 100644
--- a/src/mainboard/winent/pl6064/irq_tables.c
+++ b/src/mainboard/winent/pl6064/irq_tables.c
@@ -53,7 +53,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
{
/* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x09 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 0*/
{0x00, (0x0A << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1*/
1
0
30 Jul '16
Omar Pakker just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15967
-gerrit
commit 8d8807590358fac9960a7b8bd8259dd7b5e442d2
Author: Omar Pakker <omarpakker+coreboot(a)gmail.com>
Date: Fri Jul 29 19:05:33 2016 +0200
superio/nuvoton: Add Nuvoton NCT6791D
This adds support for Nuvoton NCT6791D Super I/O chips.
Makes use of the common Nuvoton early_serial.c.
Based on the Datasheet supplied by Nuvoton.
Datasheet Version: January 8th, 2016 Revision 1.11
Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40
Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com>
---
src/superio/nuvoton/Kconfig | 4 ++
src/superio/nuvoton/Makefile.inc | 1 +
src/superio/nuvoton/nct6791d/Makefile.inc | 16 +++++
src/superio/nuvoton/nct6791d/nct6791d.h | 58 +++++++++++++++++
src/superio/nuvoton/nct6791d/superio.c | 102 ++++++++++++++++++++++++++++++
5 files changed, 181 insertions(+)
diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig
index ce7db26..4067a41 100644
--- a/src/superio/nuvoton/Kconfig
+++ b/src/superio/nuvoton/Kconfig
@@ -32,3 +32,7 @@ config SUPERIO_NUVOTON_NCT5572D
config SUPERIO_NUVOTON_NCT6779D
bool
select SUPERIO_NUVOTON_COMMON_ROMSTAGE
+
+config SUPERIO_NUVOTON_NCT6791D
+ bool
+ select SUPERIO_NUVOTON_COMMON_ROMSTAGE
diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc
index eb3dd5d..94cc6b7 100644
--- a/src/superio/nuvoton/Makefile.inc
+++ b/src/superio/nuvoton/Makefile.inc
@@ -20,3 +20,4 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d
+subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d
diff --git a/src/superio/nuvoton/nct6791d/Makefile.inc b/src/superio/nuvoton/nct6791d/Makefile.inc
new file mode 100644
index 0000000..db5c620
--- /dev/null
+++ b/src/superio/nuvoton/nct6791d/Makefile.inc
@@ -0,0 +1,16 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += superio.c
diff --git a/src/superio/nuvoton/nct6791d/nct6791d.h b/src/superio/nuvoton/nct6791d/nct6791d.h
new file mode 100644
index 0000000..69855ac
--- /dev/null
+++ b/src/superio/nuvoton/nct6791d/nct6791d.h
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_NUVOTON_NCT6791D_H
+#define SUPERIO_NUVOTON_NCT6791D_H
+
+/* Logical Device Numbers (LDN). */
+#define NCT6791D_PP 0x01 /* Parallel port */
+#define NCT6791D_SP1 0x02 /* UART A */
+#define NCT6791D_SP2 0x03 /* UART B, IR */
+#define NCT6791D_KBC 0x05 /* Keyboard Controller */
+#define NCT6791D_CIR 0x06 /* Consumer IR */
+#define NCT6791D_GPIO678 0x07 /* GPIO 6, 7 & 8 */
+#define NCT6791D_WDT1_WDTMEM_GPIO01 0x08 /* WDT1, WDT_MEM, GPIO 0 & 1 */
+#define NCT6791D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */
+#define NCT6791D_ACPI 0x0A /* ACPI */
+#define NCT6791D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */
+#define NCT6791D_BCLK_WDT2_WDTMEM 0x0D /* BCLK, WDT2, WDT_MEM */
+#define NCT6791D_CIRWUP 0x0E /* CIR Wake-Up */
+#define NCT6791D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */
+#define NCT6791D_PORT80 0x14 /* Port 80 UART */
+#define NCT6791D_DS 0x16 /* Deep Sleep */
+
+/* Virtual LDNs */
+#define NCT6791D_WDT1 ((0 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_WDTMEM ((4 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_GPIOBASE ((3 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_GPIO0 ((1 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_GPIO1 ((7 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_GPIO2 ((0 << 8) | NCT6791D_GPIO2345)
+#define NCT6791D_GPIO3 ((1 << 8) | NCT6791D_GPIO2345)
+#define NCT6791D_GPIO4 ((2 << 8) | NCT6791D_GPIO2345)
+#define NCT6791D_GPIO5 ((3 << 8) | NCT6791D_GPIO2345)
+#define NCT6791D_GPIO6 ((0 << 8) | NCT6791D_GPIO678)
+#define NCT6791D_GPIO7 ((1 << 8) | NCT6791D_GPIO678)
+#define NCT6791D_GPIO8 ((2 << 8) | NCT6791D_GPIO678)
+#define NCT6791D_DS5 ((0 << 8) | NCT6791D_DS)
+#define NCT6791D_DS3 ((1 << 8) | NCT6791D_DS)
+#define NCT6791D_PCHDSW ((3 << 8) | NCT6791D_DS)
+#define NCT6791D_DSWWOPT ((4 << 8) | NCT6791D_DS)
+#define NCT6791D_DS3OPT ((5 << 8) | NCT6791D_DS)
+#define NCT6791D_DSDSS ((6 << 8) | NCT6791D_DS)
+#define NCT6791D_DSPU ((7 << 8) | NCT6791D_DS)
+
+#endif /* SUPERIO_NUVOTON_NCT6791D_H */
diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c
new file mode 100644
index 0000000..0a0f0be
--- /dev/null
+++ b/src/superio/nuvoton/nct6791d/superio.c
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de>
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com>
+ * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "nct6791d.h"
+
+
+static void nct6791d_init(struct device *dev)
+{
+ if (!dev->enabled)
+ return;
+
+ switch (dev->path.pnp.device) {
+ case NCT6791D_KBC:
+ pc_keyboard_init(NO_AUX_DEVICE);
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = nct6791d_init,
+ .ops_pnp_mode = &pnp_conf_mode_8787_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, NCT6791D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_SP1, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_SP2, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
+ {0x0fff, 0}, {0x0fff, 4}, },
+ { &ops, NCT6791D_CIR, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_ACPI},
+ { &ops, NCT6791D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+ {0x0ffe, 0}, {0x0ffe, 4}, },
+ { &ops, NCT6791D_BCLK_WDT2_WDTMEM},
+ { &ops, NCT6791D_CIRWUP, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_GPIO_PP_OD},
+ { &ops, NCT6791D_PORT80},
+ { &ops, NCT6791D_WDT1},
+ { &ops, NCT6791D_WDTMEM},
+ { &ops, NCT6791D_GPIOBASE, PNP_IO0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_GPIO0},
+ { &ops, NCT6791D_GPIO1},
+ { &ops, NCT6791D_GPIO2},
+ { &ops, NCT6791D_GPIO3},
+ { &ops, NCT6791D_GPIO4},
+ { &ops, NCT6791D_GPIO5},
+ { &ops, NCT6791D_GPIO6},
+ { &ops, NCT6791D_GPIO7},
+ { &ops, NCT6791D_GPIO8},
+ { &ops, NCT6791D_DS5},
+ { &ops, NCT6791D_DS3},
+ { &ops, NCT6791D_PCHDSW},
+ { &ops, NCT6791D_DSWWOPT},
+ { &ops, NCT6791D_DS3OPT},
+ { &ops, NCT6791D_DSDSS},
+ { &ops, NCT6791D_DSPU},
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nuvoton_nct6791d_ops = {
+ CHIP_NAME("NUVOTON NCT6791D Super I/O")
+ .enable_dev = enable_dev,
+};
+
1
0
30 Jul '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15986
-gerrit
commit 382d4ffcfe67af1f2b7958a550595740da362e7f
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Sat Jul 30 16:18:46 2016 +0200
src/vboot: Capitalize RAM and CPU
Change-Id: Iff6b1b08b8159588b964d9637b16e1e0bfcca940
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/vboot/Kconfig | 4 ++--
src/vboot/common.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/vboot/Kconfig b/src/vboot/Kconfig
index 6f9e3b9..0c6526f 100644
--- a/src/vboot/Kconfig
+++ b/src/vboot/Kconfig
@@ -91,7 +91,7 @@ config RETURN_FROM_VERSTAGE
help
If this is set, the verstage returns back to the calling stage instead
of exiting to the succeeding stage so that the verstage space can be
- reused by the succeeding stage. This is useful if a ram space is too
+ reused by the succeeding stage. This is useful if a RAM space is too
small to fit both the verstage and the succeeding stage.
config CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL
@@ -108,7 +108,7 @@ config VBOOT_DYNAMIC_WORK_BUFFER
depends on VBOOT
help
This option is used when there isn't enough pre-main memory
- ram to allocate the vboot work buffer. That means vboot verification
+ RAM to allocate the vboot work buffer. That means vboot verification
is after memory init and requires main memory to back the work
buffer.
diff --git a/src/vboot/common.c b/src/vboot/common.c
index 3fa9657..cfdb82a 100644
--- a/src/vboot/common.c
+++ b/src/vboot/common.c
@@ -32,7 +32,7 @@ struct selected_region {
/*
* this is placed at the start of the vboot work buffer. selected_region is used
* for the verstage to return the location of the selected slot. buffer is used
- * by the vboot2 core. Keep the struct cpu architecture agnostic as it crosses
+ * by the vboot2 core. Keep the struct CPU architecture agnostic as it crosses
* stage boundaries.
*/
struct vb2_working_data {
1
0
30 Jul '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15985
-gerrit
commit e9ce1aec768a0352eea6139f705d284afe0634a5
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Sat Jul 30 15:51:13 2016 +0200
src/lib: Capitalize ROM, RAM and CPU
Change-Id: Id0871b0c2eb31e2d728180b44cc5b518b751add4
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/lib/cbmem_console.c | 2 +-
src/lib/selfboot.c | 2 +-
src/lib/thread.c | 2 +-
src/lib/tpm2_tlcl.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
index f399f64..49c11eb 100644
--- a/src/lib/cbmem_console.c
+++ b/src/lib/cbmem_console.c
@@ -41,7 +41,7 @@ static void copy_console_buffer(struct cbmem_console *old_cons_p,
#ifdef __PRE_RAM__
/*
* While running from ROM, before DRAM is initialized, some area in cache as
- * ram space is used for the console buffer storage. The size and location of
+ * RAM space is used for the console buffer storage. The size and location of
* the area are defined by the linker script with _(e)preram_cbmem_console.
*/
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index 8e84a68..2fdf8ce 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -248,7 +248,7 @@ static int build_self_segment_list(
for (current_segment = first_segment;; ++current_segment) {
printk(BIOS_DEBUG,
- "Loading segment from rom address 0x%p\n",
+ "Loading segment from ROM address 0x%p\n",
current_segment);
cbfs_decode_payload_segment(&segment, current_segment);
diff --git a/src/lib/thread.c b/src/lib/thread.c
index 3ddf82f..75d0cfc 100644
--- a/src/lib/thread.c
+++ b/src/lib/thread.c
@@ -43,7 +43,7 @@ static inline int thread_can_yield(const struct thread *t)
return (t != NULL && t->can_yield);
}
-/* Assumes current cpu info can switch. */
+/* Assumes current CPU info can switch. */
static inline struct thread *cpu_info_to_thread(const struct cpu_info *ci)
{
return ci->thread;
diff --git a/src/lib/tpm2_tlcl.c b/src/lib/tpm2_tlcl.c
index 4ac112a..cee1947 100644
--- a/src/lib/tpm2_tlcl.c
+++ b/src/lib/tpm2_tlcl.c
@@ -301,7 +301,7 @@ uint32_t tlcl_define_space(uint32_t space_index, size_t space_size)
nvds_cmd.publicInfo.nvIndex = HR_NV_INDEX + space_index;
nvds_cmd.publicInfo.nameAlg = TPM_ALG_SHA256;
- /* Attributes common for all NV ram spaces used by firmware. */
+ /* Attributes common for all NV RAM spaces used by firmware. */
nvds_cmd.publicInfo.attributes.TPMA_NV_PPWRITE = 1;
nvds_cmd.publicInfo.attributes.TPMA_NV_AUTHREAD = 1;
nvds_cmd.publicInfo.attributes.TPMA_NV_PPREAD = 1;
1
0
Patch set updated for coreboot: src/include: Capitalize CPU, ROM, RAM and APIC
by HAOUAS Elyes 30 Jul '16
by HAOUAS Elyes 30 Jul '16
30 Jul '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15984
-gerrit
commit b508714a0941ea3d57ffb17e261880e505fa72bf
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Sat Jul 30 15:44:17 2016 +0200
src/include: Capitalize CPU, ROM, RAM and APIC
Change-Id: I09ab0564ec1cc837d721d9bc242111bf9d410f81
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/include/cbfs.h | 2 +-
src/include/console/post_codes.h | 6 +++---
src/include/cpu/x86/cache.h | 2 +-
src/include/cpu/x86/lapic.h | 2 +-
src/include/cpu/x86/mp.h | 12 ++++++------
src/include/cpu/x86/msr.h | 2 +-
src/include/cpu/x86/mtrr.h | 2 +-
src/include/cpu/x86/smm.h | 10 +++++-----
src/include/gic.h | 2 +-
src/include/rmodule.h | 2 +-
10 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index 2d19218..6d9dd42 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -23,7 +23,7 @@
* Perform CBFS operations on the boot device. *
***********************************************/
-/* Return mapping of option rom found in boot device. NULL on error. */
+/* Return mapping of option ROM found in boot device. NULL on error. */
void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device);
/* Load stage by name into memory. Returns entry address on success. NULL on
* failure. */
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 8e47905..c7722e5 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -82,14 +82,14 @@
#define POST_ENTRY_C_START 0x13
/**
- * \brief Pre call to ram stage main()
+ * \brief Pre call to RAM stage main()
*
- * POSTed right before ram stage main() is called from c_start.S
+ * POSTed right before RAM stage main() is called from c_start.S
*/
#define POST_PRE_HARDWAREMAIN 0x79
/**
- * \brief Entry into coreboot in ram stage main()
+ * \brief Entry into coreboot in RAM stage main()
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
* ramstage has successfully loaded and started executing.
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index 9c1af29..a446bbe 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -52,7 +52,7 @@ static inline void invd(void)
/* The following functions require the always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
- * ram, the cache as ram stack can no longer be used. Called
+ * ram, the cache as RAM stack can no longer be used. Called
* functions must be inlined to avoid stack usage. Also, the
* compiler must keep local variables register based and not
* allocated them from the stack. With gcc 4.5.0, some functions
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 16bc42d..dfcb4da 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -6,7 +6,7 @@
#include <halt.h>
#include <smp/node.h>
-/* See if I need to initialize the local apic */
+/* See if I need to initialize the local APIC */
#if CONFIG_SMP || CONFIG_IOAPIC
# define NEED_LAPIC 1
#else
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index 9742df0..cea3139 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -59,9 +59,9 @@ struct mp_ops {
void (*get_microcode_info)(const void **microcode, int *parallel);
/*
* Optionally provide a function which adjusts the APIC id
- * map to cpu number. By default the cpu number and APIC id
- * are 1:1. To change the APIC id for a given cpu return the
- * new APIC id. It's called for each cpu as indicated by
+ * map to CPU number. By default the CPU number and APIC id
+ * are 1:1. To change the APIC id for a given CPU return the
+ * new APIC id. It's called for each CPU as indicated by
* get_cpu_count().
*/
int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id);
@@ -78,7 +78,7 @@ struct mp_ops {
void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm);
/*
* Optionally provide a callback prior to the APs starting SMM
- * relocation or cpu driver initialization. However, note that
+ * relocation or CPU driver initialization. However, note that
* this callback is called after SMM handlers have been loaded.
*/
void (*pre_mp_smm_init)(void);
@@ -88,11 +88,11 @@ struct mp_ops {
*/
void (*per_cpu_smm_trigger)(void);
/*
- * This function is called while each cpu is in the SMM relocation
+ * This function is called while each CPU is in the SMM relocation
* handler. Its primary purpose is to adjust the SMBASE for the
* permanent handler. The parameters passed are the current cpu
* running the relocation handler, current SMBASE of relocation handler,
- * and the pre-calculated staggered cpu SMBASE address of the permanent
+ * and the pre-calculated staggered CPU SMBASE address of the permanent
* SMM handler.
*/
void (*relocation_handler)(int cpu, uintptr_t curr_smbase,
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index d644edd..151c9dc 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -48,7 +48,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index,
/* The following functions require the always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
- * ram, the cache as ram stack can no longer be used. Called
+ * ram, the cache as RAM stack can no longer be used. Called
* functions must be inlined to avoid stack usage. Also, the
* compiler must keep local variables register based and not
* allocated them from the stack. With gcc 4.5.0, some functions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index d09c77e..f32bece 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -91,7 +91,7 @@ int get_free_var_mtrr(void);
(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
#define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
-/* At the end of romstage, low ram 0..CACHE_TM_RAMTOP may be set
+/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set
* as write-back cacheable to speed up ramstage decompression.
* Note MTRR boundaries, must be power of two.
*/
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 2b13f8c..9d7e6a1 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -491,8 +491,8 @@ u16 smm_get_pmbase(void);
struct smm_runtime {
u32 smbase;
u32 save_state_size;
- /* The apic_id_to_cpu provides a mapping from APIC id to cpu number.
- * The cpu number is indicated by the index into the array by matching
+ /* The apic_id_to_cpu provides a mapping from APIC id to CPU number.
+ * The CPU number is indicated by the index into the array by matching
* the default APIC id and value at the index. The stub loader
* initializes this array with a 1:1 mapping. If the APIC ids are not
* contiguous like the 1:1 mapping it is up to the caller of the stub
@@ -525,7 +525,7 @@ void *smm_get_save_state(int cpu);
/* The smm_loader_params structure provides direction to the SMM loader:
* - stack_top - optional external stack provided to loader. It must be at
* least per_cpu_stack_size * num_concurrent_stacks in size.
- * - per_cpu_stack_size - stack size per cpu for smm modules.
+ * - per_cpu_stack_size - stack size per CPU for smm modules.
* - num_concurrent_stacks - number of concurrent cpus in handler needing stack
* optional for setting up relocation handler.
* - per_cpu_save_state_size - the smm save state size per cpu
@@ -537,8 +537,8 @@ void *smm_get_save_state(int cpu);
* the address of the module's parameters (if present).
* - runtime - this field is a result only. The SMM runtime location is filled
* into this field so the code doing the loading can manipulate the
- * runtime's assumptions. e.g. updating the apic id to cpu map to
- * handle sparse apic id space.
+ * runtime's assumptions. e.g. updating the APIC id to CPU map to
+ * handle sparse APIC id space.
*/
struct smm_loader_params {
void *stack_top;
diff --git a/src/include/gic.h b/src/include/gic.h
index 1ac1eab..f7339a4 100644
--- a/src/include/gic.h
+++ b/src/include/gic.h
@@ -26,7 +26,7 @@ void gic_enable(void);
/* Return a pointer to the base of the GIC distributor mmio region. */
void *gicd_base(void);
-/* Return a pointer to the base of the GIC cpu mmio region. */
+/* Return a pointer to the base of the GIC CPU mmio region. */
void *gicc_base(void);
#else /* CONFIG_GIC */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index c0c062c..c5de9c3 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -40,7 +40,7 @@ int rmodule_load_alignment(const struct rmodule *m);
/* rmodule_calc_region() calculates the region size, offset to place an
* rmodule in memory, and load address offset based off of a region allocator
* with an alignment of region_alignment. This function helps place an rmodule
- * in the same location in ram it will run from. The offset to place the
+ * in the same location in RAM it will run from. The offset to place the
* rmodule into the region allocated of size region_size is returned. The
* load_offset is the address to load and relocate the rmodule.
* region_alignment must be a power of 2. */
1
0
New patch to review for coreboot: src/include: Capitalize CPU, RAM and APIC
by HAOUAS Elyes 30 Jul '16
by HAOUAS Elyes 30 Jul '16
30 Jul '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15984
-gerrit
commit bd18f8b2ff25d661bf2ebda689be244286c6e073
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Sat Jul 30 15:44:17 2016 +0200
src/include: Capitalize CPU, RAM and APIC
Change-Id: I09ab0564ec1cc837d721d9bc242111bf9d410f81
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/include/cbfs.h | 2 +-
src/include/console/post_codes.h | 6 +++---
src/include/cpu/x86/cache.h | 2 +-
src/include/cpu/x86/lapic.h | 2 +-
src/include/cpu/x86/mp.h | 12 ++++++------
src/include/cpu/x86/msr.h | 2 +-
src/include/cpu/x86/mtrr.h | 2 +-
src/include/cpu/x86/smm.h | 10 +++++-----
src/include/gic.h | 2 +-
src/include/rmodule.h | 2 +-
10 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index 2d19218..6d9dd42 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -23,7 +23,7 @@
* Perform CBFS operations on the boot device. *
***********************************************/
-/* Return mapping of option rom found in boot device. NULL on error. */
+/* Return mapping of option ROM found in boot device. NULL on error. */
void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device);
/* Load stage by name into memory. Returns entry address on success. NULL on
* failure. */
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 8e47905..c7722e5 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -82,14 +82,14 @@
#define POST_ENTRY_C_START 0x13
/**
- * \brief Pre call to ram stage main()
+ * \brief Pre call to RAM stage main()
*
- * POSTed right before ram stage main() is called from c_start.S
+ * POSTed right before RAM stage main() is called from c_start.S
*/
#define POST_PRE_HARDWAREMAIN 0x79
/**
- * \brief Entry into coreboot in ram stage main()
+ * \brief Entry into coreboot in RAM stage main()
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
* ramstage has successfully loaded and started executing.
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index 9c1af29..a446bbe 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -52,7 +52,7 @@ static inline void invd(void)
/* The following functions require the always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
- * ram, the cache as ram stack can no longer be used. Called
+ * ram, the cache as RAM stack can no longer be used. Called
* functions must be inlined to avoid stack usage. Also, the
* compiler must keep local variables register based and not
* allocated them from the stack. With gcc 4.5.0, some functions
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 16bc42d..dfcb4da 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -6,7 +6,7 @@
#include <halt.h>
#include <smp/node.h>
-/* See if I need to initialize the local apic */
+/* See if I need to initialize the local APIC */
#if CONFIG_SMP || CONFIG_IOAPIC
# define NEED_LAPIC 1
#else
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index 9742df0..cea3139 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -59,9 +59,9 @@ struct mp_ops {
void (*get_microcode_info)(const void **microcode, int *parallel);
/*
* Optionally provide a function which adjusts the APIC id
- * map to cpu number. By default the cpu number and APIC id
- * are 1:1. To change the APIC id for a given cpu return the
- * new APIC id. It's called for each cpu as indicated by
+ * map to CPU number. By default the CPU number and APIC id
+ * are 1:1. To change the APIC id for a given CPU return the
+ * new APIC id. It's called for each CPU as indicated by
* get_cpu_count().
*/
int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id);
@@ -78,7 +78,7 @@ struct mp_ops {
void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm);
/*
* Optionally provide a callback prior to the APs starting SMM
- * relocation or cpu driver initialization. However, note that
+ * relocation or CPU driver initialization. However, note that
* this callback is called after SMM handlers have been loaded.
*/
void (*pre_mp_smm_init)(void);
@@ -88,11 +88,11 @@ struct mp_ops {
*/
void (*per_cpu_smm_trigger)(void);
/*
- * This function is called while each cpu is in the SMM relocation
+ * This function is called while each CPU is in the SMM relocation
* handler. Its primary purpose is to adjust the SMBASE for the
* permanent handler. The parameters passed are the current cpu
* running the relocation handler, current SMBASE of relocation handler,
- * and the pre-calculated staggered cpu SMBASE address of the permanent
+ * and the pre-calculated staggered CPU SMBASE address of the permanent
* SMM handler.
*/
void (*relocation_handler)(int cpu, uintptr_t curr_smbase,
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index d644edd..151c9dc 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -48,7 +48,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index,
/* The following functions require the always_inline due to AMD
* function STOP_CAR_AND_CPU that disables cache as
- * ram, the cache as ram stack can no longer be used. Called
+ * ram, the cache as RAM stack can no longer be used. Called
* functions must be inlined to avoid stack usage. Also, the
* compiler must keep local variables register based and not
* allocated them from the stack. With gcc 4.5.0, some functions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index d09c77e..f32bece 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -91,7 +91,7 @@ int get_free_var_mtrr(void);
(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
#define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
-/* At the end of romstage, low ram 0..CACHE_TM_RAMTOP may be set
+/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set
* as write-back cacheable to speed up ramstage decompression.
* Note MTRR boundaries, must be power of two.
*/
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 2b13f8c..9d7e6a1 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -491,8 +491,8 @@ u16 smm_get_pmbase(void);
struct smm_runtime {
u32 smbase;
u32 save_state_size;
- /* The apic_id_to_cpu provides a mapping from APIC id to cpu number.
- * The cpu number is indicated by the index into the array by matching
+ /* The apic_id_to_cpu provides a mapping from APIC id to CPU number.
+ * The CPU number is indicated by the index into the array by matching
* the default APIC id and value at the index. The stub loader
* initializes this array with a 1:1 mapping. If the APIC ids are not
* contiguous like the 1:1 mapping it is up to the caller of the stub
@@ -525,7 +525,7 @@ void *smm_get_save_state(int cpu);
/* The smm_loader_params structure provides direction to the SMM loader:
* - stack_top - optional external stack provided to loader. It must be at
* least per_cpu_stack_size * num_concurrent_stacks in size.
- * - per_cpu_stack_size - stack size per cpu for smm modules.
+ * - per_cpu_stack_size - stack size per CPU for smm modules.
* - num_concurrent_stacks - number of concurrent cpus in handler needing stack
* optional for setting up relocation handler.
* - per_cpu_save_state_size - the smm save state size per cpu
@@ -537,8 +537,8 @@ void *smm_get_save_state(int cpu);
* the address of the module's parameters (if present).
* - runtime - this field is a result only. The SMM runtime location is filled
* into this field so the code doing the loading can manipulate the
- * runtime's assumptions. e.g. updating the apic id to cpu map to
- * handle sparse apic id space.
+ * runtime's assumptions. e.g. updating the APIC id to CPU map to
+ * handle sparse APIC id space.
*/
struct smm_loader_params {
void *stack_top;
diff --git a/src/include/gic.h b/src/include/gic.h
index 1ac1eab..f7339a4 100644
--- a/src/include/gic.h
+++ b/src/include/gic.h
@@ -26,7 +26,7 @@ void gic_enable(void);
/* Return a pointer to the base of the GIC distributor mmio region. */
void *gicd_base(void);
-/* Return a pointer to the base of the GIC cpu mmio region. */
+/* Return a pointer to the base of the GIC CPU mmio region. */
void *gicc_base(void);
#else /* CONFIG_GIC */
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index c0c062c..c5de9c3 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -40,7 +40,7 @@ int rmodule_load_alignment(const struct rmodule *m);
/* rmodule_calc_region() calculates the region size, offset to place an
* rmodule in memory, and load address offset based off of a region allocator
* with an alignment of region_alignment. This function helps place an rmodule
- * in the same location in ram it will run from. The offset to place the
+ * in the same location in RAM it will run from. The offset to place the
* rmodule into the region allocated of size region_size is returned. The
* load_offset is the address to load and relocate the rmodule.
* region_alignment must be a power of 2. */
1
0
New patch to review for coreboot: src/drivers: Capitalize CPU, RAM and ACPI
by HAOUAS Elyes 30 Jul '16
by HAOUAS Elyes 30 Jul '16
30 Jul '16
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15983
-gerrit
commit 23ccee526f21d99ee0261f58c548ef667c22577e
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Sat Jul 30 15:37:26 2016 +0200
src/drivers: Capitalize CPU, RAM and ACPI
Change-Id: I720469ea1df75544f5b1e0cab718502d8a9cf197
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/drivers/i2c/w83795/w83795.c | 2 +-
src/drivers/intel/fsp1_1/cache_as_ram.inc | 2 +-
src/drivers/intel/fsp1_1/car.c | 4 ++--
src/drivers/intel/fsp1_1/include/fsp/car.h | 2 +-
src/drivers/intel/fsp1_1/include/fsp/gma.h | 2 +-
src/drivers/intel/fsp1_1/romstage.c | 2 +-
src/drivers/pc80/vga/vga.c | 2 +-
7 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c
index 78397ba..24da12c 100644
--- a/src/drivers/i2c/w83795/w83795.c
+++ b/src/drivers/i2c/w83795/w83795.c
@@ -361,7 +361,7 @@ static void w83795_hwm_init(struct device *dev)
info = cpu_info();
cpu = info->cpu;
if (!cpu)
- die("CPU: missing cpu device structure");
+ die("CPU: missing CPU device structure");
if (cpu->vendor == X86_VENDOR_AMD)
w83795_init(dev, THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI);
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 6e7e50b..6611fa1 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -154,7 +154,7 @@ before_romstage:
call cache_as_ram_main
/* One will never return from cache_as_ram_main() in verstage so there's
- * no such thing as after ram init. */
+ * no such thing as after RAM init. */
#if !ENV_VERSTAGE
#include "after_raminit.S"
#endif
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index b525a62..7eceebf 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -69,7 +69,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
set_fih_car(car_params->fih);
- /* Return new stack value in ram back to assembly stub. */
+ /* Return new stack value in RAM back to assembly stub. */
return cache_as_ram_stage_main(car_params->fih);
}
@@ -93,7 +93,7 @@ asmlinkage void *romstage_after_verstage(void)
set_fih_car(fih);
- /* Return new stack value in ram back to assembly stub. */
+ /* Return new stack value in RAM back to assembly stub. */
return cache_as_ram_stage_main(fih);
}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
index 56400a7..88dca9a 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -34,7 +34,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
asmlinkage void after_cache_as_ram(void *chipset_context);
asmlinkage void *romstage_after_verstage(void);
/* Per stage calls from the above two functions. The void * return from
- * cache_as_ram_stage_main() is the stack pointer to use in ram after
+ * cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */
void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih);
void after_cache_as_ram_stage(void);
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gma.h b/src/drivers/intel/fsp1_1/include/fsp/gma.h
index 8797932..f5ca2e6 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/gma.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/gma.h
@@ -52,7 +52,7 @@ typedef struct {
#define SBIOS_VERSION_SIZE 32
-/* mailbox 1: public acpi methods */
+/* mailbox 1: public ACPI methods */
typedef struct {
u32 drdy;
u32 csts;
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index b5d90c3..a95e5e6 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -51,7 +51,7 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
timestamp_add_now(TS_START_ROMSTAGE);
- /* Load microcode before ram init */
+ /* Load microcode before RAM init */
if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c
index 740910c..6e225e9 100644
--- a/src/drivers/pc80/vga/vga.c
+++ b/src/drivers/pc80/vga/vga.c
@@ -53,7 +53,7 @@ vga_fb_init(void)
vga_gr_write(0x07, 0x00);
vga_gr_write(0x08, 0xFF);
- /* o/e enable: ram enable */
+ /* o/e enable: RAM enable */
vga_misc_mask(0x22, 0x22);
}
1
0
30 Jul '16
Omar Pakker just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15967
-gerrit
commit ab889eb8f3f44d9a452477a4325314d5fef5a7f2
Author: Omar Pakker <omarpakker+coreboot(a)gmail.com>
Date: Fri Jul 29 19:05:33 2016 +0200
superio/nuvoton: Add Nuvoton NCT6791D
This adds support for Nuvoton NCT6791D Super I/O chips.
Makes use of the common Nuvoton early_serial.c.
Based on the Datasheet supplied by Nuvoton.
Datasheet Version: January 8th, 2016 Revision 1.11
Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40
Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com>
---
src/superio/nuvoton/Kconfig | 4 ++
src/superio/nuvoton/Makefile.inc | 1 +
src/superio/nuvoton/nct6791d/Makefile.inc | 16 +++++
src/superio/nuvoton/nct6791d/nct6791d.h | 58 ++++++++++++++++
src/superio/nuvoton/nct6791d/superio.c | 106 ++++++++++++++++++++++++++++++
5 files changed, 185 insertions(+)
diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig
index ce7db26..4067a41 100644
--- a/src/superio/nuvoton/Kconfig
+++ b/src/superio/nuvoton/Kconfig
@@ -32,3 +32,7 @@ config SUPERIO_NUVOTON_NCT5572D
config SUPERIO_NUVOTON_NCT6779D
bool
select SUPERIO_NUVOTON_COMMON_ROMSTAGE
+
+config SUPERIO_NUVOTON_NCT6791D
+ bool
+ select SUPERIO_NUVOTON_COMMON_ROMSTAGE
diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc
index eb3dd5d..94cc6b7 100644
--- a/src/superio/nuvoton/Makefile.inc
+++ b/src/superio/nuvoton/Makefile.inc
@@ -20,3 +20,4 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d
+subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d
diff --git a/src/superio/nuvoton/nct6791d/Makefile.inc b/src/superio/nuvoton/nct6791d/Makefile.inc
new file mode 100644
index 0000000..db5c620
--- /dev/null
+++ b/src/superio/nuvoton/nct6791d/Makefile.inc
@@ -0,0 +1,16 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += superio.c
diff --git a/src/superio/nuvoton/nct6791d/nct6791d.h b/src/superio/nuvoton/nct6791d/nct6791d.h
new file mode 100644
index 0000000..69855ac
--- /dev/null
+++ b/src/superio/nuvoton/nct6791d/nct6791d.h
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_NUVOTON_NCT6791D_H
+#define SUPERIO_NUVOTON_NCT6791D_H
+
+/* Logical Device Numbers (LDN). */
+#define NCT6791D_PP 0x01 /* Parallel port */
+#define NCT6791D_SP1 0x02 /* UART A */
+#define NCT6791D_SP2 0x03 /* UART B, IR */
+#define NCT6791D_KBC 0x05 /* Keyboard Controller */
+#define NCT6791D_CIR 0x06 /* Consumer IR */
+#define NCT6791D_GPIO678 0x07 /* GPIO 6, 7 & 8 */
+#define NCT6791D_WDT1_WDTMEM_GPIO01 0x08 /* WDT1, WDT_MEM, GPIO 0 & 1 */
+#define NCT6791D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */
+#define NCT6791D_ACPI 0x0A /* ACPI */
+#define NCT6791D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */
+#define NCT6791D_BCLK_WDT2_WDTMEM 0x0D /* BCLK, WDT2, WDT_MEM */
+#define NCT6791D_CIRWUP 0x0E /* CIR Wake-Up */
+#define NCT6791D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */
+#define NCT6791D_PORT80 0x14 /* Port 80 UART */
+#define NCT6791D_DS 0x16 /* Deep Sleep */
+
+/* Virtual LDNs */
+#define NCT6791D_WDT1 ((0 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_WDTMEM ((4 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_GPIOBASE ((3 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_GPIO0 ((1 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_GPIO1 ((7 << 8) | NCT6791D_WDT1_WDTMEM_GPIO01)
+#define NCT6791D_GPIO2 ((0 << 8) | NCT6791D_GPIO2345)
+#define NCT6791D_GPIO3 ((1 << 8) | NCT6791D_GPIO2345)
+#define NCT6791D_GPIO4 ((2 << 8) | NCT6791D_GPIO2345)
+#define NCT6791D_GPIO5 ((3 << 8) | NCT6791D_GPIO2345)
+#define NCT6791D_GPIO6 ((0 << 8) | NCT6791D_GPIO678)
+#define NCT6791D_GPIO7 ((1 << 8) | NCT6791D_GPIO678)
+#define NCT6791D_GPIO8 ((2 << 8) | NCT6791D_GPIO678)
+#define NCT6791D_DS5 ((0 << 8) | NCT6791D_DS)
+#define NCT6791D_DS3 ((1 << 8) | NCT6791D_DS)
+#define NCT6791D_PCHDSW ((3 << 8) | NCT6791D_DS)
+#define NCT6791D_DSWWOPT ((4 << 8) | NCT6791D_DS)
+#define NCT6791D_DS3OPT ((5 << 8) | NCT6791D_DS)
+#define NCT6791D_DSDSS ((6 << 8) | NCT6791D_DS)
+#define NCT6791D_DSPU ((7 << 8) | NCT6791D_DS)
+
+#endif /* SUPERIO_NUVOTON_NCT6791D_H */
diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c
new file mode 100644
index 0000000..04c703f
--- /dev/null
+++ b/src/superio/nuvoton/nct6791d/superio.c
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de>
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com>
+ * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "nct6791d.h"
+
+
+static void nct6791d_init(struct device *dev)
+{
+ if (!dev->enabled)
+ return;
+
+ switch (dev->path.pnp.device) {
+ case NCT6791D_KBC:
+ pc_keyboard_init(NO_AUX_DEVICE);
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = nct6791d_init,
+ .ops_pnp_mode = &pnp_conf_mode_8787_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, NCT6791D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_SP1, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_SP2, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
+ {0x0fff, 0}, {0x0fff, 4}, },
+ { &ops, NCT6791D_CIR, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_GPIO678},
+ { &ops, NCT6791D_WDT1_WDTMEM_GPIO01},
+ { &ops, NCT6791D_GPIO2345},
+ { &ops, NCT6791D_ACPI},
+ { &ops, NCT6791D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+ {0x0ffe, 0}, {0x0ffe, 4}, },
+ { &ops, NCT6791D_BCLK_WDT2_WDTMEM},
+ { &ops, NCT6791D_CIRWUP, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_GPIO_PP_OD},
+ { &ops, NCT6791D_PORT80},
+ { &ops, NCT6791D_DS},
+ { &ops, NCT6791D_WDT1},
+ { &ops, NCT6791D_WDTMEM},
+ { &ops, NCT6791D_GPIOBASE, PNP_IO0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6791D_GPIO0},
+ { &ops, NCT6791D_GPIO1},
+ { &ops, NCT6791D_GPIO2},
+ { &ops, NCT6791D_GPIO3},
+ { &ops, NCT6791D_GPIO4},
+ { &ops, NCT6791D_GPIO5},
+ { &ops, NCT6791D_GPIO6},
+ { &ops, NCT6791D_GPIO7},
+ { &ops, NCT6791D_GPIO8},
+ { &ops, NCT6791D_DS5},
+ { &ops, NCT6791D_DS3},
+ { &ops, NCT6791D_PCHDSW},
+ { &ops, NCT6791D_DSWWOPT},
+ { &ops, NCT6791D_DS3OPT},
+ { &ops, NCT6791D_DSDSS},
+ { &ops, NCT6791D_DSPU},
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nuvoton_nct6791d_ops = {
+ CHIP_NAME("NUVOTON NCT6791D Super I/O")
+ .enable_dev = enable_dev,
+};
+
1
0