coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

1 participants
1820 discussions

New patch to review for coreboot: intel/apollolake: Enable upper CMOS bank in bootblock
by Furquan Shaikh 31 Jul '16

31 Jul '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15998 -gerrit commit 138bd5deebd6e311be9ea1ae251f7e7d6eb465ab Author: Furquan Shaikh <furquan(a)google.com> Date: Sat Jul 30 18:06:23 2016 -0700 intel/apollolake: Enable upper CMOS bank in bootblock Upper CMOS bank is used to store the boot count. It is important to enable it as soon as possible in bootblock. BUG=chrome-os-partner:55473 Change-Id: I7c4f49c337c2e24a93c1e71466e2f66db04be562 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/bootblock/bootblock.c | 10 ++++++++++ src/soc/intel/apollolake/include/soc/iosf.h | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 31144ff..3015d17 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -22,6 +22,7 @@ #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/gpio.h> +#include <soc/iosf.h> #include <soc/mmap_boot.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> @@ -56,6 +57,13 @@ static void enable_pm_timer(void) wrmsr(MSR_EMULATE_PM_TMR, msr); } +static void enable_cmos_upper_bank(void) +{ + uint32_t reg = iosf_read(IOSF_RTC_PORT_ID, RTC_CONFIG); + reg |= RTC_CONFIG_UCMOS_ENABLE; + iosf_write(IOSF_RTC_PORT_ID, RTC_CONFIG, reg); +} + void asmlinkage bootblock_c_entry(uint64_t base_timestamp) { device_t dev = NB_DEV_ROOT; @@ -82,6 +90,8 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp) pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); + enable_cmos_upper_bank(); + /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(base_timestamp); } diff --git a/src/soc/intel/apollolake/include/soc/iosf.h b/src/soc/intel/apollolake/include/soc/iosf.h index eeb9330..ae3e8ec 100644 --- a/src/soc/intel/apollolake/include/soc/iosf.h +++ b/src/soc/intel/apollolake/include/soc/iosf.h @@ -20,6 +20,10 @@ #include <arch/io.h> +#define IOSF_RTC_PORT_ID 0xD1 +#define RTC_CONFIG 0x3400 +#define RTC_CONFIG_UCMOS_ENABLE (1 << 2) + inline static void iosf_write(uint16_t port, uint16_t reg, uint32_t val) { uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3);

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New patch to review for coreboot: elog: Include declarations for boot count functions unconditionally
by Furquan Shaikh 31 Jul '16

31 Jul '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15997 -gerrit commit b23075727d665462f3926a942b1169f3574c29ca Author: Furquan Shaikh <furquan(a)google.com> Date: Sat Jul 30 11:19:13 2016 -0700 elog: Include declarations for boot count functions unconditionally There is no need to add guards around boot_count_* functions since the static definition of boot_count_read is anyways unused. BUG=chrome-os-partner:55473 Change-Id: I553277cdc09a8af420ecf7caefcb59bc3dcb28f1 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/include/elog.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/include/elog.h b/src/include/elog.h index b94a281..3f949bf 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -171,11 +171,7 @@ static inline int elog_smbios_write_type15(unsigned long *current, extern u32 gsmi_exec(u8 command, u32 *param); -#if CONFIG_ELOG_BOOT_COUNT u32 boot_count_read(void); u32 boot_count_increment(void); -#else -static inline u32 boot_count_read(void) { return 0; } -#endif /* CONFIG_ELOG_BOOT_COUNT */ #endif /* ELOG_H_ */

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Patch set updated for coreboot: drivers/fsp2_0: Increment boot count for non-S3 boot
by Furquan Shaikh 31 Jul '16

31 Jul '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15948 -gerrit commit dc44ab5db7aa4d2b46116d0f65b041e9163d4ec1 Author: Furquan Shaikh <furquan(a)google.com> Date: Sat Jul 30 18:10:05 2016 -0700 drivers/fsp2_0: Increment boot count for non-S3 boot If ELOG_BOOT_COUNT is enabled and the boot is not s3 resume, then increment boot count. BUG=chrome-os-partner:55473 Change-Id: Ib3e77180bd640ec0424978e73034d7c99cdcba95 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/drivers/intel/fsp2_0/memory_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 8e3eb68..f07975e 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -17,6 +17,7 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include <elog.h> #include <fsp/api.h> #include <fsp/util.h> #include <memrange.h> @@ -300,6 +301,9 @@ enum fsp_status fsp_memory_init(bool s3wake) struct memranges memmap; struct range_entry freeranges[2]; + if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake) + boot_count_increment(); + if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); return FSP_NOT_FOUND;

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Patch set updated for coreboot: arch/riscv: Add include/arch/barrier.h
by Jonathan Neuschäfer 31 Jul '16

31 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15830 -gerrit commit a8c46ff458e2cf6f5788e553ffff1f73b067c5c8 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Tue Jul 26 01:54:34 2016 +0200 arch/riscv: Add include/arch/barrier.h mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/include/arch/barrier.h | 39 ++++++++++++++++++++++++ src/arch/riscv/include/atomic.h | 1 - src/arch/riscv/virtual_memory.c | 5 +-- src/mainboard/emulation/qemu-riscv/qemu_util.c | 5 +-- src/mainboard/emulation/spike-riscv/spike_util.c | 1 + 5 files changed, 46 insertions(+), 5 deletions(-) diff --git a/src/arch/riscv/include/arch/barrier.h b/src/arch/riscv/include/arch/barrier.h new file mode 100644 index 0000000..257e2a2 --- /dev/null +++ b/src/arch/riscv/include/arch/barrier.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef __ARCH_BARRIER_H_ +#define __ARCH_BARRIER_H__ + +static inline void mb(void) { asm volatile("fence"); } +static inline void rmb(void) { asm volatile("fence"); } +static inline void wmb(void) { asm volatile("fence"); } + +#endif /* __ARCH_BARRIER_H__ */ diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h index df455b9..8f10b9d 100644 --- a/src/arch/riscv/include/atomic.h +++ b/src/arch/riscv/include/atomic.h @@ -36,7 +36,6 @@ typedef struct { int lock; } spinlock_t; #define SPINLOCK_INIT {0} -#define mb() __sync_synchronize() #define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val) #define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr)) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index cda9057..f0cd5f6 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -14,11 +14,12 @@ * GNU General Public License for more details. */ -#include <vm.h> +#include <arch/barrier.h> #include <arch/encoding.h> #include <atomic.h> -#include <stdint.h> #include <console/console.h> +#include <stdint.h> +#include <vm.h> pte_t* root_page_table; diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c index fca7d56..3c2941c 100644 --- a/src/mainboard/emulation/qemu-riscv/qemu_util.c +++ b/src/mainboard/emulation/qemu-riscv/qemu_util.c @@ -25,11 +25,12 @@ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. */ -#include <spike_util.h> +#include <arch/barrier.h> #include <arch/errno.h> #include <atomic.h> -#include <string.h> #include <console/console.h> +#include <spike_util.h> +#include <string.h> uintptr_t translate_address(uintptr_t vAddr) { // TODO: implement the page table translation algorithm diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index 358cb44..f0f5301 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -26,6 +26,7 @@ */ #include <spike_util.h> +#include <arch/barrier.h> #include <arch/errno.h> #include <atomic.h> #include <string.h>

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New patch to review for coreboot: soc/intel/quark: Make ramstage relocatable
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15994 -gerrit commit 0dad61473e6c07e5be79509611546aec176f36dc Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 14:14:02 2016 -0700 soc/intel/quark: Make ramstage relocatable Relocate ramstage into CBMEM. TEST=Build and run on Galileo Gen2 Change-Id: I38861f2af4b7b976c7ebb7226d81242f950981e3 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2b6a0eb..b2473dc 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS select C_ENVIRONMENT_BOOTBLOCK select HAVE_HARD_RESET select REG_SCRIPT + select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON select SOC_SETS_MSRS select TSC_CONSTANT_RATE

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New patch to review for coreboot: mainboard/intel/galileo: Enable BOOTBLOCK_CONSOLE
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15993 -gerrit commit 02c2adb6748b2922a73535173bcb9356a7dce85c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 11:51:28 2016 -0700 mainboard/intel/galileo: Enable BOOTBLOCK_CONSOLE Turn on debug serial output for the boot block. TEST=Build and run on Galileo Gen2 Change-Id: I40ce71e802e9da8de6a23259afb84017a16b6e74 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index b0c69e4..cba65ea 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,6 +18,7 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select BOOTBLOCK_CONSOLE select CREATE_BOARD_CHECKLIST select ENABLE_BUILTIN_HSUART1 select HAVE_ACPI_TABLES

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New patch to review for coreboot: soc/intel/quark: Enable use of hard reset
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15992 -gerrit commit 87b1e89259aae42a07c2c59867c59b970dfac485 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 10:34:22 2016 -0700 soc/intel/quark: Enable use of hard reset Select HAVE_HARD_RESET in the KCONFIG file to enable use of the hard_reset routine. TEST=Build and run on Galileo Gen2 Change-Id: Ib11a80b64cf1c55aec24f2576d197da9017b9751 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 116dc9f..2b6a0eb 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP select C_ENVIRONMENT_BOOTBLOCK + select HAVE_HARD_RESET select REG_SCRIPT select SOC_INTEL_COMMON select SOC_SETS_MSRS

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New patch to review for coreboot: arch/x86: Display MTRRs after MTRR update in postcar
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15991 -gerrit commit 64540c713ae8f3b5ff55c23db68eee0e6bba62cb Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 07:34:20 2016 -0700 arch/x86: Display MTRRs after MTRR update in postcar Display the MTRRs after they have been updated during the postcar stage. TEST=Build and run on Galileo Gen2 Change-Id: I1532250cacd363c1eeaf72edc6cb9e9268a11375 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/arch/x86/exit_car.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index a51d662..90715e4 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -108,6 +108,9 @@ _start: wrmsr #endif /* CONFIG_SOC_SETS_MSRS */ + /* Display the MTRRs */ + call soc_display_mtrrs + /* Load and run ramstage. */ call copy_and_run /* Should never return. */

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New patch to review for coreboot: soc/intel/common: Enable MTRR display during bootblock & postcar
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15990 -gerrit commit 27863239ca4021b73cd70a23f081f83b6109f2ca Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 07:17:13 2016 -0700 soc/intel/common: Enable MTRR display during bootblock & postcar Update Makefile.inc to allow MTRR display during bootblock and postcar. TEST=Build and run on Galileo Gen2 Change-Id: If12896df46b9edfc9fff3fab3a12d2dae23517a3 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/common/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 429c61c..13ba21b 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +bootblock-y += util.c + verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c @@ -12,6 +14,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c +postcar-y += util.c + ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c

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New patch to review for coreboot: drivers/intel/fsp2_0: Display FSP calls and status
by Lee Leahy 31 Jul '16

31 Jul '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15989 -gerrit commit d55f09d9bc3ff592ec90a046eb9ad0558813ef4b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:21:13 2016 -0700 drivers/intel/fsp2_0: Display FSP calls and status Disable the chatty FSP behavior for normal builds. Use a Kconfig value to enable the display of the FSP call entry points, the call parameters and the returned status for MemoryInit, SiliconInit and FspNotify. Use inline functions to reduce the impact on the mainline code and compiled results. TEST=Build and run on Galileo Gen2 Change-Id: Iacae66f72bc5b4ba1469f53fcce4669726234441 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 ++ src/drivers/intel/fsp2_0/hand_off_block.c | 5 -- src/drivers/intel/fsp2_0/include/fsp/debug.h | 110 +++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/memory_init.c | 10 +-- src/drivers/intel/fsp2_0/notify.c | 11 +-- src/drivers/intel/fsp2_0/silicon_init.c | 12 +-- 7 files changed, 129 insertions(+), 27 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 01ce75d..7f4bbee 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -27,6 +27,13 @@ config ADD_FSP_BINARIES Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not use the FSP-T binary and it is not added. +config DISPLAY_FSP_CALLS_AND_STATUS + bool "Display the FSP calls and status" + default n + help + Display the FSP call entry point and parameters prior to calling FSP + and display the status upon return from FSP. + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index b7cb981..ce06a82 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -21,11 +21,6 @@ #define HOB_HEADER_LEN 8 -struct hob_header { - uint16_t type; - uint16_t length; -} __attribute__((packed)); - struct hob_resource { uint8_t owner_guid[16]; uint32_t type; diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h new file mode 100644 index 0000000..3fbc609 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_DEBUG_H_ +#define _FSP2_0_DEBUG_H_ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> + +struct hob_header { + uint16_t type; + uint16_t length; +} __attribute__((packed)); + +/*----------- + * MemoryInit + *----------- + */ +typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) + (void *raminit_upd, void **hob_list); + +static inline __attribute__((always_inline)) void fsp_debug_before_memory_init( + fsp_memory_init_fn memory_init, + const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd, + void **hob_list_ptr) +{ + /* Display the call entry point and paramters */ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", + memory_init); + printk(BIOS_SPEW, "\t0x%p: raminit_upd\n", fspm_new_upd); + printk(BIOS_SPEW, "\t0x%p: &hob_list_ptr\n", hob_list_ptr); + } +} + +static inline __attribute__((always_inline)) void fsp_debug_memory_init( + enum fsp_status status, const struct hob_header *hob_list_ptr) +{ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); +} + +/*----------- + * SiliconInit + *----------- + */ +typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) + (void *silicon_upd); + +static inline __attribute__((always_inline)) void fsp_debug_before_silicon_init( + fsp_silicon_init_fn silicon_init, const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd) +{ + /* Display the call to FSP SiliconInit */ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { + printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init); + printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd); + } +} + +static inline __attribute__((always_inline)) void fsp_debug_silicon_init( + enum fsp_status status) +{ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); +} + +/*----------- + * FspNotify + *----------- + */ +struct fsp_notify_params { + enum fsp_notify_phase phase; +}; + +typedef asmlinkage enum fsp_status (*fsp_notify_fn) + (struct fsp_notify_params *); + +static inline __attribute__((always_inline)) void fsp_before_debug_notify( + fsp_notify_fn notify, const struct fsp_notify_params *notify_params) +{ + /* Display the call to FSP SiliconInit */ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { + printk(BIOS_SPEW, "0x%08x: notify_params->phase\n", + notify_params->phase); + printk(BIOS_SPEW, "Calling FspNotify: 0x%p\n", notify); + printk(BIOS_SPEW, "\t0x%p: notify_params\n", notify_params); + } +} + +static inline __attribute__((always_inline)) void fsp_debug_notify( + enum fsp_status status) +{ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status); +} + +#endif /* _FSP2_0_DEBUG_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 01186f7..cc70cc1 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,7 @@ #include <boot/coreboot_tables.h> #include <commonlib/region.h> #include <fsp/api.h> +#include <fsp/debug.h> #include <fsp/info_header.h> #include <memrange.h> diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 8e3eb68..4921e88 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -29,9 +29,6 @@ #include <timestamp.h> #include <vboot/vboot_common.h> -typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) - (void *raminit_upd, void **hob_list); - static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; @@ -221,9 +218,8 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); - printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit); - printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd); - printk(BIOS_SPEW, "\t%p: hob_list ptr\n", &hob_list_ptr); + fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd, + &hob_list_ptr); post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); @@ -231,7 +227,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); - printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + fsp_debug_memory_init(status, hob_list_ptr); /* Handle any resets requested by FSPM. */ fsp_handle_reset(status); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 4e7e9c5..139e172 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -17,13 +17,6 @@ #include <string.h> #include <timestamp.h> -struct fsp_notify_params { - enum fsp_notify_phase phase; -}; - -typedef asmlinkage enum fsp_status (*fsp_notify_fn) - (struct fsp_notify_params *); - enum fsp_status fsp_notify(enum fsp_notify_phase phase) { enum fsp_status ret; @@ -35,8 +28,7 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase) fspnotify = (void*) (fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); - - printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase); + fsp_before_debug_notify(fspnotify, &notify_params); if (phase == AFTER_PCI_ENUM) { timestamp_add_now(TS_FSP_BEFORE_ENUMERATE); @@ -55,6 +47,7 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase) timestamp_add_now(TS_FSP_AFTER_FINALIZE); post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); } + fsp_debug_notify(ret); return ret; } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index c069ff1..b9fea66 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -23,9 +23,6 @@ struct fsp_header fsps_hdr; -typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) - (void *silicon_upd); - static enum fsp_status do_silicon_init(struct fsp_header *hdr) { struct FSPS_UPD upd, *supd; @@ -44,15 +41,18 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(&upd); - timestamp_add_now(TS_FSP_SILICON_INIT_START); - post_code(POST_FSP_SILICON_INIT); + /* Call SiliconInit */ silicon_init = (void *) (hdr->image_base + hdr->silicon_init_entry_offset); + fsp_debug_before_silicon_init(silicon_init, supd, &upd); + + timestamp_add_now(TS_FSP_SILICON_INIT_START); + post_code(POST_FSP_SILICON_INIT); status = silicon_init(&upd); timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_INIT); - printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + fsp_debug_silicon_init(status); /* Handle any resets requested by FSPS. */ fsp_handle_reset(status);

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coreboot-gerrit July 2016